> -----Original Message-----
> From: Nitka, Grzegorz <[email protected]>
> Sent: Tuesday, June 24, 2025 9:22 PM
> To: [email protected]
> Cc: [email protected]; Nguyen, Anthony L
> <[email protected]>; Kitszel, Przemyslaw
> <[email protected]>; Olech, Milena <[email protected]>;
> Korba, Przemyslaw <[email protected]>; Nitka, Grzegorz
> <[email protected]>
> Subject: [PATCH v2 iwl-net] ice: add recovery clock and clock 1588 control for
> E825c
>
> From: Przemyslaw Korba <[email protected]>
>
> Add control for E825 input pins: phy clock recovery and clock 1588.
> E825 does not provide control over platform level DPLL but it
> provides control over PHY clock recovery, and PTP/timestamp driven
> inputs for platform level DPLL.
>
> Introduce a software controlled layer of abstraction to:
> - create a DPLL of type EEC for E825c,
> - create recovered clock pin for each PF, and control them through
> writing to registers,
> - create pin to control clock 1588 for PF0, and control it through
> writing to registers.
>
> Reviewed-by: Milena Olech <[email protected]>
> Co-developed-by: Grzegorz Nitka <[email protected]>
> Signed-off-by: Grzegorz Nitka <[email protected]>
> Signed-off-by: Przemyslaw Korba <[email protected]>
> ---
> v2:
> - rebased, addressed comments from v1 (kdoc updated, removed unrelated
> code changes, fixed undefined 'ret' code in error patchs, use feature
> flag instead of MAC type chacking)
> - use ptp.ptp_port to create pins indexes instead of PF ID
> - removed CLK_OUT/output pins definitions as unused
> - removed redundant dpll_netdev_pin_set call on 1588 pin
> - removed checkpatch warning about SET_PIN_STATE macro (parenthesis
> added)
> ---
> drivers/net/ethernet/intel/ice/ice_dpll.c | 823 ++++++++++++++++++--
> drivers/net/ethernet/intel/ice/ice_dpll.h | 26 +-
> drivers/net/ethernet/intel/ice/ice_lib.c | 3 +
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 35 +-
> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 2 +
> drivers/net/ethernet/intel/ice/ice_tspll.h | 7 +
> drivers/net/ethernet/intel/ice/ice_type.h | 6 +
> 7 files changed, 839 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
> b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index fc9f40aff251..a33b04d549ea 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
> @@ -9,6 +9,7 @@
> #define ICE_CGU_STATE_ACQ_ERR_THRESHOLD 50
> #define ICE_DPLL_PIN_IDX_INVALID 0xff
> #define ICE_DPLL_RCLK_NUM_PER_PF 1
> +#define ICE_DPLL_PIN_1588_NUM 1
> #define ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT 25
> #define ICE_DPLL_PIN_GEN_RCLK_FREQ 1953125
> #define ICE_DPLL_PIN_PRIO_OUTPUT 0xff
> @@ -61,6 +62,7 @@ static const char * const pin_type_name[] = {
>
> static const char * const ice_dpll_sw_pin_sma[] = { "SMA1", "SMA2" };
> static const char * const ice_dpll_sw_pin_ufl[] = { "U.FL1", "U.FL2" };
> +static const char ice_dpll_pin_1588[] = "pin_1588";
>
> static const struct dpll_pin_frequency ice_esync_range[] = {
> DPLL_PIN_FREQUENCY_RANGE(0, DPLL_PIN_FREQUENCY_1_HZ),
> @@ -515,6 +517,107 @@ ice_dpll_pin_disable(struct ice_hw *hw, struct
> ice_dpll_pin *pin,
> return ret;
> }
>
...
> +/**
> + * ice_dpll_init_pin_1588 - initialize pin to control clock 1588
> + * @pf: board private structure
> + * @pin: pin to register
> + * @start_idx: on which index shall allocation start in dpll subsystem
> + * @ops: callback ops registered with the pins
> + *
> + * Allocate resource for clock 1588 pin in dpll subsystem. Register the
> + * pin with the parents it has in the info. Register pin with the pf's main
> vsi
> + * netdev.
> + *
> + * Return:
> + * * 0 - success
> + * * negative - registration failure reason
> + */
> +static int
> +ice_dpll_init_pin_1588(struct ice_pf *pf, struct ice_dpll_pin *pin,
> + int start_idx, const struct dpll_pin_ops *ops)
> +{
> + struct ice_vsi *vsi = ice_get_main_vsi(pf);
> + struct dpll_pin *parent;
> + int ret;
> + u8 i;
> +
> + ret = ice_dpll_get_pins(pf, pin, start_idx, ICE_DPLL_PIN_1588_NUM,
> + pf->dplls.clock_id);
> + if (ret)
> + return ret;
> + for (i = 0; i < pf->dplls.pin_1588.num_parents; i++) {
> + parent = pf->dplls.inputs[pf-
> >dplls.pin_1588.parent_idx[i]].pin;
> + if (!parent) {
> + ret = -ENODEV;
> + goto unregister_pins;
> + }
> + ret = dpll_pin_on_pin_register(parent, pf-
> >dplls.pin_1588.pin,
> + ops, &pf->dplls.pin_1588);
> + if (ret)
> + goto unregister_pins;
> + }
> + if (WARN_ON((!vsi || !vsi->netdev)))
> + return -EINVAL;
> +
Still leftover from v1 (no need to check netdev).
> + return 0;
> +
> +unregister_pins:
> + while (i) {
