> -----Original Message-----
> From: Intel-wired-lan <[email protected]> On Behalf
> Of Grzegorz Nitka
> Sent: Wednesday, April 22, 2026 2:32 PM
> To: [email protected]
> Cc: [email protected]; Kubalewski, Arkadiusz
> <[email protected]>; Nguyen, Anthony L
> <[email protected]>; Kitszel, Przemyslaw
> <[email protected]>
> Subject: [Intel-wired-lan] [PATCH iwl-net 1/2] ice: ptp: serialize
> E825 PHY timer start with PTP lock
>
> ice_start_phy_timer_eth56g() programs TIMETUS registers and issues
> INIT_INCVAL without holding the global PTP semaphore.
>
> This allows concurrent PTP command paths to interleave with PHY timer
> start, which can make the sequence fail and leave timer initialization
> inconsistent.
>
> Take the PTP lock around TIMETUS registers programming and INIT_INCVAL
> command execution, and make sure the lock is released on all error
> paths.
>
> Keep the subsequent sync step outside of this critical section, since
> ice_sync_phy_timer_eth56g() takes the same semaphore internally.
>
> Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C
> products")
> Reviewed-by: Arkadiusz Kubalewski <[email protected]>
> Signed-off-by: Grzegorz Nitka <[email protected]>
I recommend to add Cc: [email protected]
Reviewed-by: Aleksandr Loktionov <[email protected]>
> ---
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> index 672218e5d1f9..8bb94e785f2a 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> @@ -2141,16 +2141,23 @@ int ice_start_phy_timer_eth56g(struct ice_hw
> *hw, u8 port)
> }
> incval = (u64)hi << 32 | lo;
>
> + if (!ice_ptp_lock(hw)) {
> + dev_err(ice_hw_to_dev(hw), "Failed to acquire PTP
> semaphore\n");
> + return -EBUSY;
> + }
> +
> err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
> incval);
> if (err)
> - return err;
> + goto err_ptp_unlock;
>
> err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
> if (err)
> - return err;
> + goto err_ptp_unlock;
>
> ice_ptp_exec_tmr_cmd(hw);
>
> + ice_ptp_unlock(hw);
> +
> err = ice_sync_phy_timer_eth56g(hw, port);
> if (err)
> return err;
> @@ -2166,6 +2173,10 @@ int ice_start_phy_timer_eth56g(struct ice_hw
> *hw, u8 port)
> ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n",
> port);
>
> return 0;
> +
> +err_ptp_unlock:
> + ice_ptp_unlock(hw);
> + return err;
> }
>
> /**
> --
> 2.39.3
