> -----Original Message-----
> From: Intel-wired-lan <[email protected]> On Behalf
> Of Petr Oros
> Sent: Wednesday, April 8, 2026 1:05 PM
> To: [email protected]
> Cc: Kitszel, Przemyslaw <[email protected]>; Eric Dumazet
> <[email protected]>; Kubalewski, Arkadiusz
> <[email protected]>; Andrew Lunn <[email protected]>;
> Nguyen, Anthony L <[email protected]>; Simon Horman
> <[email protected]>; [email protected]; Jakub Kicinski
> <[email protected]>; Paolo Abeni <[email protected]>; David S. Miller
> <[email protected]>; [email protected]
> Subject: [Intel-wired-lan] [PATCH iwl-net v2] ice: fix SMA and U.FL
> pin state changes affecting paired pin
>
> SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and
> SMA2/U.FL2) controlled by the PCA9575 GPIO expander. Each pair can
> only have one active pin at a time: SMA1 output and U.FL1 output share
> the same CGU output, SMA2 input and U.FL2 input share the same CGU
> input. The PCA9575 register bits determine which connector in each
> pair owns the signal path.
>
> The driver does not account for this pairing in two places:
>
> ice_dpll_ufl_pin_state_set() modifies PCA9575 bits and disables the
> backing CGU pin without checking whether the U.FL pin is currently
> active. Disconnecting an already inactive U.FL pin flips bits that
> the paired SMA pin relies on, breaking its connection.
>
> ice_dpll_sma_direction_set() does not propagate direction changes to
> the paired U.FL pin. For SMA2/U.FL2 the ICE_SMA2_UFL2_RX_DIS bit is
> never managed, so U.FL2 stays disconnected after SMA2 switches to
> output. For both pairs the backing CGU pin of the U.FL side is never
> enabled when a direction change activates it, so userspace sees the
> pin as disconnected even though the routing is correct.
>
> Fix by guarding the U.FL disconnect path against inactive pins and by
> updating the paired U.FL pin fully on SMA direction changes: manage
> ICE_SMA2_UFL2_RX_DIS for the SMA2/U.FL2 pair and enable the backing
> CGU pin whenever the peer becomes active.
>
> Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
> Signed-off-by: Petr Oros <[email protected]>
> ---
> v2:
> - fix ice_dpll_sma_direction_set() to manage ICE_SMA2_UFL2_RX_DIS
> when SMA2 direction changes
> - enable paired U.FL backing CGU pin when direction change makes
> it active, so it reports as connected immediately
> - (both reported by Intel test on the SMA init and notification
> patch threads)
> v1: https://lore.kernel.org/all/20260325151050.2081977-1-
> [email protected]/
> ---
> drivers/net/ethernet/intel/ice/ice_dpll.c | 50
> ++++++++++++++++++++++-
> 1 file changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
> b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index 498ec2c045f384..3f8cd5b8298b57 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
> @@ -1171,6 +1171,8 @@ static int ice_dpll_sma_direction_set(struct
> ice_dpll_pin *p,
> enum dpll_pin_direction direction,
> struct netlink_ext_ack *extack) {
...
> data |= ICE_SMA2_UFL2_RX_DIS;
> enable = false;
> } else {
> --
> 2.52.0
Reviewed-by: Aleksandr Loktionov <[email protected]>
