> -----Original Message-----
> From: Anton Vorontsov [mailto:cbouatmai...@gmail.com]
> Sent: Friday, January 13, 2012 8:13 PM
> To: Huang Changming-R66093
> Cc: Chris Ball; linux-mmc@vger.kernel.org
> Subject: Re: [PATCH 4/5 v4] ESDHC: Workaround for data crc error on
> p1010rdb
>
> On Fri, Jan 13, 2012 at 02:37:07AM +0000, Huang Changming-R66093 wrote:
> > Hi, Anton,
> > Could you have any comment about this serial patch?
> >
> > Thanks
> > Jerry Huang
> >
> [...]
> > > @@ -56,6 +56,13 @@ static inline void esdhc_set_clock(struct
> > > sdhci_host *host, unsigned int clock)
> > > if (clock == 0)
> > > goto out;
> > >
> > > + if (host->quirks2 & SDHCI_QUIRK2_RELAX_FREQ) {
> > > + if (clock > 20000000)
> > > + clock -= 5000000;
> > > + if (clock > 40000000)
> > > + clock -= 5000000;
> > > + }
> > > +
>
> That's weird. According to the code, you are underclocking a device (i.e.
> the card actually expects higher clocks).
>
> Did you check (with an oscilloscope) what clocks HW actually generates?
> Maybe it just generates higher than expected clocks, then this code would
> be a correct workaround.
>
> Otherwise, if HW generates correct/precise clock, then you probably would
> rather not permit high clocks at all... but then you limit max freq to 20
> MHz. :-(
>
> Oh well, if the patch works for your HW, I'm fine with it.
>
> Acked-by: Anton Vorontsov <cbouatmai...@gmail.com>
Yes, it is very weird.
Due to the limitation of some FSL platform's eSDHC controller, we must decrease
the bus frequency for some SD card, otherwise, the card can't work correctly.
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