From: "Chai, Chong Yi" <chong.yi.c...@intel.com>
---
features/soc/baytrail/baytrail.scc | 10 +
...spidev_test-to-test-automatic-PIO-DMA-swi.patch | 93 ++++++++
...spidev_test-to-test-modifying-FIFO-trigge.patch | 134 ++++++++++++
...Add-new-ioctl-for-configuring-FIFO-trigge.patch | 112 ++++++++++
...xx-Don-t-use-slave_id-of-dma_slave_config.patch | 240 +++++++++++++++++++++
...Prevent-DMA-from-transferring-too-many-by.patch | 70 ++++++
...auto-switch-between-PIO-and-DMA-with-conf.patch | 106 +++++++++
...change-default-supported-DMA-burst-size-t.patch | 43 ++++
...fix-incorrect-SW-mode-chipselect-setting-.patch | 51 +++++
.../spi-pxa2xx-fix-runtime-PM-enabling-order.patch | 57 +++++
...pi-pxa2xx-remove-unnecessary-OOM-messages.patch | 50 +++++
11 files changed, 966 insertions(+)
create mode 100644
features/soc/baytrail/spi-modify-spidev_test-to-test-automatic-PIO-DMA-swi.patch
create mode 100644
features/soc/baytrail/spi-modify-spidev_test-to-test-modifying-FIFO-trigge.patch
create mode 100644
features/soc/baytrail/spi-pxa2xx-Add-new-ioctl-for-configuring-FIFO-trigge.patch
create mode 100644
features/soc/baytrail/spi-pxa2xx-Don-t-use-slave_id-of-dma_slave_config.patch
create mode 100644
features/soc/baytrail/spi-pxa2xx-Prevent-DMA-from-transferring-too-many-by.patch
create mode 100644
features/soc/baytrail/spi-pxa2xx-auto-switch-between-PIO-and-DMA-with-conf.patch
create mode 100644
features/soc/baytrail/spi-pxa2xx-change-default-supported-DMA-burst-size-t.patch
create mode 100644
features/soc/baytrail/spi-pxa2xx-fix-incorrect-SW-mode-chipselect-setting-.patch
create mode 100644
features/soc/baytrail/spi-pxa2xx-fix-runtime-PM-enabling-order.patch
create mode 100644
features/soc/baytrail/spi-pxa2xx-remove-unnecessary-OOM-messages.patch
diff --git a/features/soc/baytrail/baytrail.scc
b/features/soc/baytrail/baytrail.scc
index 1e7c7f2..8ac3cfc 100644
--- a/features/soc/baytrail/baytrail.scc
+++ b/features/soc/baytrail/baytrail.scc
@@ -27,3 +27,13 @@ patch i2c-designware-improve-FIFO-performance.patch
patch i2c-designware-add-per-channel-speed-parameter-and-f.patch
patch i2c-designware-add-i2c-high-speed-support.patch
patch i2c-designware-Fix-checkpatch.pl-warnings.patch
+patch spi-pxa2xx-remove-unnecessary-OOM-messages.patch
+patch spi-pxa2xx-Prevent-DMA-from-transferring-too-many-by.patch
+patch spi-pxa2xx-fix-runtime-PM-enabling-order.patch
+patch spi-pxa2xx-change-default-supported-DMA-burst-size-t.patch
+patch spi-pxa2xx-fix-incorrect-SW-mode-chipselect-setting-.patch
+patch spi-pxa2xx-Don-t-use-slave_id-of-dma_slave_config.patch
+patch spi-pxa2xx-auto-switch-between-PIO-and-DMA-with-conf.patch
+patch spi-modify-spidev_test-to-test-automatic-PIO-DMA-swi.patch
+patch spi-pxa2xx-Add-new-ioctl-for-configuring-FIFO-trigge.patch
+patch spi-modify-spidev_test-to-test-modifying-FIFO-trigge.patch
diff --git
a/features/soc/baytrail/spi-modify-spidev_test-to-test-automatic-PIO-DMA-swi.patch
b/features/soc/baytrail/spi-modify-spidev_test-to-test-automatic-PIO-DMA-swi.patch
new file mode 100644
index 0000000..4d98e8f
--- /dev/null
+++
b/features/soc/baytrail/spi-modify-spidev_test-to-test-automatic-PIO-DMA-swi.patch
@@ -0,0 +1,93 @@
+From 2ae34b84014c5d3e9b5f515b01c08bfc6dd82be4 Mon Sep 17 00:00:00 2001
+From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+Date: Thu, 6 Aug 2015 14:08:18 +0800
+Subject: [PATCH 142/164] spi: modify spidev_test to test automatic PIO/DMA
+ switching
+
+This commit adds two options to the existing spidev_test application,
+-P --auto-pio to enable automatic PIO/DMA switching mode, and
+-T --thresh <value> to set the threshold value to perform the switching
+between PIO and DMA.
+
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ Documentation/spi/spidev_test.c | 21 ++++++++++++++++++++-
+ 1 files changed, 20 insertions(+), 1 deletions(-)
+
+diff --git a/Documentation/spi/spidev_test.c b/Documentation/spi/spidev_test.c
+index 16feda9..85bd71e 100644
+--- a/Documentation/spi/spidev_test.c
++++ b/Documentation/spi/spidev_test.c
+@@ -34,6 +34,8 @@ static uint8_t mode;
+ static uint8_t bits = 8;
+ static uint32_t speed = 500000;
+ static uint16_t delay;
++static uint8_t auto_pio_dma_mode;
++static uint32_t auto_pio_dma_threshold;
+
+ static void transfer(int fd)
+ {
+@@ -55,6 +57,8 @@ static void transfer(int fd)
+ .delay_usecs = delay,
+ .speed_hz = speed,
+ .bits_per_word = bits,
++ .auto_pio_dma_mode = auto_pio_dma_mode,
++ .auto_pio_dma_threshold = auto_pio_dma_threshold,
+ };
+
+ ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+@@ -81,6 +85,8 @@ static void print_usage(const char *prog)
+ " -O --cpol clock polarity\n"
+ " -L --lsb least significant bit first\n"
+ " -C --cs-high chip select active high\n"
++ " -P --auto-pio auto switch PIO/DMA mode\n"
++ " -T --thresh auto switch PIO/DMA threshold\n"
+ " -3 --3wire SI/SO signals shared\n");
+ exit(1);
+ }
+@@ -98,6 +104,8 @@ static void parse_opts(int argc, char *argv[])
+ { "cpol", 0, 0, 'O' },
+ { "lsb", 0, 0, 'L' },
+ { "cs-high", 0, 0, 'C' },
++ { "auto-pio", 0, 0, 'P' },
++ { "thresh", 1, 0, 'T' },
+ { "3wire", 0, 0, '3' },
+ { "no-cs", 0, 0, 'N' },
+ { "ready", 0, 0, 'R' },
+@@ -105,7 +113,7 @@ static void parse_opts(int argc, char *argv[])
+ };
+ int c;
+
+- c = getopt_long(argc, argv, "D:s:d:b:lHOLC3NR", lopts, NULL);
++ c = getopt_long(argc, argv, "D:s:d:b:lHOLCPT:3NR", lopts, NULL);
+
+ if (c == -1)
+ break;
+@@ -138,6 +146,12 @@ static void parse_opts(int argc, char *argv[])
+ case 'C':
+ mode |= SPI_CS_HIGH;
+ break;
++ case 'P':
++ auto_pio_dma_mode = 1;
++ break;
++ case 'T':
++ auto_pio_dma_threshold = atoi(optarg);
++ break;
+ case '3':
+ mode |= SPI_3WIRE;
+ break;
+@@ -201,6 +215,11 @@ int main(int argc, char *argv[])
+ printf("spi mode: %d\n", mode);
+ printf("bits per word: %d\n", bits);
+ printf("max speed: %d Hz (%d KHz)\n", speed, speed/1000);
++ printf("auto switch PIO/DMA: %s\n",
++ auto_pio_dma_mode ? "enabled" : "disabled");
++ if (auto_pio_dma_mode)
++ printf("auto switch PIO/DMA threshold: %d\n",
++ auto_pio_dma_threshold);
+
+ transfer(fd);
+
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-modify-spidev_test-to-test-modifying-FIFO-trigge.patch
b/features/soc/baytrail/spi-modify-spidev_test-to-test-modifying-FIFO-trigge.patch
new file mode 100644
index 0000000..7ad2f2a
--- /dev/null
+++
b/features/soc/baytrail/spi-modify-spidev_test-to-test-modifying-FIFO-trigge.patch
@@ -0,0 +1,134 @@
+From ac07f67627e6e8c2e54487086c8d5d47370a1eab Mon Sep 17 00:00:00 2001
+From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+Date: Thu, 6 Aug 2015 17:05:30 +0800
+Subject: [PATCH 144/164] spi: modify spidev_test to test modifying FIFO
+ trigger level during runtime
+
+This commit adds three options to the existing spidev_test application,
+-r --rx-thr Rx FIFO trigger level
+-t --txlo-thr Tx (low) FIFO trigger level
+-h --txhi-thr Tx (high) FIFO trigger level
+to set the new FIFO trigger level value.
+
+If no value provided, the current FIFO trigger value will be used.
+Use with care as there is not checking on the validity of the input.
+
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ Documentation/spi/spidev_test.c | 55 +++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 53 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/spi/spidev_test.c b/Documentation/spi/spidev_test.c
+index 85bd71e..a7ee217 100644
+--- a/Documentation/spi/spidev_test.c
++++ b/Documentation/spi/spidev_test.c
+@@ -37,6 +37,11 @@ static uint16_t delay;
+ static uint8_t auto_pio_dma_mode;
+ static uint32_t auto_pio_dma_threshold;
+
++static int32_t rx_thresh = -1;
++static int32_t txlo_thresh = -1;
++static int32_t txhi_thresh = -1;
++static int32_t fifo_trigger_level;
++
+ static void transfer(int fd)
+ {
+ int ret;
+@@ -75,7 +80,7 @@ static void transfer(int fd)
+
+ static void print_usage(const char *prog)
+ {
+- printf("Usage: %s [-DsbdlHOLC3]\n", prog);
++ printf("Usage: %s [-DsbdlHOLCrthPT3]\n", prog);
+ puts(" -D --device device to use (default /dev/spidev1.1)\n"
+ " -s --speed max speed (Hz)\n"
+ " -d --delay delay (usec)\n"
+@@ -85,6 +90,9 @@ static void print_usage(const char *prog)
+ " -O --cpol clock polarity\n"
+ " -L --lsb least significant bit first\n"
+ " -C --cs-high chip select active high\n"
++ " -r --rx-thr Rx FIFO trigger level\n"
++ " -t --txlo-thr Tx (low) FIFO trigger level\n"
++ " -h --txhi-thr Tx (high) FIFO trigger level\n"
+ " -P --auto-pio auto switch PIO/DMA mode\n"
+ " -T --thresh auto switch PIO/DMA threshold\n"
+ " -3 --3wire SI/SO signals shared\n");
+@@ -104,6 +112,9 @@ static void parse_opts(int argc, char *argv[])
+ { "cpol", 0, 0, 'O' },
+ { "lsb", 0, 0, 'L' },
+ { "cs-high", 0, 0, 'C' },
++ { "rx-thr", 1, 0, 'r' },
++ { "txlo-thr", 1, 0, 't' },
++ { "txhi-thr", 1, 0, 'h' },
+ { "auto-pio", 0, 0, 'P' },
+ { "thresh", 1, 0, 'T' },
+ { "3wire", 0, 0, '3' },
+@@ -113,7 +124,8 @@ static void parse_opts(int argc, char *argv[])
+ };
+ int c;
+
+- c = getopt_long(argc, argv, "D:s:d:b:lHOLCPT:3NR", lopts, NULL);
++ c = getopt_long(argc, argv, "D:s:d:b:lHOLCr:t:h:PT:3NR",
++ lopts, NULL);
+
+ if (c == -1)
+ break;
+@@ -146,6 +158,15 @@ static void parse_opts(int argc, char *argv[])
+ case 'C':
+ mode |= SPI_CS_HIGH;
+ break;
++ case 'r':
++ rx_thresh = atoi(optarg);
++ break;
++ case 't':
++ txlo_thresh = atoi(optarg);
++ break;
++ case 'h':
++ txhi_thresh = atoi(optarg);
++ break;
+ case 'P':
+ auto_pio_dma_mode = 1;
+ break;
+@@ -212,9 +233,39 @@ int main(int argc, char *argv[])
+ if (ret == -1)
+ pabort("can't get max speed hz");
+
++ /*
++ * fifo trigger level
++ */
++ ret = ioctl(fd, SPI_IOC_RD_FIFO_TRIGGER_LEVEL, &fifo_trigger_level);
++ if (ret == -1)
++ pabort("can't get fifo trigger level");
++
++ /* use new fifo trigger value */
++ if (rx_thresh != -1)
++ fifo_trigger_level = (fifo_trigger_level & 0x00ffff)
++ | ((rx_thresh << 16) & 0xff0000);
++ if (txlo_thresh != -1)
++ fifo_trigger_level = (fifo_trigger_level & 0xff00ff)
++ | ((txlo_thresh << 8) & 0x00ff00);
++ if (txhi_thresh != -1)
++ fifo_trigger_level = (fifo_trigger_level & 0xffff00)
++ | (txhi_thresh & 0x0000ff);
++
++ ret = ioctl(fd, SPI_IOC_WR_FIFO_TRIGGER_LEVEL, &fifo_trigger_level);
++ if (ret == -1)
++ pabort("can't set fifo trigger level");
++
++ ret = ioctl(fd, SPI_IOC_RD_FIFO_TRIGGER_LEVEL, &fifo_trigger_level);
++ if (ret == -1)
++ pabort("can't get fifo trigger level");
++
+ printf("spi mode: %d\n", mode);
+ printf("bits per word: %d\n", bits);
+ printf("max speed: %d Hz (%d KHz)\n", speed, speed/1000);
++ printf("fifo trigger level: RX=%d, TX_LO=%d, TX_HI=%d\n",
++ (fifo_trigger_level & 0xff0000) >> 16,
++ (fifo_trigger_level & 0x00ff00) >> 8,
++ (fifo_trigger_level & 0x0000ff));
+ printf("auto switch PIO/DMA: %s\n",
+ auto_pio_dma_mode ? "enabled" : "disabled");
+ if (auto_pio_dma_mode)
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-pxa2xx-Add-new-ioctl-for-configuring-FIFO-trigge.patch
b/features/soc/baytrail/spi-pxa2xx-Add-new-ioctl-for-configuring-FIFO-trigge.patch
new file mode 100644
index 0000000..7fe5914
--- /dev/null
+++
b/features/soc/baytrail/spi-pxa2xx-Add-new-ioctl-for-configuring-FIFO-trigge.patch
@@ -0,0 +1,112 @@
+From c7bece344e7e1c73c1f56d184fbb8f1dca5a2bc4 Mon Sep 17 00:00:00 2001
+From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+Date: Thu, 6 Aug 2015 16:40:20 +0800
+Subject: [PATCH 143/164] spi/pxa2xx: Add new ioctl for configuring FIFO
+ trigger level in runtime
+
+This commit is to enable user space application to configure the the FIFO
+trigger level for Rx and Tx.
+
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/spi/spi-pxa2xx.c | 13 +++++++++++++
+ drivers/spi/spidev.c | 17 +++++++++++++++++
+ include/linux/spi/spi.h | 1 +
+ include/uapi/linux/spi/spidev.h | 3 +++
+ 4 files changed, 34 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
+index 69883b8..11d78b0 100644
+--- a/drivers/spi/spi-pxa2xx.c
++++ b/drivers/spi/spi-pxa2xx.c
+@@ -904,6 +904,16 @@ static int setup(struct spi_device *spi)
+ rx_thres = RX_THRESH_DFLT;
+ }
+
++ /* Override default FIFO trigger level, with new value. */
++ if (spi->fifo_trigger_level) {
++ if (rx_thres != (spi->fifo_trigger_level >> 16) & 0xff)
++ rx_thres = (spi->fifo_trigger_level >> 16) & 0xff;
++ if (tx_thres != (spi->fifo_trigger_level >> 8) & 0xff)
++ tx_thres = (spi->fifo_trigger_level >> 8) & 0xff;
++ if (tx_hi_thres != spi->fifo_trigger_level & 0xff)
++ tx_hi_thres = spi->fifo_trigger_level & 0xff;
++ }
++
+ /* Only alloc on first setup */
+ chip = spi_get_ctldata(spi);
+ if (!chip) {
+@@ -961,6 +971,9 @@ static int setup(struct spi_device *spi)
+ chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
+ | SSITF_TxHiThresh(tx_hi_thres);
+
++ spi->fifo_trigger_level = (chip->lpss_rx_threshold + 1) << 16
++ | (chip->lpss_tx_threshold + 0x101);
++
+ /* set dma burst and threshold outside of chip_info path so that if
+ * chip_info goes away after setting chip->enable_dma, the
+ * burst and threshold can still respond to changes in bits_per_word */
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index e14c7c0..6b6aa78 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -374,6 +374,10 @@ spidev_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg)
+ case SPI_IOC_RD_MAX_SPEED_HZ:
+ retval = __put_user(spi->max_speed_hz, (__u32 __user *)arg);
+ break;
++ case SPI_IOC_RD_FIFO_TRIGGER_LEVEL:
++ retval = __put_user(spi->fifo_trigger_level,
++ (__u32 __user *)arg);
++ break;
+
+ /* write requests */
+ case SPI_IOC_WR_MODE:
+@@ -438,6 +442,19 @@ spidev_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg)
+ dev_dbg(&spi->dev, "%d Hz (max)\n", tmp);
+ }
+ break;
++ case SPI_IOC_WR_FIFO_TRIGGER_LEVEL:
++ retval = __get_user(tmp, (__u32 __user *)arg);
++ if (retval == 0) {
++ u32 save = spi->fifo_trigger_level;
++
++ spi->fifo_trigger_level = tmp;
++ retval = spi_setup(spi);
++ if (retval < 0)
++ spi->fifo_trigger_level = save;
++ else
++ dev_dbg(&spi->dev, "FIFO trigger 0x%d\n", tmp);
++ }
++ break;
+
+ default:
+ /* segmented and/or full-duplex I/O request */
+diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
+index f2c3424..69fd062 100644
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -98,6 +98,7 @@ struct spi_device {
+ void *controller_data;
+ char modalias[SPI_NAME_SIZE];
+ int cs_gpio; /* chip select gpio */
++ u32 fifo_trigger_level;
+
+ /*
+ * likely need more hooks for more protocol options affecting how
+diff --git a/include/uapi/linux/spi/spidev.h b/include/uapi/linux/spi/spidev.h
+index c5ed56d..7babba0 100644
+--- a/include/uapi/linux/spi/spidev.h
++++ b/include/uapi/linux/spi/spidev.h
+@@ -128,6 +128,9 @@ struct spi_ioc_transfer {
+ #define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32)
+ #define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32)
+
++/* Read / Write SPI FIFO threshold */
++#define SPI_IOC_RD_FIFO_TRIGGER_LEVEL _IOR(SPI_IOC_MAGIC, 5, __u32)
++#define SPI_IOC_WR_FIFO_TRIGGER_LEVEL _IOW(SPI_IOC_MAGIC, 5, __u32)
+
+
+ #endif /* SPIDEV_H */
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-pxa2xx-Don-t-use-slave_id-of-dma_slave_config.patch
b/features/soc/baytrail/spi-pxa2xx-Don-t-use-slave_id-of-dma_slave_config.patch
new file mode 100644
index 0000000..e122a28
--- /dev/null
+++
b/features/soc/baytrail/spi-pxa2xx-Don-t-use-slave_id-of-dma_slave_config.patch
@@ -0,0 +1,240 @@
+From 5a432f09ff1aa0cf0c199c0ef48b131004959ee9 Mon Sep 17 00:00:00 2001
+From: Mika Westerberg <mika.westerb...@linux.intel.com>
+Date: Tue, 19 Aug 2014 20:29:19 +0300
+Subject: [PATCH 087/164] spi/pxa2xx: Don't use slave_id of dma_slave_config
+
+That field has been deprecated in favour of getting the necessary
+information from ACPI/DT.
+
+However, we still need to deal systems that are PCI only (no ACPI to back
+up). In order to support such systems, we allow the DMA filter function and
+its corresponding parameter via pxa2xx_spi_master platform data. Then when
+the pxa2xx_spi_dma_setup() doesn't find the channel via ACPI, it falls back
+to use the given filter function.
+
+Suggested-by: Arnd Bergmann <a...@arndb.de>
+Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Acked-by: Mark Brown <broo...@linaro.org>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+(cherry picked from commit b729bf34535ed413667b397a2f59cfa81266facf)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/spi/spi-pxa2xx-dma.c | 15 +--------
+ drivers/spi/spi-pxa2xx-pci.c | 64 +++++++++++++++++++++++++++++----------
+ drivers/spi/spi-pxa2xx.c | 2 -
+ include/linux/spi/pxa2xx_spi.h | 9 +++--
+ 4 files changed, 54 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c
+index 6fc2bc1..3297e9a 100644
+--- a/drivers/spi/spi-pxa2xx-dma.c
++++ b/drivers/spi/spi-pxa2xx-dma.c
+@@ -158,7 +158,6 @@ static struct dma_async_tx_descriptor *
+ pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
+ enum dma_transfer_direction dir)
+ {
+- struct pxa2xx_spi_master *pdata = drv_data->master_info;
+ struct chip_data *chip = drv_data->cur_chip;
+ enum dma_slave_buswidth width;
+ struct dma_slave_config cfg;
+@@ -185,7 +184,6 @@ pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
+ cfg.dst_addr = drv_data->ssdr_physical;
+ cfg.dst_addr_width = width;
+ cfg.dst_maxburst = chip->dma_burst_size;
+- cfg.slave_id = pdata->tx_slave_id;
+
+ sgt = &drv_data->tx_sgt;
+ nents = drv_data->tx_nents;
+@@ -194,7 +192,6 @@ pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
+ cfg.src_addr = drv_data->ssdr_physical;
+ cfg.src_addr_width = width;
+ cfg.src_maxburst = chip->dma_burst_size;
+- cfg.slave_id = pdata->rx_slave_id;
+
+ sgt = &drv_data->rx_sgt;
+ nents = drv_data->rx_nents;
+@@ -211,14 +208,6 @@ pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ }
+
+-static bool pxa2xx_spi_dma_filter(struct dma_chan *chan, void *param)
+-{
+- const struct pxa2xx_spi_master *pdata = param;
+-
+- return chan->chan_id == pdata->tx_chan_id ||
+- chan->chan_id == pdata->rx_chan_id;
+-}
+-
+ bool pxa2xx_spi_dma_is_possible(size_t len)
+ {
+ return len <= MAX_DMA_LEN;
+@@ -322,12 +311,12 @@ int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
+ return -ENOMEM;
+
+ drv_data->tx_chan = dma_request_slave_channel_compat(mask,
+- pxa2xx_spi_dma_filter, pdata, dev, "tx");
++ pdata->dma_filter, pdata->tx_param, dev, "tx");
+ if (!drv_data->tx_chan)
+ return -ENODEV;
+
+ drv_data->rx_chan = dma_request_slave_channel_compat(mask,
+- pxa2xx_spi_dma_filter, pdata, dev, "rx");
++ pdata->dma_filter, pdata->rx_param, dev, "rx");
+ if (!drv_data->rx_chan) {
+ dma_release_channel(drv_data->tx_chan);
+ drv_data->tx_chan = NULL;
+diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
+index 20ebbc7..0424b67 100644
+--- a/drivers/spi/spi-pxa2xx-pci.c
++++ b/drivers/spi/spi-pxa2xx-pci.c
+@@ -10,6 +10,9 @@
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
+
++#include <linux/dmaengine.h>
++#include <linux/platform_data/dma-dw.h>
++
+ enum {
+ PORT_CE4100,
+ PORT_BYT,
+@@ -19,33 +22,41 @@ struct pxa_spi_info {
+ enum pxa_ssp_type type;
+ int port_id;
+ int num_chipselect;
+- int tx_slave_id;
+- int tx_chan_id;
+- int rx_slave_id;
+- int rx_chan_id;
+ unsigned long max_clk_rate;
++
++ /* DMA channel request parameters */
++ void *tx_param;
++ void *rx_param;
+ };
+
++static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
++static struct dw_dma_slave byt_rx_param = { .src_id = 1 };
++
++static bool lpss_dma_filter(struct dma_chan *chan, void *param)
++{
++ struct dw_dma_slave *dws = param;
++
++ if (dws->dma_dev != chan->device->dev)
++ return false;
++
++ chan->private = dws;
++ return true;
++}
++
+ static struct pxa_spi_info spi_info_configs[] = {
+ [PORT_CE4100] = {
+ .type = PXA25x_SSP,
+ .port_id = -1,
+ .num_chipselect = -1,
+- .tx_slave_id = -1,
+- .tx_chan_id = -1,
+- .rx_slave_id = -1,
+- .rx_chan_id = -1,
+ .max_clk_rate = 3686400,
+ },
+ [PORT_BYT] = {
+ .type = LPSS_SSP,
+ .port_id = 0,
+ .num_chipselect = 1,
+- .tx_slave_id = 0,
+- .tx_chan_id = 0,
+- .rx_slave_id = 1,
+- .rx_chan_id = 1,
+ .max_clk_rate = 50000000,
++ .tx_param = &byt_tx_param,
++ .rx_param = &byt_rx_param,
+ },
+ };
+
+@@ -59,6 +70,7 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
+ struct ssp_device *ssp;
+ struct pxa_spi_info *c;
+ char buf[40];
++ struct pci_dev *dma_dev;
+
+ ret = pcim_enable_device(dev);
+ if (ret)
+@@ -73,11 +85,29 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
+ memset(&spi_pdata, 0, sizeof(spi_pdata));
+ spi_pdata.num_chipselect = (c->num_chipselect > 0) ?
+ c->num_chipselect : dev->devfn;
+- spi_pdata.tx_slave_id = c->tx_slave_id;
+- spi_pdata.tx_chan_id = c->tx_chan_id;
+- spi_pdata.rx_slave_id = c->rx_slave_id;
+- spi_pdata.rx_chan_id = c->rx_chan_id;
+- spi_pdata.enable_dma = c->rx_slave_id >= 0 && c->tx_slave_id >= 0;
++
++ dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
++
++ if (c->tx_param) {
++ struct dw_dma_slave *slave = c->tx_param;
++
++ slave->dma_dev = &dma_dev->dev;
++ slave->src_master = 1;
++ slave->dst_master = 0;
++ }
++
++ if (c->rx_param) {
++ struct dw_dma_slave *slave = c->rx_param;
++
++ slave->dma_dev = &dma_dev->dev;
++ slave->src_master = 1;
++ slave->dst_master = 0;
++ }
++
++ spi_pdata.dma_filter = lpss_dma_filter;
++ spi_pdata.tx_param = c->tx_param;
++ spi_pdata.rx_param = c->rx_param;
++ spi_pdata.enable_dma = c->rx_param && c->tx_param;
+
+ ssp = &spi_pdata.ssp;
+ ssp->phys_base = pci_resource_start(dev, 0);
+diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
+index ceb6bf0..914ceab 100644
+--- a/drivers/spi/spi-pxa2xx.c
++++ b/drivers/spi/spi-pxa2xx.c
+@@ -1064,8 +1064,6 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
+
+ pdata->num_chipselect = 1;
+ pdata->enable_dma = true;
+- pdata->tx_chan_id = -1;
+- pdata->rx_chan_id = -1;
+
+ return pdata;
+ }
+diff --git a/include/linux/spi/pxa2xx_spi.h b/include/linux/spi/pxa2xx_spi.h
+index 82d5111..d5a3165 100644
+--- a/include/linux/spi/pxa2xx_spi.h
++++ b/include/linux/spi/pxa2xx_spi.h
+@@ -23,6 +23,8 @@
+ #define PXA2XX_CS_ASSERT (0x01)
+ #define PXA2XX_CS_DEASSERT (0x02)
+
++struct dma_chan;
++
+ /* device.platform_data for SSP controller devices */
+ struct pxa2xx_spi_master {
+ u32 clock_enable;
+@@ -30,10 +32,9 @@ struct pxa2xx_spi_master {
+ u8 enable_dma;
+
+ /* DMA engine specific config */
+- int rx_chan_id;
+- int tx_chan_id;
+- int rx_slave_id;
+- int tx_slave_id;
++ bool (*dma_filter)(struct dma_chan *chan, void *param);
++ void *tx_param;
++ void *rx_param;
+
+ /* For non-PXA arches */
+ struct ssp_device ssp;
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-pxa2xx-Prevent-DMA-from-transferring-too-many-by.patch
b/features/soc/baytrail/spi-pxa2xx-Prevent-DMA-from-transferring-too-many-by.patch
new file mode 100644
index 0000000..c4efae0
--- /dev/null
+++
b/features/soc/baytrail/spi-pxa2xx-Prevent-DMA-from-transferring-too-many-by.patch
@@ -0,0 +1,70 @@
+From 9999cd8d40c8e6fbc0c3a30cc285efedff1711ec Mon Sep 17 00:00:00 2001
+From: Mika Westerberg <mika.westerb...@linux.intel.com>
+Date: Thu, 8 May 2014 17:30:31 +0300
+Subject: [PATCH 020/164] spi/pxa2xx: Prevent DMA from transferring too many
+ bytes
+
+In case we are doing DMA transfer and the size of the buffer is not multiple
+of 4 bytes the driver truncates that to 4-byte boundary and tries to handle
+remaining bytes using PIO.
+
+Or that is what it tried to do. What actually happens is that it calls
+ALIGN() to the buffer size which aligns it to the next 4-byte boundary
+(doesn't truncate). Doing this results 1-3 bytes extra to be transferred.
+Furthermore we handle remaining bytes using PIO which results one extra
+byte to be transferred. In worst case the driver transfers 4 extra bytes.
+
+While investigating this it turned out that the DMA hardware doesn't even
+have such limitation so we can solve this by dropping the code that tries
+to handle unaligned bytes.
+
+Reported-by: Chiau Ee Chew <chiau.ee.c...@intel.com>
+Reported-by: Hock Leong Kweh <hock.leong.k...@intel.com>
+Signed-off-by: Mika Westerberg <mika.westerb...@linux.intel.com>
+Signed-off-by: Mark Brown <broo...@linaro.org>
+(cherry picked from commit 111e0a9dc71ed75baa5e739289b9bdb06fda13be)
+
+Signed-off-by: Maurice Petallo <mauricex.r.peta...@intel.com>
+---
+ drivers/spi/spi-pxa2xx-dma.c | 16 ----------------
+ 1 files changed, 0 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c
+index 3c0b551..07a4625 100644
+--- a/drivers/spi/spi-pxa2xx-dma.c
++++ b/drivers/spi/spi-pxa2xx-dma.c
+@@ -30,18 +30,6 @@ static int pxa2xx_spi_map_dma_buffer(struct driver_data
*drv_data,
+ struct sg_table *sgt;
+ void *buf, *pbuf;
+
+- /*
+- * Some DMA controllers have problems transferring buffers that are
+- * not multiple of 4 bytes. So we truncate the transfer so that it
+- * is suitable for such controllers, and handle the trailing bytes
+- * manually after the DMA completes.
+- *
+- * REVISIT: It would be better if this information could be
+- * retrieved directly from the DMA device in a similar way than
+- * ->copy_align etc. is done.
+- */
+- len = ALIGN(drv_data->len, 4);
+-
+ if (dir == DMA_TO_DEVICE) {
+ dmadev = drv_data->tx_chan->device->dev;
+ sgt = &drv_data->tx_sgt;
+@@ -145,12 +133,8 @@ static void pxa2xx_spi_dma_transfer_complete(struct
driver_data *drv_data,
+ if (!error) {
+ pxa2xx_spi_unmap_dma_buffers(drv_data);
+
+- /* Handle the last bytes of unaligned transfer */
+ drv_data->tx += drv_data->tx_map_len;
+- drv_data->write(drv_data);
+-
+ drv_data->rx += drv_data->rx_map_len;
+- drv_data->read(drv_data);
+
+ msg->actual_length += drv_data->len;
+ msg->state = pxa2xx_spi_next_transfer(drv_data);
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-pxa2xx-auto-switch-between-PIO-and-DMA-with-conf.patch
b/features/soc/baytrail/spi-pxa2xx-auto-switch-between-PIO-and-DMA-with-conf.patch
new file mode 100644
index 0000000..2437183
--- /dev/null
+++
b/features/soc/baytrail/spi-pxa2xx-auto-switch-between-PIO-and-DMA-with-conf.patch
@@ -0,0 +1,106 @@
+From c95d65aa649a74ba29b35b3e3c177b1a6bebe799 Mon Sep 17 00:00:00 2001
+From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+Date: Fri, 24 Jul 2015 11:39:17 +0800
+Subject: [PATCH 141/164] spi/pxa2xx: auto switch between PIO and DMA with
+ configurable threshold size
+
+This commit introduces a mode where spidev driver can enable/disable
+an automatic switching for data transfer to be performed in PIO mode or
+DMA mode upon reaching a configurable data transfer threshold size.
+
+If the data transfer size larger than the threshold size and less than the
+value of MAX_DMA_LEN, the transfer is performed in DMA mode.
+
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/spi/spi-pxa2xx.c | 17 +++++++++++++++--
+ drivers/spi/spidev.c | 2 ++
+ include/linux/spi/spi.h | 2 ++
+ include/uapi/linux/spi/spidev.h | 2 ++
+ 4 files changed, 21 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
+index 5d71e61..69883b8 100644
+--- a/drivers/spi/spi-pxa2xx.c
++++ b/drivers/spi/spi-pxa2xx.c
+@@ -619,6 +619,7 @@ static void pump_transfers(unsigned long data)
+ u32 cr1;
+ u32 dma_thresh = drv_data->cur_chip->dma_threshold;
+ u32 dma_burst = drv_data->cur_chip->dma_burst_size;
++ u8 auto_pio_dma_use_pio;
+
+ /* Get current state information */
+ message = drv_data->cur_msg;
+@@ -652,8 +653,20 @@ static void pump_transfers(unsigned long data)
+ cs_deassert(drv_data);
+ }
+
++ /*
++ * Check if in auto switch PIO/DMA mode.
++ * If true, use PIO if the length is less than threshold value.
++ */
++ auto_pio_dma_use_pio = chip->enable_dma ? 0 : 1;
++ if (transfer->auto_pio_dma_mode) {
++ if (transfer->len <= transfer->auto_pio_dma_threshold) {
++ auto_pio_dma_use_pio = 1;
++ }
++ }
++
+ /* Check if we can DMA this transfer */
+- if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
++ if ((!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma)
++ || auto_pio_dma_use_pio) {
+
+ /* reject already-mapped transfers; PIO won't always work */
+ if (message->is_dma_mapped
+@@ -747,7 +760,7 @@ static void pump_transfers(unsigned long data)
+ message->state = RUNNING_STATE;
+
+ drv_data->dma_mapped = 0;
+- if (pxa2xx_spi_dma_is_possible(drv_data->len))
++ if (pxa2xx_spi_dma_is_possible(drv_data->len) && !auto_pio_dma_use_pio)
+ drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
+ if (drv_data->dma_mapped) {
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 2fe5b61..e14c7c0 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -271,6 +271,8 @@ static int spidev_message(struct spidev_data *spidev,
+ k_tmp->bits_per_word = u_tmp->bits_per_word;
+ k_tmp->delay_usecs = u_tmp->delay_usecs;
+ k_tmp->speed_hz = u_tmp->speed_hz;
++ k_tmp->auto_pio_dma_mode = u_tmp->auto_pio_dma_mode;
++ k_tmp->auto_pio_dma_threshold = u_tmp->auto_pio_dma_threshold;
+ #ifdef VERBOSE
+ dev_dbg(&spidev->spi->dev,
+ " xfer len %zd %s%s%s%dbits %u usec %uHz\n",
+diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
+index 4203c66..f2c3424 100644
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -589,6 +589,8 @@ struct spi_transfer {
+ u8 bits_per_word;
+ u16 delay_usecs;
+ u32 speed_hz;
++ u8 auto_pio_dma_mode;
++ u32 auto_pio_dma_threshold;
+
+ struct list_head transfer_list;
+ };
+diff --git a/include/uapi/linux/spi/spidev.h b/include/uapi/linux/spi/spidev.h
+index 52d9ed0..c5ed56d 100644
+--- a/include/uapi/linux/spi/spidev.h
++++ b/include/uapi/linux/spi/spidev.h
+@@ -92,6 +92,8 @@ struct spi_ioc_transfer {
+ __u16 delay_usecs;
+ __u8 bits_per_word;
+ __u8 cs_change;
++ __u8 auto_pio_dma_mode;
++ __u32 auto_pio_dma_threshold;
+ __u32 pad;
+
+ /* If the contents of 'struct spi_ioc_transfer' ever change
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-pxa2xx-change-default-supported-DMA-burst-size-t.patch
b/features/soc/baytrail/spi-pxa2xx-change-default-supported-DMA-burst-size-t.patch
new file mode 100644
index 0000000..eda8ece
--- /dev/null
+++
b/features/soc/baytrail/spi-pxa2xx-change-default-supported-DMA-burst-size-t.patch
@@ -0,0 +1,43 @@
+From 9909f106fd1d170790584deb82ff20b860281993 Mon Sep 17 00:00:00 2001
+From: "Chew, Chiau Ee" <chiau.ee.c...@intel.com>
+Date: Fri, 6 Jun 2014 01:45:09 +0800
+Subject: [PATCH 022/164] spi/pxa2xx: change default supported DMA burst size
+ to 1
+
+This is to fix the SPI DMA transfer failure for speed less than 1M.
+If using current DMA burst size setting (16), the Rx data bytes are
+invalid due to each data byte is multiplied according to the burst
+size setting.
+
+Let's said supposedly we shall receive the following 18 bytes of data:
+01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18
+Instead, the data bytes received consist of "16 bytes of '01' +
+2 bytes of '02'" :
+01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 02 02
+
+Signed-off-by: Chew, Chiau Ee <chiau.ee.c...@intel.com>
+Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
+Signed-off-by: Mark Brown <broo...@linaro.org>
+(cherry picked from commit 01d7aafb3fbaafe2403780ef9ed497b3289ab1b9)
+
+Signed-off-by: Maurice Petallo <mauricex.r.peta...@intel.com>
+---
+ drivers/spi/spi-pxa2xx-dma.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c
+index 07a4625..6fc2bc1 100644
+--- a/drivers/spi/spi-pxa2xx-dma.c
++++ b/drivers/spi/spi-pxa2xx-dma.c
+@@ -369,7 +369,7 @@ int pxa2xx_spi_set_dma_burst_and_threshold(struct
chip_data *chip,
+ * otherwise we use the default. Also we use the default FIFO
+ * thresholds for now.
+ */
+- *burst_code = chip_info ? chip_info->dma_burst_size : 16;
++ *burst_code = chip_info ? chip_info->dma_burst_size : 1;
+ *threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
+ | SSCR1_TxTresh(TX_THRESH_DFLT);
+
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-pxa2xx-fix-incorrect-SW-mode-chipselect-setting-.patch
b/features/soc/baytrail/spi-pxa2xx-fix-incorrect-SW-mode-chipselect-setting-.patch
new file mode 100644
index 0000000..df0bae3
--- /dev/null
+++
b/features/soc/baytrail/spi-pxa2xx-fix-incorrect-SW-mode-chipselect-setting-.patch
@@ -0,0 +1,51 @@
+From a976c0d36fc864d0a9fe0b29dc729cef6b47a939 Mon Sep 17 00:00:00 2001
+From: "Chew, Chiau Ee" <chiau.ee.c...@intel.com>
+Date: Fri, 13 Jun 2014 23:57:25 +0800
+Subject: [PATCH 023/164] spi/pxa2xx: fix incorrect SW mode chipselect setting
+ for BayTrail LPSS SPI
+
+It was observed that after module removal followed by insertion,
+the SW mode chipselect is not properly set. Thus causing transfer
+failure due to incorrect CS toggling.
+
+Signed-off-by: Chew, Chiau Ee <chiau.ee.c...@intel.com>
+Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
+Signed-off-by: Mark Brown <broo...@linaro.org>
+(cherry picked from commit e61f487fd596ce570e87ccfdc0a7fc9fa87aced9)
+
+Signed-off-by: Maurice Petallo <mauricex.r.peta...@intel.com>
+---
+ drivers/spi/spi-pxa2xx.c | 8 ++++++--
+ 1 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
+index 8f001b4..ceb6bf0 100644
+--- a/drivers/spi/spi-pxa2xx.c
++++ b/drivers/spi/spi-pxa2xx.c
+@@ -119,6 +119,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
+ */
+ orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
+
++ /* Test SPI_CS_CONTROL_SW_MODE bit enabling */
+ value = orig | SPI_CS_CONTROL_SW_MODE;
+ writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
+ value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
+@@ -127,10 +128,13 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
+ goto detection_done;
+ }
+
+- value &= ~SPI_CS_CONTROL_SW_MODE;
++ orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
++
++ /* Test SPI_CS_CONTROL_SW_MODE bit disabling */
++ value = orig & ~SPI_CS_CONTROL_SW_MODE;
+ writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
+ value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
+- if (value != orig) {
++ if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) {
+ offset = 0x800;
+ goto detection_done;
+ }
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-pxa2xx-fix-runtime-PM-enabling-order.patch
b/features/soc/baytrail/spi-pxa2xx-fix-runtime-PM-enabling-order.patch
new file mode 100644
index 0000000..87d4d45
--- /dev/null
+++ b/features/soc/baytrail/spi-pxa2xx-fix-runtime-PM-enabling-order.patch
@@ -0,0 +1,57 @@
+From 30ee7a1c04af326d5655381917ee545743fa01fe Mon Sep 17 00:00:00 2001
+From: Antonio Ospite <a...@ao2.it>
+Date: Fri, 30 May 2014 18:18:09 +0200
+Subject: [PATCH 021/164] spi/pxa2xx: fix runtime PM enabling order
+
+In commit 7dd62787334ac6e0e2a0ef3f20bb1936ac431b04 (spi/pxa2xx: Convert
+to core runtime PM) master->auto_runtime_pm was set to true.
+
+In this case pm_runtime_enable() must be called *before*
+spi_register_master(), otherwise the kernel hangs with this error
+message:
+
+ spi_master spi0: Failed to power device: -13
+
+A similar fix, but for spi/hspi, was applied in
+268d76430d1b68c340687357ffd18b4b12d02269.
+
+Signed-off-by: Antonio Ospite <a...@ao2.it>
+Signed-off-by: Mark Brown <broo...@linaro.org>
+(cherry picked from commit 836d1a22db9ee0a466301465e873bc94da86cb15)
+
+Signed-off-by: Maurice Petallo <mauricex.r.peta...@intel.com>
+---
+ drivers/spi/spi-pxa2xx.c | 10 +++++-----
+ 1 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
+index 0268c96..8f001b4 100644
+--- a/drivers/spi/spi-pxa2xx.c
++++ b/drivers/spi/spi-pxa2xx.c
+@@ -1198,6 +1198,11 @@ static int pxa2xx_spi_probe(struct platform_device
*pdev)
+ tasklet_init(&drv_data->pump_transfers, pump_transfers,
+ (unsigned long)drv_data);
+
++ pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
++ pm_runtime_use_autosuspend(&pdev->dev);
++ pm_runtime_set_active(&pdev->dev);
++ pm_runtime_enable(&pdev->dev);
++
+ /* Register with the SPI framework */
+ platform_set_drvdata(pdev, drv_data);
+ status = devm_spi_register_master(&pdev->dev, master);
+@@ -1206,11 +1211,6 @@ static int pxa2xx_spi_probe(struct platform_device
*pdev)
+ goto out_error_clock_enabled;
+ }
+
+- pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
+- pm_runtime_use_autosuspend(&pdev->dev);
+- pm_runtime_set_active(&pdev->dev);
+- pm_runtime_enable(&pdev->dev);
+-
+ return status;
+
+ out_error_clock_enabled:
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/spi-pxa2xx-remove-unnecessary-OOM-messages.patch
b/features/soc/baytrail/spi-pxa2xx-remove-unnecessary-OOM-messages.patch
new file mode 100644
index 0000000..7fd2a30
--- /dev/null
+++ b/features/soc/baytrail/spi-pxa2xx-remove-unnecessary-OOM-messages.patch
@@ -0,0 +1,50 @@
+From 6f1cc42a2887e7fd891a82a40f4d6d460e792628 Mon Sep 17 00:00:00 2001
+From: Jingoo Han <jg1....@samsung.com>
+Date: Tue, 29 Apr 2014 17:19:38 +0900
+Subject: [PATCH 019/164] spi: pxa2xx: remove unnecessary OOM messages
+
+The site-specific OOM messages are unnecessary, because they
+duplicate the MM subsystem generic OOM message.
+
+Signed-off-by: Jingoo Han <jg1....@samsung.com>
+Signed-off-by: Mark Brown <broo...@linaro.org>
+(cherry picked from commit 9deae4592b66c0b2a7832fefa192e7a506ce047e)
+
+Signed-off-by: Maurice Petallo <mauricex.r.peta...@intel.com>
+---
+ drivers/spi/spi-pxa2xx.c | 10 ++--------
+ 1 files changed, 2 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
+index 458a148..0268c96 100644
+--- a/drivers/spi/spi-pxa2xx.c
++++ b/drivers/spi/spi-pxa2xx.c
+@@ -887,11 +887,8 @@ static int setup(struct spi_device *spi)
+ chip = spi_get_ctldata(spi);
+ if (!chip) {
+ chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
+- if (!chip) {
+- dev_err(&spi->dev,
+- "failed setup: can't allocate chip data\n");
++ if (!chip)
+ return -ENOMEM;
+- }
+
+ if (drv_data->ssp_type == CE4100_SSP) {
+ if (spi->chip_select > 4) {
+@@ -1038,11 +1035,8 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
+ return NULL;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+- if (!pdata) {
+- dev_err(&pdev->dev,
+- "failed to allocate memory for platform data\n");
++ if (!pdata)
+ return NULL;
+- }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+--
+1.7.7.6
+
--
1.9.1
--
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