core:
  ooo:
    base: ooo 
    params:
      ISSUE_WIDTH: 4
      COMMIT_WIDTH: 4
      per_thread:
        rob_size: 128
        lsq_size: 96
      int_FUs: 3
      fp_FUs: 3
 
cache:
  l1_32k_8_:
    base: moesi_cache
    params:
      SIZE: 32K
      LINE_SIZE: 64 # bytes
      ASSOC: 8
      LATENCY: 4
      READ_PORTS: 2
      WRITE_PORTS: 1
  l1_32k_4_:
    base: moesi_cache
    params:
      SIZE: 32K
      LINE_SIZE: 64 # bytes
      ASSOC: 4
      LATENCY: 3
      READ_PORTS: 2
      WRITE_PORTS: 1
  l2_256k:
    base: moesi_cache
    params:
      SIZE: 256K
      LINE_SIZE: 64 # bytes
      ASSOC: 8
      LATENCY: 12
      READ_PORTS: 2
      WRITE_PORTS: 2
  l3_24M:
    base: wb_cache
    params:
      SIZE: 24M
      LINE_SIZE: 64 # bytes
      ASSOC: 24
      LATENCY: 36
      READ_PORTS: 2
      WRITE_PORTS: 2
 
memory:
  dram_cont:
    base: simple_dram_cont
 
machine:
  xeon1:
    description: Mix of OOO and Atom cores with private L2
    min_contexts: 2
    cores:
      - type: ooo
        name_prefix: ooo_
        option:
            threads: 1
    caches:
      - type: l1_32k_4_
        name_prefix: L1_I_
        insts: $NUMCORES
        option:
            private: true
      - type: l1_32k_8_
        name_prefix: L1_D_
        insts: $NUMCORES
        option:
            private: true
      - type: l2_256k
        name_prefix: L2_
        insts: $NUMCORES
        option:
            private: true
            last_private: true
      - type: l3_24M
        name_prefix: L3_
        insts: 1
    memory:
      - type: dram_cont
        name_prefix: MEM_
        insts: 1 # Single DRAM controller
        option:
            latency: 300
    interconnects:
      - type: p2p
        connections:
          - core_$: I
            L1_I_$: UPPER
          - core_$: D
            L1_D_$: UPPER
          - L1_I_$: LOWER
            L2_$: UPPER
          - L1_D_$: LOWER
            L2_$: UPPER2
          - L3_0: LOWER
            MEM_0: UPPER
      - type: switch
        connections:
          - L2_*: LOWER
            L3_0: UPPER
