*** marss_orig/ptlsim/cache/cpuController.cpp	2016-05-23 10:49:08.159451389 +0900
--- marss_orig_patch/ptlsim/cache/cpuController.cpp	2016-05-23 11:37:57.363679561 +0900
***************
*** 224,229 ****
--- 224,230 ----
  	} else {
  		if(fastPathLat > 0) {
  			queueEntry->cycles = fastPathLat;
+             queueEntry->created_cycles = sim_cycle;
  		} else {
  			cache_access_cb(queueEntry);
  		}
***************
*** 286,291 ****
--- 287,293 ----
  		assert(nextEntry->request);
  		memdebug("Setting cycles left to 1 for dependent\n");
  		nextEntry->cycles = 1;
+         nextEntry->created_cycles = sim_cycle;
          nextEntry->waitFor = -1;
  	}
  }
***************
*** 422,428 ****
  	CPUControllerQueueEntry* queueEntry;
  	foreach_list_mutable(pendingRequests_.list(), queueEntry, entry_t,
  			prev_t) {
! 		queueEntry->cycles--;
  		if(queueEntry->cycles == 0) {
  			memdebug("Finalizing from clock\n");
  			finalize_request(queueEntry);
--- 424,432 ----
  	CPUControllerQueueEntry* queueEntry;
  	foreach_list_mutable(pendingRequests_.list(), queueEntry, entry_t,
  			prev_t) {
!         if (queueEntry->created_cycles != sim_cycle){
!             queueEntry->cycles--;
!         }
  		if(queueEntry->cycles == 0) {
  			memdebug("Finalizing from clock\n");
  			finalize_request(queueEntry);