*** marss_orig/ptlsim/core/ooo-core/ooo-exec.cpp	2016-05-23 10:49:08.167451690 +0900
--- marss_orig_patch/ptlsim/core/ooo-core/ooo-exec.cpp	2016-05-23 12:02:44.657580732 +0900
***************
*** 1034,1040 ****
      bool annul;
      bool tlb_hit;
  
!     if(!uop.internal) {
          /* First Probe the TLB */
          tlb_hit = probetlb(state, origaddr, ra, rb, rc, pteupdate);
  
--- 1034,1040 ----
      bool annul;
      bool tlb_hit;
  
!     if(!uop.internal && !state.orig_physaddr_valid) {
          /* First Probe the TLB */
          tlb_hit = probetlb(state, origaddr, ra, rb, rc, pteupdate);
  
***************
*** 1049,1055 ****
          }
      }
  
!     Waddr physaddr = addrgen(state, origaddr, virtpage, ra, rb, rc, pteupdate, addr, exception, pfec, annul);
  
      assert(exception == 0);
  
--- 1049,1060 ----
          }
      }
  
!     if (!lsq->orig_physaddr_valid){
!         Waddr physaddr = addrgen(state, origaddr, virtpage, ra, rb, rc, pteupdate, addr, exception, pfec, annul);
!         state.orig_physaddr = physaddr;
!         state.orig_physaddr_valid = true;
!         state.physaddr = (annul) ? INVALID_PHYSADDR : (physaddr >> 3);
!     }
  
      assert(exception == 0);
  
***************
*** 1058,1065 ****
      thread.thread_stats.dcache.store.type.internal += uop.internal;
      thread.thread_stats.dcache.store.size[sizeshift]++;
  
-     state.physaddr = (annul) ? INVALID_PHYSADDR : (physaddr >> 3);
- 
  /*
   *     The STQ is then searched for the most recent prior store S to same 64-bit block. If found, U's
   *     rs dependency is set to S by setting the ROB's rs field to point to the prior store's physreg
--- 1063,1068 ----
***************
*** 1451,1457 ****
      bool annul;
      bool tlb_hit;
  
!     if(!uop.internal) {
          /* First Probe the TLB */
          tlb_hit = probetlb(state, origaddr, ra, rb, rc, pteupdate);
  
--- 1454,1460 ----
      bool annul;
      bool tlb_hit;
  
!     if(!uop.internal && !state.orig_physaddr_valid) {
          /* First Probe the TLB */
          tlb_hit = probetlb(state, origaddr, ra, rb, rc, pteupdate);
  
***************
*** 1466,1472 ****
          }
      }
  
!     Waddr physaddr = addrgen(state, origaddr, virtpage, ra, rb, rc, pteupdate, addr, exception, pfec, annul);
  
      assert(exception == 0);
  
--- 1469,1480 ----
          }
      }
  
!     if (!state.orig_physaddr_valid){
!         Waddr physaddr = addrgen(state, origaddr, virtpage, ra, rb, rc, pteupdate, addr, exception, pfec, annul);
!         state.orig_physaddr = physaddr;
!         state.physaddr = (annul) ? INVALID_PHYSADDR : (physaddr >> 3);
!         state.orig_physaddr_valid = true;
!     }
  
      assert(exception == 0);
  
***************
*** 1475,1481 ****
      thread.thread_stats.dcache.load.type.internal += uop.internal;
      thread.thread_stats.dcache.load.size[sizeshift]++;
  
!     state.physaddr = (annul) ? INVALID_PHYSADDR : (physaddr >> 3);
  
      W64 data;
  
--- 1483,1489 ----
      thread.thread_stats.dcache.load.type.internal += uop.internal;
      thread.thread_stats.dcache.load.size[sizeshift]++;
  
! 
  
      W64 data;
  
***************
*** 1705,1711 ****
          assert(sfra == NULL);
  
          load_store_second_phase = 1;
!         data = (annul) ? 0 : thread.ctx.loadphys(physaddr, true,
                  sizeshift);
          state.data = data;
          state.datavalid = 1;
--- 1713,1719 ----
          assert(sfra == NULL);
  
          load_store_second_phase = 1;
!         data = (annul) ? 0 : thread.ctx.loadphys(state.orig_physaddr, true,
                  sizeshift);
          state.data = data;
          state.datavalid = 1;
***************
*** 2925,2932 ****
--- 2933,2942 ----
  
      if unlikely (lsq) {
          lsq->physaddr = 0;
+         lsq->orig_physaddr = 0;
          lsq->virtaddr = 0;
          lsq->addrvalid = 0;
+         lsq->orig_physaddr_valid = 0;
          lsq->datavalid = 0;
          lsq->mbtag = -1;
          lsq->data = 0;