Module: Mesa
Branch: master
Commit: 58c8aae24113f604ddfc03022249cab8d2450ad7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58c8aae24113f604ddfc03022249cab8d2450ad7
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Tue Jun 6 21:39:42 2017 +0200
radv: Move pipeline stuff from flush_state to emit_graphics_pipeline.
No functional changes.
Signed-off-by: Bas Nieuwenhuizen <ba...@google.com>
Reviewed-by: Dave Airlie <airl...@redhat.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ca9d606a7c..6dfd52ea9d 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -901,6 +901,16 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer,
cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
pipeline->graphics.can_use_guardband)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
+
+ radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN,
pipeline->graphics.vgt_shader_stages_en);
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
+ radeon_set_uconfig_reg_idx(cmd_buffer->cs,
R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
+ } else {
+ radeon_set_config_reg(cmd_buffer->cs,
R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
+ }
+ radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
pipeline->graphics.gs_out);
+
cmd_buffer->state.emitted_pipeline = pipeline;
}
@@ -1586,17 +1596,6 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer
*cmd_buffer,
cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
}
- if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
- radeon_set_context_reg(cmd_buffer->cs,
R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
-
- if (cmd_buffer->device->physical_device->rad_info.chip_class >=
CIK) {
- radeon_set_uconfig_reg_idx(cmd_buffer->cs,
R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
- } else {
- radeon_set_config_reg(cmd_buffer->cs,
R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
- }
- radeon_set_context_reg(cmd_buffer->cs,
R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
- }
-
radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
_______________________________________________
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
