That is great. Thanks very much.
As soon as I merge Brian's Windows documentation I should be able to put up
an mpir-2.7.0-alpha. This evening hopefully!
Bill.
On 4 April 2014 19:29, Jean-Pierre Flori <jpfl...@gmail.com> wrote:
>
>
> On Thursday, April 3, 2014 11:18:04 AM UTC+2, Bill Hart wrote:
>>
>> That would be great!
>>
>> Here you go
>
> cat /proc/cpuinfo
>
> choupi@pichou:~/mpir/tune$ cat /proc/cpuinfo
> processor : 0
> vendor_id : GenuineIntel
> cpu family : 6
> model : 28
> model name : Intel(R) Atom(TM) CPU N450 @ 1.66GHz
> stepping : 10
> microcode : 0x105
> cpu MHz : 1667.000
> cache size : 512 KB
> physical id : 0
> siblings : 2
> core id : 0
> cpu cores : 1
> apicid : 0
> initial apicid : 0
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm
> constant_tsc arch_perfmon pebs bts rep_good nopl aperfmperf pni dtes64
> monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm movbe lahf_lm dtherm
> bogomips : 3325.07
> clflush size : 64
> cache_alignment : 64
> address sizes : 32 bits physical, 48 bits virtual
> power management:
>
> processor : 1
> vendor_id : GenuineIntel
> cpu family : 6
> model : 28
> model name : Intel(R) Atom(TM) CPU N450 @ 1.66GHz
> stepping : 10
> microcode : 0x105
> cpu MHz : 1000.000
> cache size : 512 KB
> physical id : 0
> siblings : 2
> core id : 0
> cpu cores : 1
> apicid : 1
> initial apicid : 1
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm
> constant_tsc arch_perfmon pebs bts rep_good nopl aperfmperf pni dtes64
> monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm movbe lahf_lm dtherm
> bogomips : 3325.07
> clflush size : 64
> cache_alignment : 64
> address sizes : 32 bits physical, 48 bits virtual
> power management:
>
> make tune
> ...
> Parameters for ./mpn/x86_64/atom/gmp-mparam.h
>
> Using: CPU cycle counter, supplemented by microsecond getrusage()
> speed_precision 1000000, speed_unittime 6.00e-10 secs, CPU freq 1667.00 MHz
> DEFAULT_MAX_SIZE 1000, fft_max_size 50000
>
> /* Generated by tuneup.c, 2014-04-04, gcc 4.6 */
>
> #define MUL_KARATSUBA_THRESHOLD 10
> #define MUL_TOOM3_THRESHOLD 113
> #define MUL_TOOM4_THRESHOLD 197
> #define MUL_TOOM8H_THRESHOLD 199
>
>
> #define SQR_BASECASE_THRESHOLD 0 /* always (native) */
> #define SQR_KARATSUBA_THRESHOLD 16
> #define SQR_TOOM3_THRESHOLD 105
> #define SQR_TOOM4_THRESHOLD 278
> #define SQR_TOOM8_THRESHOLD 286
>
> #define POWM_THRESHOLD 59
>
> #define HGCD_THRESHOLD 70
> #define GCD_DC_THRESHOLD 192
> #define GCDEXT_DC_THRESHOLD 169
> #define JACOBI_BASE_METHOD 3
>
>
> #define DIVREM_1_NORM_THRESHOLD MP_SIZE_T_MAX /* never */
> #define DIVREM_1_UNNORM_THRESHOLD MP_SIZE_T_MAX /* never */
> #define MOD_1_NORM_THRESHOLD 0 /* always */
> #define MOD_1_UNNORM_THRESHOLD 0 /* always */
>
> #define USE_PREINV_DIVREM_1 1 /* native */
> #define USE_PREINV_MOD_1 1
> #define DIVEXACT_1_THRESHOLD 0 /* always */
>
> #define MODEXACT_1_ODD_THRESHOLD 0 /* always (native) */
> #define MOD_1_1_THRESHOLD 7
> #define MOD_1_2_THRESHOLD 8
> #define MOD_1_3_THRESHOLD 12
> #define DIVREM_HENSEL_QR_1_THRESHOLD 126
> #define RSH_DIVREM_HENSEL_QR_1_THRESHOLD 996
> #define DIVREM_EUCLID_HENSEL_THRESHOLD 58
>
> #define ROOTREM_THRESHOLD 6
>
> #define GET_STR_DC_THRESHOLD 20
> #define GET_STR_PRECOMPUTE_THRESHOLD 25
> #define SET_STR_DC_THRESHOLD 248
> #define SET_STR_PRECOMPUTE_THRESHOLD 262
>
> #define MUL_FFT_FULL_THRESHOLD 2496
>
> #define SQR_FFT_FULL_THRESHOLD 1760
>
> #define MULLOW_BASECASE_THRESHOLD 0 /* always */
> #define MULLOW_DC_THRESHOLD 12
> #define MULLOW_MUL_THRESHOLD 2324
>
> #define MULHIGH_BASECASE_THRESHOLD 8
> #define MULHIGH_DC_THRESHOLD 8
> #define MULHIGH_MUL_THRESHOLD 2257
>
> #define MULMOD_2EXPM1_THRESHOLD 14
>
> #define FAC_UI_THRESHOLD 8252
> #define DC_DIV_QR_THRESHOLD 28
> #define DC_DIVAPPR_Q_N_THRESHOLD 14
> #define INV_DIV_QR_THRESHOLD 1442
> #define INV_DIVAPPR_Q_N_THRESHOLD 14
> #define DC_DIV_Q_THRESHOLD 73
> #define INV_DIV_Q_THRESHOLD 2801
> #define DC_DIVAPPR_Q_THRESHOLD 10
> #define INV_DIVAPPR_Q_THRESHOLD 7881
> #define DC_BDIV_QR_THRESHOLD 28
> #define DC_BDIV_Q_THRESHOLD 34
>
>
> /* fft_tuning -- autogenerated by tune-fft */
>
> #define FFT_TAB \
> { { 4, 3 }, { 3, 2 }, { 3, 2 }, { 2, 1 }, { 1, 0 } }
>
> #define MULMOD_TAB \
> { 4, 3, 3, 4, 4, 3, 3, 3, 3, 2, 2, 2, 3, 2, 2, 2, 2, 1, 1 }
>
> #define FFT_N_NUM 19
>
> #define FFT_MULMOD_2EXPP1_CUTOFF 128
>
>
> /* Tuneup completed successfully, took 565 seconds */
>
>
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