#ifndef __MSP430_HEADERS_UCS_H #define __MSP430_HEADERS_UCS_H /* ucs.h * * mspgcc project: MSP430 device headers * unified clock system module * * (c) 2008 by Roberto Padovani * Originally based on MSP430F543x datasheet (slas609) * and MSP430x5xx Family User's Guide (slau208). * */ /* Switches: __MSP430_UCS_BASE__ - base address of Unified Clock System module */ #define UCSCTL0_ __MSP430_UCS_BASE__ + 0x00 /* UCS control register 0 */ sfrw(UCSCTL0, UCSCTL0_); #define UCSCTL1_ __MSP430_UCS_BASE__ + 0x02 /* UCS control register 0 */ sfrw(UCSCTL1, UCSCTL1_); #define UCSCTL2_ __MSP430_UCS_BASE__ + 0x04 /* UCS control register 0 */ sfrw(UCSCTL2, UCSCTL2_); #define UCSCTL3_ __MSP430_UCS_BASE__ + 0x06 /* UCS control register 0 */ sfrw(UCSCTL3, UCSCTL3_); #define UCSCTL4_ __MSP430_UCS_BASE__ + 0x08 /* UCS control register 0 */ sfrw(UCSCTL4, UCSCTL4_); #define UCSCTL5_ __MSP430_UCS_BASE__ + 0x0A /* UCS control register 0 */ sfrw(UCSCTL5, UCSCTL5_); #define UCSCTL6_ __MSP430_UCS_BASE__ + 0x0C /* UCS control register 0 */ sfrw(UCSCTL6, UCSCTL6_); #define UCSCTL7_ __MSP430_UCS_BASE__ + 0x0E /* UCS control register 0 */ sfrw(UCSCTL7, UCSCTL7_); #define UCSCTL8_ __MSP430_UCS_BASE__ + 0x10 /* UCS control register 0 */ sfrw(UCSCTL8, UCSCTL8_); /* UCSCTL0 */ #define MOD0 (1<<3) /* MOD Bit 0 */ #define MOD1 (1<<4) /* MOD Bit 1 */ #define MOD2 (1<<5) /* MOD Bit 2 */ #define MOD3 (1<<6) /* MOD Bit 3 */ #define MOD4 (1<<7) /* MOD Bit 4 */ #define DCO0 (1<<8) /* DCO Tap 0 */ #define DCO1 (1<<9) /* DCO Tap 1 */ #define DCO2 (1<<10) /* DCO Tap 2 */ #define DCO3 (1<<11) /* DCO Tap 3 */ #define DCO4 (1<<12) /* DCO Tap 4 */ /* UCSCTL1 */ #define DISMOD (1<<0) /* Disable Modulation */ #define RSEL0 (1<<4) /* DCO Range Select 0 */ #define RSEL1 (1<<5) /* DCO Range Select 1 */ #define RSEL2 (1<<6) /* DCO Range Select 2 */ /* UCSCTL2 */ #define FLLN0 (1<<0) /* FLL Multiplier Value 0 */ #define FLLN1 (1<<1) /* FLL Multiplier Value 1 */ #define FLLN2 (1<<2) /* FLL Multiplier Value 2 */ #define FLLN3 (1<<3) /* FLL Multiplier Value 3 */ #define FLLN4 (1<<4) /* FLL Multiplier Value 4 */ #define FLLN5 (1<<5) /* FLL Multiplier Value 5 */ #define FLLN6 (1<<6) /* FLL Multiplier Value 6 */ #define FLLN7 (1<<7) /* FLL Multiplier Value 7 */ #define FLLN8 (1<<8) /* FLL Multiplier Value 8 */ #define FLLN9 (1<<9) /* FLL Multiplier Value 9 */ #define FFLD0 (1<<12) /* FLL Divider Value 0 */ #define FFLD1 (1<<13) /* FLL Divider Value 1 */ #define FFLD2 (1<<14) /* FLL Divider Value 2 */ /* Aliases by mspgcc */ #define FFLD_0 (0<<12) /* FLL Divider /1 */ #define FFLD_1 (1<<12) /* FLL Divider /2 */ #define FFLD_2 (2<<12) /* FLL Divider /4 */ #define FFLD_3 (3<<12) /* FLL Divider /8 */ #define FFLD_4 (4<<12) /* FLL Divider /16 */ #define FFLD_5 (5<<12) /* FLL Divider /32 */ #define FFLD_6 (6<<12) /* Reserved, defaults to FLL Divider /32 */ #define FFLD_7 (7<<12) /* Reserved, defaults to FLL Divider /32 */ /* UCSCTL3 */ #define FLLREFDIV0 (1<<0) /* FLL Reference Divider Bit 0 */ #define FLLREFDIV1 (1<<1) /* FLL Reference Divider Bit 1 */ #define FLLREFDIV2 (1<<2) /* FLL Reference Divider Bit 2 */ #define SELREF0 (1<<4) /* FLL Reference Select Bit 0 */ #define SELREF1 (1<<5) /* FLL Reference Select Bit 1 */ #define SELREF2 (1<<6) /* FLL Reference Select Bit 2 */ /* Aliases by mspgcc */ #define FLLREFDIV_0 (0<<0) /* FLL Reference Divider /1 */ #define FLLREFDIV_1 (1<<0) /* FLL Reference Divider /2 */ #define FLLREFDIV_2 (2<<0) /* FLL Reference Divider /4 */ #define FLLREFDIV_3 (3<<0) /* FLL Reference Divider /8 */ #define FLLREFDIV_4 (4<<0) /* FLL Reference Divider /12 */ #define FLLREFDIV_5 (5<<0) /* FLL Reference Divider /16 */ #define FLLREFDIV_6 (6<<0) /* Reserved, defaults to /16 */ #define FLLREFDIV_7 (7<<0) /* Reserved, defaults to /16 */ #define SELREF_0 (0<<4) /* FLL Reference Select XT1CLK */ #define SELREF_1 (1<<4) /* FLL Reference Select Reserved, defaults to XT1CLK */ #define SELREF_2 (2<<4) /* FLL Reference Select REFOCLK */ #define SELREF_3 (3<<4) /* FLL Reference Select Reserved, defaults to REFOCLK */ #define SELREF_4 (4<<4) /* FLL Reference Select Reserved, defaults to REFOCLK */ #define SELREF_5 (5<<4) /* FLL Reference Select XT2CLK when available, REFOCLK otherwise */ #define SELREF_6 (6<<4) /* FLL Reference Select Reserved, defaults to XT2CLK when available, REFOCLK otherwise */ #define SELREF_7 (7<<4) /* FLL Reference Select Reserved, defaults to XT2CLK when available, REFOCLK otherwise */ /* UCSCTL4 */ #define SELM0 (1<<0) /* MCLK Source Select Bit 0 */ #define SELM1 (1<<1) /* MCLK Source Select Bit 1 */ #define SELM2 (1<<2) /* MCLK Source Select Bit 2 */ #define SELS0 (1<<4) /* SMCLK Source Select Bit 0 */ #define SELS1 (1<<5) /* SMCLK Source Select Bit 1 */ #define SELS2 (1<<6) /* SMCLK Source Select Bit 2 */ #define SELA0 (1<<8) /* ACLK Source Select Bit 0 */ #define SELA1 (1<<9) /* ACLK Source Select Bit 1 */ #define SELA2 (1<<10) /* ACLK Source Select Bit 2 */ /* Aliases by mspgcc */ #define SELM_0 (0<<0) /* MCLK Source Select XT1CLK */ #define SELM_1 (1<<0) /* MCLK Source Select VLOCLK */ #define SELM_2 (2<<0) /* MCLK Source Select REFOCLK */ #define SELM_3 (3<<0) /* MCLK Source Select DCOCLK */ #define SELM_4 (4<<0) /* MCLK Source Select DCOCLKDIV */ #define SELM_5 (5<<0) /* MCLK Source Select XT2CLK when available, DCOCLKDIV otherwise */ #define SELM_6 (6<<0) /* Reserved, defaults to XT2CLK when available, DCOCLKDIV otherwise */ #define SELM_7 (7<<0) /* Reserved, defaults to XT2CLK when available, DCOCLKDIV otherwise */ #define SELS_0 (0<<4) /* SMCLK Source Select XT1CLK */ #define SELS_1 (1<<4) /* SMCLK Source Select VLOCLK */ #define SELS_2 (2<<4) /* SMCLK Source Select REFOCLK */ #define SELS_3 (3<<4) /* SMCLK Source Select DCOCLK */ #define SELS_4 (4<<4) /* SMCLK Source Select DCOCLKDIV */ #define SELS_5 (5<<4) /* SMCLK Source Select XT2CLK when available, DCOCLKDIV otherwise */ #define SELS_6 (6<<4) /* Reserved, defaults to XT2CLK when available, DCOCLKDIV otherwise */ #define SELS_7 (7<<4) /* Reserved, defaults to XT2CLK when available, DCOCLKDIV otherwise */ #define SELA_0 (0<<8) /* ACLK Source Select XT1CLK */ #define SELA_1 (1<<8) /* ACLK Source Select VLOCLK */ #define SELA_2 (2<<8) /* ACLK Source Select REFOCLK */ #define SELA_3 (3<<8) /* ACLK Source Select DCOCLK */ #define SELA_4 (4<<8) /* ACLK Source Select DCOCLKDIV */ #define SELA_5 (5<<8) /* ACLK Source Select XT2CLK when available, DCOCLKDIV otherwise */ #define SELA_6 (6<<8) /* Reserved, defaults to XT2CLK when available, DCOCLKDIV otherwise */ #define SELA_7 (7<<8) /* Reserved, defaults to XT2CLK when available, DCOCLKDIV otherwise */ /* UCSCTL5 */ #define DIVM0 (1<<0) /* MCLK Divider Bit 0 */ #define DIVM1 (1<<1) /* MCLK Divider Bit 1 */ #define DIVM2 (1<<2) /* MCLK Divider Bit 2 */ #define DIVS0 (1<<4) /* SMCLK Divider Bit 0 */ #define DIVS1 (1<<5) /* SMCLK Divider Bit 1 */ #define DIVS2 (1<<6) /* SMCLK Divider Bit 2 */ #define DIVA0 (1<<8) /* ACLK Divider Bit 0 */ #define DIVA1 (1<<9) /* ACLK Divider Bit 1 */ #define DIVA2 (1<<10) /* ACLK Divider Bit 2 */ #define DIVPA0 (1<<12) /* External ACLK Divider Bit 0 */ #define DIVPA1 (1<<13) /* External ACLK Divider Bit 1 */ #define DIVPA2 (1<<14) /* External ACLK Divider Bit 2 */ /* Aliases by mspgcc */ #define DIVM_0 (0<<0) /* MCLK Source Divider /1 */ #define DIVM_1 (1<<0) /* MCLK Source Divider /2 */ #define DIVM_2 (2<<0) /* MCLK Source Divider /4 */ #define DIVM_3 (3<<0) /* MCLK Source Divider /8 */ #define DIVM_4 (4<<0) /* MCLK Source Divider /16 */ #define DIVM_5 (5<<0) /* MCLK Source Divider /32 */ #define DIVM_6 (6<<0) /* Reserved, defaults to /32 */ #define DIVM_7 (7<<0) /* Reserved, defaults to /32 */ #define DIVS_0 (0<<4) /* SMCLK Source Divider /1 */ #define DIVS_1 (1<<4) /* SMCLK Source Divider /2 */ #define DIVS_2 (2<<4) /* SMCLK Source Divider /4 */ #define DIVS_3 (3<<4) /* SMCLK Source Divider /8 */ #define DIVS_4 (4<<4) /* SMCLK Source Divider /16 */ #define DIVS_5 (5<<4) /* SMCLK Source Divider /32 */ #define DIVS_6 (6<<4) /* Reserved, defaults to /32 */ #define DIVS_7 (7<<4) /* Reserved, defaults to /32 */ #define DIVA_0 (0<<8) /* ACLK Source Divider /1 */ #define DIVA_1 (1<<8) /* ACLK Source Divider /2 */ #define DIVA_2 (2<<8) /* ACLK Source Divider /4 */ #define DIVA_3 (3<<8) /* ACLK Source Divider /8 */ #define DIVA_4 (4<<8) /* ACLK Source Divider /16 */ #define DIVA_5 (5<<8) /* ACLK Source Divider /32 */ #define DIVA_6 (6<<8) /* Reserved, defaults to /32 */ #define DIVA_7 (7<<8) /* Reserved, defaults to /32 */ #define DIVPA_0 (0<<12) /* External ACLK Source Divider /1 */ #define DIVPA_1 (1<<12) /* External ACLK Source Divider /2 */ #define DIVPA_2 (2<<12) /* External ACLK Source Divider /4 */ #define DIVPA_3 (3<<12) /* External ACLK Source Divider /8 */ #define DIVPA_4 (4<<12) /* External ACLK Source Divider /16 */ #define DIVPA_5 (5<<12) /* External ACLK Source Divider /32 */ #define DIVPA_6 (6<<12) /* Reserved, defaults to /32 */ #define DIVPA_7 (7<<12) /* Reserved, defaults to /32 */ /* UCSCTL6 */ #define XT1OFF (1<<0) /* High Frequency XT1 Disable */ #define SMCLKOFF (1<<1) /* SMCLK Off */ #define XCAP0 (1<<2) /* Capacitor Selection 0 */ #define XCAP1 (1<<3) /* Capacitor Selection 1 */ #define XT1BYPASS (1<<4) /* XT1 Bypass Externally */ #define XTS (1<<5) /* HF Mode Select for XT1 */ #define XT1DRIVE0 (1<<6) /* XT1 Drive Bit 0 */ #define XT1DRIVE1 (1<<7) /* XT1 Drive Bit 1 */ #define XT2OFF (1<<8) /* High Frequency XT2 Disable */ #define XT2BYPASS (1<<12) /* XT2 Bypass Externally */ #define XT2DRIVE0 (1<<14) /* XT2 Drive Bit 0 */ #define XT2DRIVE1 (1<<15) /* XT2 Drive Bit 1 */ /* Aliases by mspgcc */ #define XCAP_0 (0<<2) /* Capacitor Selection (see Datasheet) */ #define XCAP_1 (1<<2) /* Capacitor Selection (see Datasheet) */ #define XCAP_2 (2<<2) /* Capacitor Selection (see Datasheet) */ #define XCAP_3 (3<<2) /* Capacitor Selection (see Datasheet) */ #define XT1DRIVE_0 (0<<6) /* LF Lowest Current, HF between 4MHz and 8MHz */ #define XT1DRIVE_1 (1<<6) /* LF Increasing Current, HF between 8MHz and 16MHz */ #define XT1DRIVE_2 (2<<6) /* LF Increasing Current, HF between 16MHz and 24MHz */ #define XT1DRIVE_3 (3<<6) /* LF Highest Current, HF between 24MHz and 32MHz */ #define XT2DRIVE_0 (0<<12) /* Lowest Current, HF between 4MHz and 8MHz */ #define XT2DRIVE_1 (1<<12) /* Increasing Current, HF between 8MHz and 16MHz */ #define XT2DRIVE_2 (2<<12) /* Increasing Current, HF between 16MHz and 24MHz */ #define XT2DRIVE_3 (3<<12) /* Highest Current, HF between 24MHz and 32MHz */ /* UCSCTL7 */ #define DCOFFG (1<<0) /* DCO Fault Flag */ #define XT1LFOFFG (1<<1) /* XT1 Low Frequency Mode Fault Flag */ #define XT1HFOFFG (1<<2) /* XT1 High Frequency Mode Fault Flag */ #define XT2OFFG (1<<3) /* XT2 Fault Flag */ #define FLLULIFG (1<<4) /* FLL Unlock Interrupt Flag */ #define FLLUNLOCK0 (1<<8) /* FLL Unlock Condition 0 */ #define FLLUNLOCK1 (1<<9) /* FLL Unlock Condition 1 */ #define FLLUNLOCKHIS0 (1<<10) /* FLL Unlock History 0 */ #define FLLUNLOCKHIS1 (1<<11) /* FLL Unlock History 1 */ #define FLLULIE (1<<12) /* FLL Unlock Interrupt Enable */ #define FLLWARNEN (1<<13) /* FLL Warning Enable */ /* Aliases by mspgcc */ #define FLLUNLOCK_0 (0<<8) /* FLL Locked */ #define FLLUNLOCK_1 (1<<8) /* DCO too Low */ #define FLLUNLOCK_2 (2<<8) /* DCO too Fast */ #define FLLUNLOCK_3 (3<<8) /* DCO Out of Range */ #define FLLUNLOCKHIS_0 (0<<10) /* FLL Locked */ #define FLLUNLOCKHIS_1 (1<<10) /* DCO too Low */ #define FLLUNLOCKHIS_2 (2<<10) /* DCO too Fast */ #define FLLUNLOCKHIS_3 (3<<10) /* DCO Both too Low and too Fast */ /* UCSCTL8 */ #define MODOSCREQEN (1<<3) /* MODOSC Clock Request Enable */ #define UCSCTL8_MASK (0x0317) /* Bit 0,1,2,4,8,9 MUST always be written as 1 !!!!! /* Aliases by mspgcc */ #define MODOSCREQEN_0 (UCSCTL8_MASK) /* Correctly Clear MODOSC: UCSCTL8 = MODOSCREQEN_0 */ #define MODOSCREQEN_1 ((UCSCTL8_MASK)|MODOSCREQEN) /* Correctly Set MODOSC : UCSCTL8 = MODOSCREQEN_1 */ #endif /* __MSP430_HEADERS_UCS_H */