This is an automated email from Gerrit. Alamy Liu ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3306
-- gerrit commit b2bc52cf509e7ac8fb80f5674d7bf966c18d41d9 Author: Alamy Liu <[email protected]> Date: Wed Oct 7 10:42:07 2015 -0700 arm_dpm: debug reason (target->debug_reason) in armv8 version. ARMv8 has differnet and more status (debug_reason) entering Debug state. The old arm_dpm_report_dscr() does not decode ARMv8 reason properly. Introduce armv8_edscr_debug_reason() for ARMv8 targets. Change-Id: Ied624ba6733e13fb72d6db1d158b078beafd13e1 Signed-off-by: Alamy Liu <[email protected]> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 5e93ac5..1c07e79 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1139,11 +1139,7 @@ static int aarch64_debug_entry(struct target *target) #endif /* Examine debug reason */ - arm_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_edscr); - mem_ap_sel_read_atomic_u32(swjdp, armv8->debug_ap, - armv8->debug_base + CPUDBG_DESR, &tmp); - if ((tmp & 0x7) == 0x4) - target->debug_reason = DBG_REASON_SINGLESTEP; + target->debug_reason = armv8_edscr_debug_reason(aarch64->cpudbg_edscr); /* save address of instruction that triggered the watchpoint? */ if (target->debug_reason == DBG_REASON_WATCHPOINT) { diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 0cb69ee..fe22f25 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -22,6 +22,7 @@ #endif #include "arm.h" +#include "armv8.h" #include "arm_dpm.h" #include <jtag/jtag.h> #include "register.h" @@ -1134,6 +1135,63 @@ void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr) } } +enum target_debug_reason armv8_edscr_debug_reason(uint32_t edscr) +{ + enum target_debug_reason reason = DBG_REASON_UNDEFINED; + + switch (EDSCR_STATUS(edscr)) { + case ARMV8_EDSCR_STATUS_NDBG: /* Non-debug */ + case ARMV8_EDSCR_STATUS_RESTART: /* Restarting */ + reason = DBG_REASON_NOTHALTED; + break; + + case ARMV8_EDSCR_STATUS_EDBGRQ: /* External debug request */ + reason = DBG_REASON_DBGRQ; + break; + + case ARMV8_EDSCR_STATUS_BP: /* Breakpoint */ + reason = DBG_REASON_BREAKPOINT; + break; + + case ARMV8_EDSCR_STATUS_WP: /* Watchpoint */ + reason = DBG_REASON_WATCHPOINT; + break; + + case ARMV8_EDSCR_STATUS_HALT_NORM: /* Step, normal */ + case ARMV8_EDSCR_STATUS_HALT_EXCL: /* Step, exclusive */ + case ARMV8_EDSCR_STATUS_HALT_NOSYND:/* Step, no syndrome */ + reason = DBG_REASON_SINGLESTEP; + break; + + case ARMV8_EDSCR_STATUS_OS_UL: /* OS unlock catch */ + reason = DBG_REASON_OSUL; + break; + + case ARMV8_EDSCR_STATUS_RESET: /* Reset catch */ + reason = DBG_REASON_RESET; + break; + + case ARMV8_EDSCR_STATUS_HLT: /* HLT instruction */ + reason = DBG_REASON_HLT; + break; + + case ARMV8_EDSCR_STATUS_SW_ACC: /* Software access to debug register */ + reason = DBG_REASON_SWACC; + break; + + case ARMV8_EDSCR_STATUS_EXCP: /* Exception catch */ + reason = DBG_REASON_EXCP; + break; + + default: + /* We don't really need this as the value had been pre-assigned */ + reason = DBG_REASON_UNDEFINED; + break; + } // end of switch() + + return reason; +} + /*----------------------------------------------------------------------*/ /* diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index bce9633..ffeddfc 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -207,6 +207,7 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar); void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr); +enum target_debug_reason armv8_edscr_debug_reason(uint32_t edscr); #endif /* __ARM_DPM_H */ diff --git a/src/target/target.h b/src/target/target.h index b7a3c81..3df2a4b 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -78,6 +78,10 @@ enum target_reset_mode { RESET_INIT = 3, /* reset and halt target out of reset, then run init script */ }; +/* + * Mapping of DSCR.STATUS, bits[5:0] + * See arm_dpm.c::arm_dpm_report_dscr() + */ enum target_debug_reason { DBG_REASON_DBGRQ = 0, DBG_REASON_BREAKPOINT = 1, @@ -86,7 +90,12 @@ enum target_debug_reason { DBG_REASON_SINGLESTEP = 4, DBG_REASON_NOTHALTED = 5, DBG_REASON_EXIT = 6, - DBG_REASON_UNDEFINED = 7, + DBG_REASON_OSUL = 7, /* ARMv8: OS Unlock catch */ + DBG_REASON_RESET = 8, /* ARMv8: Reset catch */ + DBG_REASON_HLT = 9, /* ARMv8: HLT instruction */ + DBG_REASON_SWACC = 10, /* ARMv8: Software access to debug register */ + DBG_REASON_EXCP = 11, /* ARMv8: Exception catch */ + DBG_REASON_UNDEFINED = 12, }; enum target_endianness { -- ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140 _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
