The accurate timing implementation in this patch gets the wall clock counter via
cntvct_el0 register access. This call is portable to all aarch64 architectures
and has been verified on an 64-bit arm server.
Suggested-by: Yanqin Wei <yanqin....@arm.com>
Signed-off-by: Malvika Gupta <malvika.gu...@arm.com>
Reviewed-by: Ilya Maximets <i.maxim...@ovn.org>
---
v2:
- Updated patch subject to remove redundant words and enhance clarity.
- Modify code to write directly to s->last_tsc instead of writing to a local
variable first and then assigning it to s->last_tsc.
---
lib/dpif-netdev-perf.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/lib/dpif-netdev-perf.h b/lib/dpif-netdev-perf.h
index ce369375b..72645b6b3 100644
--- a/lib/dpif-netdev-perf.h
+++ b/lib/dpif-netdev-perf.h
@@ -220,6 +220,10 @@ cycles_counter_update(struct pmd_perf_stats *s)
asm volatile("rdtsc" : "=a" (l), "=d" (h));
return s->last_tsc = ((uint64_t) h << 32) | l;
+#elif !defined(_MSC_VER) && defined(__aarch64__)
+ asm volatile("mrs %0, cntvct_el0" : "=r" (s->last_tsc));
+
+ return s->last_tsc;
#elif defined(__linux__)
return rdtsc_syscall(s);
#else
--
2.17.1
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