Submitted By: Andrey Vul <andrey dot vul at gmail dot com>
Date: 2007-03-03
Initial Package Version: 4.1.1
Upstream Status: Not Submitted - Hack
Origin: Andrey Vul
Description: Adds SSE3 support to amd64 processors.
             SSE2 for the original Athlon 64 (for compatibility) can be achieved with
             -mno-sse3 switch.
             It was too much work to add a new sub-architecture.
             Documentation has been updated (SSE3 support in K8).
diff -Naur gcc-4.1.1.orig/gcc/config/i386/i386.c gcc-4.1.1/gcc/config/i386/i386.c
--- gcc-4.1.1.orig/gcc/config/i386/i386.c	2006-05-17 01:11:59.000000000 +0000
+++ gcc-4.1.1/gcc/config/i386/i386.c	2007-03-03 02:45:27.128363200 +0000
@@ -1264,15 +1264,15 @@
       {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
 				      | PTA_3DNOW_A | PTA_SSE},
       {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
-			       | PTA_SSE | PTA_SSE2 },
+			       | PTA_SSE | PTA_SSE2 | PTA_SSE3},
       {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
-				      | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
+				      | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_SSE3},
       {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
-				      | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
+				      | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_SSE3},
       {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
-				      | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
+				      | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_SSE3},
       {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
-				      | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
+				      | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_SSE3},
     };
 
   int const pta_size = ARRAY_SIZE (processor_alias_table);
diff -Naur gcc-4.1.1.orig/gcc/doc/g++.1 gcc-4.1.1/gcc/doc/g++.1
--- gcc-4.1.1.orig/gcc/doc/g++.1	2006-05-24 23:54:59.000000000 +0000
+++ gcc-4.1.1/gcc/doc/g++.1	2007-03-03 02:46:05.373356800 +0000
@@ -8414,7 +8414,7 @@
 .IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4
 .IX Item "k8, opteron, athlon64, athlon-fx"
 \&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support.  (This supersets
-\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
+\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
 .IP "\fIwinchip\-c6\fR" 4
 .IX Item "winchip-c6"
 \&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
diff -Naur gcc-4.1.1.orig/gcc/doc/gcc.1 gcc-4.1.1/gcc/doc/gcc.1
--- gcc-4.1.1.orig/gcc/doc/gcc.1	2006-05-24 23:54:59.000000000 +0000
+++ gcc-4.1.1/gcc/doc/gcc.1	2007-03-03 02:46:23.619593600 +0000
@@ -8414,7 +8414,7 @@
 .IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4
 .IX Item "k8, opteron, athlon64, athlon-fx"
 \&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support.  (This supersets
-\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
+\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
 .IP "\fIwinchip\-c6\fR" 4
 .IX Item "winchip-c6"
 \&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
diff -Naur gcc-4.1.1.orig/gcc/doc/gcc.info gcc-4.1.1/gcc/doc/gcc.info
--- gcc-4.1.1.orig/gcc/doc/gcc.info	2006-05-24 23:54:54.000000000 +0000
+++ gcc-4.1.1/gcc/doc/gcc.info	2007-03-03 20:05:00.306588800 +0000
@@ -8892,7 +8892,7 @@
 
     _k8, opteron, athlon64, athlon-fx_
           AMD K8 core based CPUs with x86-64 instruction set support.
-          (This supersets MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and
+          (This supersets MMX, SSE, SSE2, SSE3, 3dNOW!, enhanced 3dNOW! and
           64-bit instruction set extensions.)
 
     _winchip-c6_
diff -Naur gcc-4.1.1.orig/gcc/doc/invoke.texi gcc-4.1.1/gcc/doc/invoke.texi
--- gcc-4.1.1.orig/gcc/doc/invoke.texi	2006-02-14 15:08:01.000000000 +0000
+++ gcc-4.1.1/gcc/doc/invoke.texi	2007-03-03 20:05:20.435532800 +0000
@@ -9038,7 +9038,7 @@
 instruction set support.
 @item k8, opteron, athlon64, athlon-fx
 AMD K8 core based CPUs with x86-64 instruction set support.  (This supersets
-MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
+MMX, SSE, SSE2, SSE3, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
 @item winchip-c6
 IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
 set support.