From 6fc3adb6e496c3186c7bda7251060e15a8e0946a Mon Sep 17 00:00:00 2001
From: Raghuveer Devulapalli <raghuveer.devulapalli@intel.com>
Date: Thu, 21 Nov 2024 14:59:29 -0800
Subject: [PATCH v4 2/2] Use consistent logic in configure and meson to
 generate USE_SSE42_CRC32C

---
 meson.build | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/meson.build b/meson.build
index 671ac7052b..5f199b4b7c 100644
--- a/meson.build
+++ b/meson.build
@@ -2236,11 +2236,9 @@ if host_cpu == 'x86' or host_cpu == 'x86_64'
 
     sse42_crc_prog = '''
 #include <nmmintrin.h>
-#ifdef TEST_SSE42_WITH_ATTRIBUTE
 #if defined(__has_attribute) && __has_attribute (target)
 __attribute__((target("sse4.2")))
 #endif
-#endif
 int main(void)
 {
     unsigned int crc = 0;
@@ -2251,13 +2249,12 @@ int main(void)
 }
 '''
 
-    if cc.links(sse42_crc_prog, name: '_mm_crc32_u8 and _mm_crc32_u32 without -msse4.2',
-          args: test_c_args)
+    if cc.get_define('__SSE4_2__') != ''
       # Use Intel SSE 4.2 unconditionally.
       cdata.set('USE_SSE42_CRC32C', 1)
       have_optimized_crc = true
     elif cc.links(sse42_crc_prog, name: '_mm_crc32_u8 and _mm_crc32_u32 with sse4.2 function attribute',
-          args: test_c_args + ['-D TEST_SSE42_WITH_ATTRIBUTE'])
+          args: test_c_args)
       # Use Intel SSE 4.2, with runtime check. The CPUID instruction is needed for
       # the runtime check.
       cflags_crc += '-msse4.2'
-- 
2.43.0

