CVSROOT: /cvs Module name: ports Changes by: [email protected] 2025/08/31 10:56:15
Modified files:
www/liferea : Makefile
Log message:
WANTLIB+=drm_intel is MD, mark it as so
CVSROOT: /cvs Module name: ports Changes by: [email protected] 2025/08/31 10:56:15
Modified files:
www/liferea : Makefile
Log message:
WANTLIB+=drm_intel is MD, mark it as so