Since the 405 CPU family was phased out, the SLER SPR has no users
anymore.
Signed-off-by: Cédric Le Goater <c...@redhat.com>
---
target/ppc/cpu.h | 2 --
target/ppc/helper.h | 1 -
target/ppc/spr_common.h | 1 -
target/ppc/helper_regs.c | 10 ----------
target/ppc/misc_helper.c | 5 -----
target/ppc/translate.c | 6 ------
6 files changed, 25 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0fe44cedb1b3..2f3741860076 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1620,7 +1620,6 @@ void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
target_ulong load_40x_pit(CPUPPCState *env);
void store_40x_pit(CPUPPCState *env, target_ulong val);
void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
-void store_40x_sler(CPUPPCState *env, uint32_t val);
void store_40x_tcr(CPUPPCState *env, target_ulong val);
void store_40x_tsr(CPUPPCState *env, target_ulong val);
void store_booke_tcr(CPUPPCState *env, target_ulong val);
@@ -2172,7 +2171,6 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_7XX_PMC1 (0x3B9)
#define SPR_7XX_PMC2 (0x3BA)
#define SPR_7XX_SIAR (0x3BB)
-#define SPR_405_SLER (0x3BB)
#define SPR_7XX_MMCR1 (0x3BC)
#define SPR_405_SU0R (0x3BC)
#define SPR_401_SKR (0x3BC)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5a77e761bd3f..86f3bbc087f6 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -753,7 +753,6 @@ DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void,
env, tl)
DEF_HELPER_FLAGS_2(store_40x_tsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_40x_pid, void, env, tl)
DEF_HELPER_2(store_40x_dbcr0, void, env, tl)
-DEF_HELPER_2(store_40x_sler, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_3(store_ibatl, void, env, i32, tl)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 01aff449bccc..e98fb07bb285 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -138,7 +138,6 @@ void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn);
void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn);
void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
-void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn);
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 3ad4273c1649..1e5ba9a1c64b 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -354,16 +354,6 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value,
int alter_hv)
}
#ifndef CONFIG_USER_ONLY
-void store_40x_sler(CPUPPCState *env, uint32_t val)
-{
- /* XXX: TO BE FIXED */
- if (val != 0x00000000) {
- cpu_abort(env_cpu(env),
- "Little-endian regions are not supported by now\n");
- }
- env->spr[SPR_405_SLER] = val;
-}
-
void check_tlb_flush(CPUPPCState *env, bool global)
{
CPUState *cs = env_cpu(env);
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index f0ca80153b2b..78bb29d441a7 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -404,11 +404,6 @@ void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong
val)
/* Bits 28 & 29 affect reset or shutdown. */
store_40x_dbcr0(env, val);
}
-
-void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
-{
- store_40x_sler(env, val);
-}
#endif
/*****************************************************************************/
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 80638ab53597..918bf8f3a0cc 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -967,12 +967,6 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int
gprn)
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
-void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
-{
- translator_io_start(&ctx->base);
- gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]);
-}
-
void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
--
2.47.1
