Hi Joel, > From: Joel Stanley <[email protected]> > Sent: Thursday, February 6, 2025 12:55 PM > To: Jamin Lin <[email protected]> > Cc: Andrew Jeffery <[email protected]>; Cédric Le Goater > <[email protected]>; Peter Maydell <[email protected]>; Steven Lee > <[email protected]>; Troy Lee <[email protected]>; open > list:ASPEED BMCs <[email protected]>; open list:All patches CC here > <[email protected]>; Troy Lee <[email protected]>; Yunlin > Tang <[email protected]> > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > Hi Jamin, > > On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery <[email protected]> > wrote: > > Thanks, I'll consider this updated diagram as well while I put my own > > together from the other pieces of info you've provided. > > When you send the next version, please try to separate your code cleanups and > minor renames into a different patch. It makes it easier to see what you're > adding. > > Thanks, > > Joel
Thanks for suggestion. Cedric, also made the same suggestion in patch 0, https://patchwork.kernel.org/project/qemu-devel/cover/[email protected]/ I think I will re-send this first. 1. INTC rename/prereqs/cleanups hw/intc/aspeed: Rename INTC to INTC0 hw/intc/aspeed: Support different memory region ops hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 hw/intc/aspeed: Support setting different memory and register size hw/intc/aspeed: Introduce helper functions for enable and status registers hw/intc/aspeed: Add ID to trace events for better debugging hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin
