From: Anton Blanchard <[email protected]> Masked vector reduction instructions must not use v0 as a source register. Check rs1 and rs2 against the mask register when vm=0.
Signed-off-by: Anton Blanchard <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5b72926b3c..e65356eb7c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3265,6 +3265,8 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && + require_vm(a->vm, a->rs1) && + require_vm(a->vm, a->rs2) && vext_check_reduction(s, a->rs2); } -- 2.53.0
