On Wed, 29 Apr 2026 at 08:38, Philippe Mathieu-Daudé <[email protected]> wrote: > > On 28/4/26 11:33, Peter Maydell wrote: > > Currently npcm7xx_fiu_flash_ops provides no .impl substruct; this > > means that it gets the default of "implements 1, 2 and 4 byte aligned > > accesses". This is more constrained than the device permits in its > > .valid substruct, and also narrower than the functions are written to > > handle. > > > > Add a .impl substruct matching the .valid substruct; this means that > > all guest accesses are handled directly by the read and write > > functions, and are never synthesized by the memory subsystem > > performing multiple accesses to the device (which would not behave > > correctly, as these read and write fucntions have side effects). > > Typo "functions". > > > > > Based-on-a-patch-by: CJ Chen <[email protected]> > > Signed-off-by: Peter Maydell <[email protected]> > > --- > > hw/ssi/npcm7xx_fiu.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c > > index 02707de350..2d5bed005a 100644 > > --- a/hw/ssi/npcm7xx_fiu.c > > +++ b/hw/ssi/npcm7xx_fiu.c > > @@ -250,6 +250,11 @@ static const MemoryRegionOps npcm7xx_fiu_flash_ops = { > > .read = npcm7xx_fiu_flash_read, > > .write = npcm7xx_fiu_flash_write, > > .endianness = DEVICE_LITTLE_ENDIAN, > > + .impl = { > > + .min_access_size = 1, > > + .max_access_size = 8, > > IMO this device should be adapted to have byte granularity ops handlers, > thus .max_access_size = 1.
Looking at the implementation that doesn't look like it would be possible. The implementation does operations to start an SSI transfer, then transfers the number of bytes written. That makes "guest does an 8 byte write" different from "guest does 8 separate byte writes", and so the read/write fns need to really handle all the possible access sizes. thanks -- PMM
