As these operations doesn't use the fpstatus pointer we can be smarter
about allocating it. The negh can also be done with a bitwise xor rather
than calling a helper.
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
---
target/arm/translate-a64.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 5baf0261ff..da3c7bfa85 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10801,6 +10801,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
TCGv_i32 tcg_rmode = NULL;
TCGv_ptr tcg_fpstatus = NULL;
bool need_rmode = false;
+ bool need_fpst = true;
int rmode;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
@@ -10917,6 +10918,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
+ case 0x2f: /* FABS */
+ case 0x6f: /* FNEG */
+ need_fpst = false;
+ break;
default:
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
@@ -10970,6 +10975,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x7b: /* FCVTZU */
gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
break;
+ case 0x6f: /* FNEG */
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+ break;
default:
g_assert_not_reached();
}
@@ -11013,6 +11021,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x59: /* FRINTX */
gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
break;
+ case 0x2f: /* FABS */
+ gen_helper_advsimd_absh(tcg_res, tcg_op);
+ break;
+ case 0x6f: /* FNEG */
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+ break;
default:
g_assert_not_reached();
}
--
2.15.1
