On 1/3/20 2:33 PM, LIU Zhiwei wrote:
> The 32 vector registers will be viewed as a continuous memory block.
> It avoids the convension between element index and (regno,offset).
> Thus elements can be directly accessed by offset from the first vector
> base address.
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> ---
> target/riscv/cpu.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0adb307f32..af66674461 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -93,9 +93,23 @@ typedef struct CPURISCVState CPURISCVState;
>
> #include "pmp.h"
>
> +#define RV_VLEN_MAX 4096
> +
> struct CPURISCVState {
> target_ulong gpr[32];
> uint64_t fpr[32]; /* assume both F and D extensions */
> +
> + /* vector coprocessor state. */
> + struct {
> + uint64_t vreg[32 * RV_VLEN_MAX / 64];
Missing alignment.
> + target_ulong vxrm;
> + target_ulong vxsat;
> + target_ulong vl;
> + target_ulong vstart;
> + target_ulong vtype;
> + } vext;
> +
> + bool foflag;
Remove this. As discussed before, you don't need it. Faulting behaviour
should be handled with the proper interfaces.
r~
