On 8/6/20 3:46 AM, frank.ch...@sifive.com wrote:
> +static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz, bool
> is_ldst)
> {
> - return simd_maxsz(desc) << vext_lmul(desc);
> + /*
> + * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
> + * so vlen in bytes (vlenb) is encoded as maxsz.
> + */
> + uint32_t vlenb = simd_maxsz(desc);
> +
> + if (is_ldst) {
> + /*
> + * Vector load/store instructions have the EEW encoded
> + * directly in the instructions. The maximum vector size is
> + * calculated with EMUL rather than LMUL.
> + */
> + uint32_t eew = ctzl(esz);
> + uint32_t sew = vext_sew(desc);
> + uint32_t lmul = vext_lmul(desc);
> + int32_t emul = eew - sew + lmul;
> + uint32_t emul_r = emul < 0 ? 0 : emul;
> + return 1 << (ctzl(vlenb) + emul_r - ctzl(esz));
As I said before, the is_ldst instructions should put the EEW and EMUL values
into the SEW and LMUL desc fields, so that this does not need to be
special-cased at all.
> + /* Return VLMAX */
> + return 1 << (ctzl(vlenb) + vext_lmul(desc) - ctzl(esz));
This is overly complicated.
(1) 1 << ctzl(vlenb) == vlenb.
(2) I'm not sure why esz is not already a log2 number.
This ought to look more like
int scale = lmul - esz;
return (scale < 0
? vlenb >> -scale
: vlenb << scale);
r~
