On Fri, Aug 14, 2020 at 9:41 AM Bin Meng <bmeng...@gmail.com> wrote:
>
> From: Bin Meng <bin.m...@windriver.com>
>
> RISC-V machines do not instantiate RISC-V CPUs directly, instead
> they do that via the hart array. Add a new property for the reset
> vector address to allow the value to be passed to the CPU, before
> CPU is realized.
>
> Signed-off-by: Bin Meng <bin.m...@windriver.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
>
> hw/riscv/riscv_hart.c | 3 +++
> include/hw/riscv/riscv_hart.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index f59fe52..613ea2a 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -31,6 +31,8 @@ static Property riscv_harts_props[] = {
> DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
> DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
> DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
> + DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
> + DEFAULT_RSTVEC),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int
> idx,
> char *cpu_type, Error **errp)
> {
> object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
> + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
> s->harts[idx].env.mhartid = s->hartid_base + idx;
> qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
> return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
> diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
> index c75856f..77aa4bc 100644
> --- a/include/hw/riscv/riscv_hart.h
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState {
> uint32_t num_harts;
> uint32_t hartid_base;
> char *cpu_type;
> + uint64_t resetvec;
> RISCVCPU *harts;
> } RISCVHartArrayState;
>
> --
> 2.7.4
>
>
