This is a v2 because it's a respin of "target/arm: More v8.1M
features". The bad news is it's nearly doubled in length. The good
news is that this is because the new patches on the end are enough to
implement all the remaining missing v8.1M specifics to the point
where we can provide a Cortex-M55 CPU. (There is as yet no board
model that uses the Cortex-M55, though; that's next on my todo list.)
As before, the series is a mix of bugfixes and new features:
In the bugfix category:
* RAZWI (or BusFault for unprivileged accesses) the whole of the
system PPB address range, not just the SCS
* Don't clobber ID_PFR1.Security on M-profile
* Don't allow VMRS/VMSR to fp sysregs that don't exist on M-profile
* CCR.BFHFNMIGN should RAZ/WI for Nonsecure if AIRCR.BFHFNMINS == 0
* The change in commit 077d7449100d824a4 to handle "bad returns from
NMI/HardFault forcibly deactivate those exceptions" wasn't quite
right; we would deactivate those exceptions but generally not
trigger the illegal exception return that we ought to
* fix a typo in the name we give the NVIC object when we create it
In the features category:
* v8.1M PXN extension
* VSCCLRM and CLRM insns
* VLDR/VSTR (sysreg) insns
* new M-profile fp sysregs: FPSCR_nzcvqc, FPCXT_S, FPCXT_NS
* update FPDSCR masking to allow new-in-v8.1M bits in that register
* v8.1M has a new REVIDR register
* v8.1M does not set HFSR.FORCED on vector table fetch failure
* v8.1M always clears R0-R3, R12, APSR, EPSR on exception entry
(the behaviour is tightened up compared to v8.0M)
* v8.1M has a new check on exception return which might trigger
a NOCP UsageFault
* v8.1M has new VLLDM and VLSTM encodings
* v8.1M's new CCR.TRD bit that enables an extra integrity check
when executing an SG instruction
* v8.1M "minimal RAS" (the architecturally minimum permitted
do-nothing implementation, essentially)
Already reviewed: patches 1-6, 8, 11, 12.
thanks
-- PMM
Peter Maydell (28):
hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
target/arm: Implement v8.1M PXN extension
target/arm: Don't clobber ID_PFR1.Security on M-profile cores
target/arm: Implement VSCCLRM insn
target/arm: Implement CLRM instruction
target/arm: Enforce M-profile VMRS/VMSR register restrictions
target/arm: Refactor M-profile VMSR/VMRS handling
target/arm: Move general-use constant expanders up in translate.c
target/arm: Implement VLDR/VSTR system register
target/arm: Implement M-profile FPSCR_nzcvqc
target/arm: Use new FPCR_NZCV_MASK constant
target/arm: Factor out preserve-fp-state from full_vfp_access_check()
target/arm: Implement FPCXT_S fp system register
target/arm: Implement FPCXT_NS fp system register
hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on
exception entry
target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch
failures
target/arm: Implement v8.1M REVIDR register
target/arm: Implement new v8.1M NOCP check for exception return
target/arm: Implement new v8.1M VLLDM and VLSTM encodings
hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN
hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
target/arm: Implement CCR_S.TRD behaviour for SG insns
hw/intc/armv7m_nvic: Fix "return from inactive handler" check
target/arm: Implement M-profile "minimal RAS implementation"
hw/intc/armv7m_nvic: Implement read/write for RAS register block
hw/arm/armv7m: Correct typo in QOM object name
target/arm: Implement Cortex-M55 model
include/hw/intc/armv7m_nvic.h | 2 +
target/arm/cpu.h | 46 +++
target/arm/m-nocp.decode | 10 +-
target/arm/t32.decode | 10 +-
target/arm/vfp.decode | 14 +
hw/arm/armv7m.c | 4 +-
hw/intc/armv7m_nvic.c | 257 +++++++++++---
target/arm/cpu.c | 5 +-
target/arm/cpu_tcg.c | 42 +++
target/arm/helper.c | 7 +-
target/arm/m_helper.c | 130 ++++++-
target/arm/translate.c | 105 ++++--
target/arm/translate-vfp.c.inc | 604 +++++++++++++++++++++++++++++++--
13 files changed, 1115 insertions(+), 121 deletions(-)
--
2.20.1
