On Sun, Jan 10, 2021 at 10:53 AM Alexey Baturo <baturo.ale...@gmail.com> wrote:
>
> From: Anatoly Parshintsev <kupokupokup...@gmail.com>
>
> Signed-off-by: Anatoly Parshintsev <kupokupokup...@gmail.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/riscv/cpu.h | 19 +++++++++++++++++++
> target/riscv/translate.c | 34 ++++++++++++++++++++++++++++++++--
> 2 files changed, 51 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 37ea7f7802..b3c63ca5ff 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -397,6 +397,7 @@ FIELD(TB_FLAGS, SEW, 5, 3)
> FIELD(TB_FLAGS, VILL, 8, 1)
> /* Is a Hypervisor instruction load/store allowed? */
> FIELD(TB_FLAGS, HLSX, 9, 1)
> +FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
Can you add a comment above this for what this is? PM could be lots of
different things.
>
> bool riscv_cpu_is_32bit(CPURISCVState *env);
>
> @@ -454,6 +455,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
> *env, target_ulong *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
> }
> }
> + if (riscv_has_ext(env, RVJ)) {
> + int priv = cpu_mmu_index(env, false);
> + bool pm_enabled = false;
> + switch (priv) {
> + case PRV_U:
> + pm_enabled = env->mmte & U_PM_ENABLE;
> + break;
> + case PRV_S:
> + pm_enabled = env->mmte & S_PM_ENABLE;
> + break;
> + case PRV_M:
> + pm_enabled = env->mmte & M_PM_ENABLE;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
> + }
> #endif
>
> *pflags = flags;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5da7330f33..980604935d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
> static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
> static TCGv load_res;
> static TCGv load_val;
> +/* globals for PM CSRs */
> +static TCGv pm_mask[4];
> +static TCGv pm_base[4];
>
> #include "exec/gen-icount.h"
>
> @@ -64,6 +67,10 @@ typedef struct DisasContext {
> uint16_t vlen;
> uint16_t mlen;
> bool vl_eq_vlmax;
> + /* PointerMasking extension */
> + bool pm_enabled;
> + TCGv pm_mask;
> + TCGv pm_base;
> } DisasContext;
>
> #ifdef TARGET_RISCV64
> @@ -103,13 +110,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> }
>
> /*
> - * Temp stub: generates address adjustment for PointerMasking
> + * Generates address adjustment for PointerMasking
> */
> static void gen_pm_adjust_address(DisasContext *s,
> TCGv_i64 dst,
> TCGv_i64 src)
> {
> - tcg_gen_mov_i64(dst, src);
> + if (!s->pm_enabled) {
> + /* Load unmodified address */
> + tcg_gen_mov_i64(dst, src);
> + } else {
> + tcg_gen_andc_i64(dst, src, s->pm_mask);
> + tcg_gen_or_i64(dst, dst, s->pm_base);
> + }
> }
>
> /*
> @@ -828,6 +841,10 @@ static void riscv_tr_init_disas_context(DisasContextBase
> *dcbase, CPUState *cs)
> ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
> ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
> + int priv = cpu_mmu_index(env, false);
Can you AND this with TB_FLAGS_PRIV_MMU_MASK?
Alistair
> + ctx->pm_mask = pm_mask[priv];
> + ctx->pm_base = pm_base[priv];
> }
>
> static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
> @@ -947,4 +964,17 @@ void riscv_translate_init(void)
> "load_res");
> load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
> "load_val");
> + /* Assign PM CSRs to tcg globals */
> + pm_mask[PRV_U] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask),
> "upmmask");
> + pm_base[PRV_U] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase),
> "upmbase");
> + pm_mask[PRV_S] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask),
> "spmmask");
> + pm_base[PRV_S] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase),
> "spmbase");
> + pm_mask[PRV_M] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask),
> "mpmmask");
> + pm_base[PRV_M] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase),
> "mpmbase");
> }
> --
> 2.20.1
>
>
