On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> This function was created to move the sync between cpu->cfg.ext_N bit
> changes to env->misa_ext* from the validation step to an ealier step,
> giving us a guarantee that we could use either cpu->cfg.ext_N or
> riscv_has_ext(env,N) in the validation.
>
> We don't have any cpu->cfg.ext_N left that has an existing MISA bit
> (cfg.ext_g will be handled shortly). The function is now a no-op, simply
> copying the existing values of misa_ext* back to misa_ext*.
>
> Remove it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 52 ----------------------------------------------
> 1 file changed, 52 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b40a55bc8d..3eb3b7dc59 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1081,50 +1081,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu,
> Error **errp)
> #endif
> }
>
> -static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
> -{
> - uint32_t ext = 0;
> -
> - if (riscv_has_ext(env, RVI)) {
> - ext |= RVI;
> - }
> - if (riscv_has_ext(env, RVE)) {
> - ext |= RVE;
> - }
> - if (riscv_has_ext(env, RVM)) {
> - ext |= RVM;
> - }
> - if (riscv_has_ext(env, RVA)) {
> - ext |= RVA;
> - }
> - if (riscv_has_ext(env, RVF)) {
> - ext |= RVF;
> - }
> - if (riscv_has_ext(env, RVD)) {
> - ext |= RVD;
> - }
> - if (riscv_has_ext(env, RVC)) {
> - ext |= RVC;
> - }
> - if (riscv_has_ext(env, RVS)) {
> - ext |= RVS;
> - }
> - if (riscv_has_ext(env, RVU)) {
> - ext |= RVU;
> - }
> - if (riscv_has_ext(env, RVH)) {
> - ext |= RVH;
> - }
> - if (riscv_has_ext(env, RVV)) {
> - ext |= RVV;
> - }
> - if (riscv_has_ext(env, RVJ)) {
> - ext |= RVJ;
> - }
> -
> - env->misa_ext = env->misa_ext_mask = ext;
> -}
> -
> static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> {
> if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
> @@ -1168,14 +1124,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> set_priv_version(env, priv_version);
> }
>
> - /*
> - * We can't be sure of whether we set defaults during cpu_init()
> - * or whether the user enabled/disabled some bits via cpu->cfg
> - * flags. Sync env->misa_ext with cpu->cfg now to allow us to
> - * use just env->misa_ext later.
> - */
> - riscv_cpu_sync_misa_cfg(env);
> -
> riscv_cpu_validate_misa_priv(env, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> --
> 2.39.2
>
>
