Re: gEDA-user: gEDA user with problems
Hi Carlos, [snip] >I had a little more time, so I tried with 20060906 debian package, and I >get autonumbering working both when placing and copying components. > >It's not a matter of versions. Something else is not working properly. > >Ales, it seems you were able to reproduce part of the bug. Can you track >it down? > Yes. Okay, if my memory serves me correctly, CVS HEAD works fine for renumbering components when copying, but the glist_dev branch does not. I need to verify this again (I got distracted the last time I was going down this path). -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Vendor FPGA tools (was Re: Re: Pointer to 3d CAD?)
ldoolitt-dhTElhTvxjT/[EMAIL PROTECTED] wrote: > I have added some odd features > over the past couple of years. Like the ability to automatically > create a .ucf file with timing goals in it based on the comments > in the top level Verilog module: > > module stacker( > input clk, // timespec 6.5 ns > input gate, > ... > > which is useful for keeping track of timing and cell usage for > each of the components of a design. I use attributes for this sort of thing: module stacker( (* PERIOD="6.5ns" *) input clk, ... xst understands this, as does Icarus Verilog. -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: no pins in JUMPER10
On 11/8/06, Giorgenes Gelatti <[EMAIL PROTECTED]> wrote: I've changed the refdes as you said and it worked. Thank you. You know, I`m new to electronics, geda and such. But it seems too tricky for me. I just wonder why are all these things necessary. I am not sure what you mean by "all these things". Your first problem occured because the gsch2pcb script places all of the components on top of each other. It would be nice if the script spaced the components out but you now know how to deal with that issue. Your second problem occured because you were not familiar with the reference designator syntax that PCB requires. If you follow the outline I posted you should be OK. You now should be able to proceed with your layout. Here are a couple of things to be careful of --- 1. Verify that the footprints you choose meet the manufacturer's package specification for the components you are using. Usually each component datasheet contains a recommended footprint. 2. Set the DRC rules to match the PCB vendor that you plan on using and run the DRC *frequently* as you are doing your board. It is much easier to fix the errors as you go than to end up with a huge list (which can be quite discouraging). 3. Always check the Gerber files prior to sending them to the PCB vendor. I use gerbv to do this. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bug or feature in recent versions of PCB?
> GTK Have you tried the lesstif one? I've never seen it do what you're seeing. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: no pins in JUMPER10
I've changed the refdes as you said and it worked. Thank you. You know, I`m new to electronics, geda and such. But it seems too tricky for me. I just wonder why are all these things necessary. 2006/11/8, John Luciani <[EMAIL PROTECTED]>: On 11/8/06, John Luciani <[EMAIL PROTECTED]> wrote: > > Substitute an integer value for This should be Substitute a cardinal number for (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bug or feature in recent versions of PCB?
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 > Lesstif or Gtk? GTK Best regards Tomaz -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.5 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFFUlHJsAlAlRhL9q8RApZ/AKCWX/ARO/rHMrkWLftwVfRkSok/DgCfWiWE OgEYFZV4Y3OKcPnA0uHMfUA= =R1Ot -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: bug or feature in recent versions of PCB?
On Wed, 08 Nov 2006 18:08:50 +0100, Tomaz Solc wrote: > Recent versions of PCB (20060822 and also CVS head) seem to have this > weird feature which I'm unable to figure out: > > Sometimes when I try to draw a line, the window automatically pans under > the cursor and the line is placed at some random location instead of the > point where I clicked. Same symptoms over here :-| PCB version 20060822, GTK GUI. ---<(kaimartin)>--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Polarized capacitor question
I was asked this question the other day and I did not have a good answer to it, and have not been able to find a good answer for it. So I figured I would see if anyone here knew of a good answer. All tantalum capacitor that I have ever seen marked the anode(+). On the other hand all electrolytic capacitors that I have seen marked the cathode(-). Is this an industry standard or is it done this way just because it has always been done this way? Thanks, Matthew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bug or feature in recent versions of PCB?
Lesstif or Gtk? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: bug or feature in recent versions of PCB?
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi everyone. Recent versions of PCB (20060822 and also CVS head) seem to have this weird feature which I'm unable to figure out: Sometimes when I try to draw a line, the window automatically pans under the cursor and the line is placed at some random location instead of the point where I clicked. In more detail, it goes like this: Press to select the line tool. Click left button to place the start of the line. Move mouse to the desired end of the line. Click left button. Window pans to some random direction for a moment and the line end is placed at a wrong location (usually right across some other line or element) This happens only in one out of ten cases and is extremely annoying. In fact it makes newer versions of PCB unusable for any serious work. I can't find any options that would turn this off and I can't understand how this feature is supposed to help me. I've checked the manual and FAQ and I can't find anything about this. Can anyone explain what is happening here? I am obviously missing something since I can't believe such a bug could stay in the code for so long. Best regards Tomaz Solc -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.5 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFFUg8isAlAlRhL9q8RAnAlAJ49P9M13w/wFPQFBjZxrWPe+uLM8gCeITNE 6Dsn3Rp1Qq7w5P/l+QhYseI= =K3s3 -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: Vendor FPGA tools (was Re: gEDA-user: Re: Pointer to 3d CAD?)
Dave -
On Wed, Nov 08, 2006 at 08:40:26AM -0500, Dave McGuire wrote:
> On Oct 31, 2006, at 1:40 AM, [EMAIL PROTECTED] wrote:
> >After [Xilinx XST is] installed, I too use the command-line-only
> >programs. With some scripting, they embed nicely in my Makefiles.
>
> I've about had it with the Xilinx GUI. Would you be willing to
> share your Makefiles?
Here's a Makefile snippet:
SYNTH = inch.v ad95xx_driver.v source.v freq_count.v trace.v rx_buffer.v
generic_fifo_dc_gray.v generic_dpram.v dds.v cordic.v
# test build, mostly a syntax check
inch: ${SYNTH} BUFG.v
iverilog -DTARGET_s3 -Wall $^ -o $@
# synthesize a bitfile
_xilinx/inch_s3.bit: ${SYNTH}
arch=s3 sh runme inch_s3 $^
where the real work happens in runme, which I will both attach
and post to http://recycle.lbl.gov/~ldoolitt/xilinx/runme
That script is somewhat organic, I have added some odd features
over the past couple of years. Like the ability to automatically
create a .ucf file with timing goals in it based on the comments
in the top level Verilog module:
module stacker(
input clk, // timespec 6.5 ns
input gate,
...
which is useful for keeping track of timing and cell usage for
each of the components of a design.
The other major features of the script are:
- immediate exit with failure if $XILINX is not set
- target chip determined by $arch input
- all 22 scratch and log files pushed into _xilinx directory
- exits with failure if timing constraints not met
One defect in the script is that it doesn't split the synthesis
and P&R steps, so changing the ucf file requires resynthesis.
I find most of the time is spent in the P&R, so my motivation
to split them is small.
I hope this helps. If more than two of us start using a script
like this, I'll post a web page to keep track of ideas and
script variants.
- Larry
# This script places all scratch files, and the resulting .bit file,
# in the _xilinx directory. Tested with XST 7.1i.
# Default architecture is s3
if [ -z "$arch" ]; then arch=s3; fi
if [ "$XILINX" = "" ]; then
echo "set up for Xilinx first" >&2
exit 1
fi
set -e
mkdir -p _xilinx
cd _xilinx
# DESIGN=stacker
DESIGN=$1
shift
PART_s3=xc3s1000-ft256-4
CLOCK_PIN=P125
#PART_s3=xc3s400-ft256-4
#CLOCK_PIN=T9
eval PART=\$PART_$arch
cat <$DESIGN.xst
set -tmpdir .
run
-ifn $DESIGN.prj
-ifmt Verilog
-ofn $DESIGN
-ofmt NGC
-p $PART
-top $DESIGN
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator _
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-vlgincdir
-fsm_extract YES -fsm_encoding Auto
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-mux_extract YES
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-resource_sharing YES
-iobuf YES
-max_fanout 100
-bufg 4
-register_duplication YES
-equivalent_register_removal YES
-register_balancing No
-slice_packing YES
-iob auto
-slice_utilization_ratio_maxmargin 5
EOT
BOMB=""
toplevel=$1
echo "\`define TARGET_$arch 1" >$DESIGN.prj
for s; do
test -r ../$s || BOMB="$BOMB $s"
echo "\`include \"../$s\""
done >>$DESIGN.prj
# sed -e 's/^/\`include "..\//' -e 's/$/"/' ../$DESIGN.set
echo "\`include \"$XILINX/verilog/src/iSE/unisim_comp.v\"" >>$DESIGN.prj
# If the ${DESIGN}.ucf file doesn't exist, create one based on
# comments in the top level Verilog.
ucf=../${DESIGN}.ucf
if [ ! -r $ucf ]; then
ucf=${DESIGN}.ucf
perl -ne 'if (/(\w+),\s+\/\/ timespec\s+(.+)/) {print "NET \"$1\"
LOC=\"'${CLOCK_PIN}'\";\nNET \"$1\" TNM_NET = \"CLK_1\";\nTIMESPEC \"TS_CLK_1\"
= PERIOD \"CLK_1\" $2 HIGH 50%;\n"}' ../$toplevel >$ucf
fi
test -r $ucf || BOMB="$BOMB $ucf"
if [ -n "$BOMB" ]; then
echo "missing files:$BOMB" >&2
exit 1
fi
# exit
# demote USB_IFCLK error to a WARNING
export XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING=1
xst -ifn $DESIGN.xst -ofn $DESIGN.syr
ngdbuild -dd . -uc $ucf -p $PART $DESIGN.ngc $DESIGN.ngd
# was "-cm area"
map -p $PART -timing -cm speed -ol high -pr b -k 4 -c 100 -tx off -o
${DESIGN}_map.ncd $DESIGN.ngd $DESIGN.pcf
par -w -ol high -t 1 ${DESIGN}_map.ncd $DESIGN.ncd $DESIGN.pcf
# optional (timing report)
trce -e 3 -l 3 $DESIGN.ncd -o $DESIGN.twr $DESIGN.pcf
if grep "All constraints were met\." $DESIGN.par &&
grep "All signals are completely routed\." $DESIGN.par; then
echo "PAR success confirmed for $DESIGN"
else
echo "PAR apparently failed for $DESIGN"
exit 1
fi
bitgen -w -g StartUpClk:JtagClk $DESIGN.ncd
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Re: Vendor FPGA tools (was Re: gEDA-user: Re: Pointer to 3d CAD?)
On Oct 31, 2006, at 1:40 AM, [EMAIL PROTECTED] wrote: I've tried it, but got turned off in utter disgust when I saw that the thing is packaged in encrypted (!) ZIPs specifically to make it impossible to bypass their stinky GUI installer. The installer is indeed the worst part of the Xilinx setup. After it's installed, I too use the command-line-only programs. With some scripting, they embed nicely in my Makefiles. I've about had it with the Xilinx GUI. Would you be willing to share your Makefiles? -Dave -- Dave McGuire Cape Coral, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: about DJ
Here in Brazil a public university offers an online C language course. Of
course, they recommend to use DJGPP. I tryed this course in 99, was the first
time I used DJGPP.
If someone is curious, here is the link to the course, in portuguese only:
http://www.ead.eee.ufmg.br/cursos/C/c.html
Em Qua 08 Nov 2006 07:54, Peter Baxendale escreveu:
> We used to use DJGPP in our C programming classes. Now the students use
> pcb in their ECAD classes. Wonder what he will turn his hand to next...
>
> On Tue, 2006-11-07 at 18:11 -0500, Dave McGuire wrote:
> > On Nov 7, 2006, at 6:05 PM, Paul Bunyk wrote:
> > > Brings back fond memories of compiling my code with PharLap, then with
> > > djgpp and getting like 30% better performance with the latter! :-)
> > > Moving to GNU toolchain completely right after that and to Linux
> > > ("Hey, it actually *comes* will all the tools!") around kernel version
> > > 0.93. First Slackware base install living on 16MB partition on my PC
> > > with /usr/ NFS-mounted from Interactive UNIX server... 1991-1992, I
> > > think...
> > >
> > > Thanks, DJ!
> >
> >I echo this "thanks" to DJ. I was working on a 386DX/20 running
> > DOS, and had gotten about as far as I could with Turbo C. It was a
> > good system, but it was like pulling teeth when compared to
> > developing on [what at the time was my] modern system, a Sun 4/110
> > running SunOS 4.1. I finally found djgpp and it was like a breath of
> > fresh air.
> >
> >-Dave
>
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Re: gEDA-user: no pins in JUMPER10
On 11/8/06, John Luciani <[EMAIL PROTECTED]> wrote: Substitute an integer value for This should be Substitute a cardinal number for (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: no pins in JUMPER10
On 11/8/06, Giorgenes Gelatti <[EMAIL PROTECTED]> wrote: there is goes.. thank you I changed the refdes value of "pinbar" to "J1" and the value of "serial" to "J2" and the netlist loads. Below are the refdes conventions that I use (that I have seen on *many* schematics). I may have missed a few since this is BC (before Cappuccino). (* jcl *) Substitute an integer value for value component type - R Resistor L Inductor C Capacitor B Battery J Connector P Connector (usually plugs that mate with J) K Relay S Switch T Transformer D Diode Q Transistor U IC X Crystal -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: no pins in JUMPER10
there is goes.. thank you 2006/11/7, John Luciani <[EMAIL PROTECTED]>: On 11/7/06, Giorgenes Gelatti <[EMAIL PROTECTED]> wrote: > sure. > And I did the "disperse all elements" too. > > 2006/11/7, Dan McMahill <[EMAIL PROTECTED]>: > > Giorgenes Gelatti wrote: > > > > > > 2006/11/6, John Luciani <[EMAIL PROTECTED]>: > > > > > >> On 11/6/06, Giorgenes Gelatti <[EMAIL PROTECTED]> wrote: > > >> > I got a simpler circuit that is not working. > > >> > I have snap turned on, but can't see a way of making it works :( > > >> > > > >> > > >> What specifically isn't working? > > >> > > >> the netlist produced --- > > >> > > >> unnamed_net9serial-2 pinbar-9 > > >> unnamed_net8serial-1 pinbar-10 > > >> unnamed_net7serial-4 pinbar-7 > > >> unnamed_net6serial-6 pinbar-5 > > >> unnamed_net5serial-8 pinbar-3 > > >> unnamed_net4serial-3 pinbar-8 > > >> unnamed_net3serial-5 pinbar-6 > > >> unnamed_net2serial-7 pinbar-4 > > >> unnamed_net1serial-9 pinbar-2 > > >> > > >> which is all of the connections. I do not have the same set of > > >> footprints so I > > >> did not check out a PCB file. > > >> > > >> (* jcl *) > > > > > In pcb the components are not connected. :-( Attach the PCB file and the netlist file. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user db2bar.net Description: Binary data db2bar.pcb Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: about DJ
We used to use DJGPP in our C programming classes. Now the students use
pcb in their ECAD classes. Wonder what he will turn his hand to next...
On Tue, 2006-11-07 at 18:11 -0500, Dave McGuire wrote:
> On Nov 7, 2006, at 6:05 PM, Paul Bunyk wrote:
> > Brings back fond memories of compiling my code with PharLap, then with
> > djgpp and getting like 30% better performance with the latter! :-)
> > Moving to GNU toolchain completely right after that and to Linux
> > ("Hey, it actually *comes* will all the tools!") around kernel version
> > 0.93. First Slackware base install living on 16MB partition on my PC
> > with /usr/ NFS-mounted from Interactive UNIX server... 1991-1992, I
> > think...
> >
> > Thanks, DJ!
>
>I echo this "thanks" to DJ. I was working on a 386DX/20 running
> DOS, and had gotten about as far as I could with Turbo C. It was a
> good system, but it was like pulling teeth when compared to
> developing on [what at the time was my] modern system, a Sun 4/110
> running SunOS 4.1. I finally found djgpp and it was like a breath of
> fresh air.
>
>-Dave
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