[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: add Makefile magic for testing headers are self-contained (rev4)
== Series Details == Series: drm/i915: add Makefile magic for testing headers are self-contained (rev4) URL : https://patchwork.freedesktop.org/series/58938/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5863_full -> Patchwork_12674_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12674_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12674_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12674_full: ### IGT changes ### Possible regressions * igt@gem_eio@reset-stress: - shard-skl: PASS -> DMESG-WARN Known issues Here are the changes found in Patchwork_12674_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ppgtt@blt-vs-render-ctxn: - shard-iclb: PASS -> INCOMPLETE [fdo#109801] * igt@gem_userptr_blits@process-exit-gtt: - shard-glk: NOTRUN -> SKIP [fdo#109271] +44 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +1 * igt@kms_busy@extended-pageflip-hang-oldfb-render-f: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-apl: PASS -> DMESG-WARN [fdo#110222] * igt@kms_chamelium@hdmi-crc-fast: - shard-skl: NOTRUN -> SKIP [fdo#109271] +83 * igt@kms_cursor_crc@cursor-256x256-random: - shard-glk: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-iclb: PASS -> FAIL [fdo#103355] +1 * igt@kms_flip@2x-modeset-vs-vblank-race: - shard-glk: PASS -> FAIL [fdo#103060] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-iclb: PASS -> FAIL [fdo#105363] - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt: - shard-skl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-iclb: PASS -> FAIL [fdo#109247] +18 * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-apl: NOTRUN -> SKIP [fdo#109271] +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10 * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_psr@primary_mmap_gtt: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] Possible fixes * igt@gem_tiled_pread_pwrite: - shard-iclb: TIMEOUT [fdo#109673] -> PASS * igt@i915_pm_rpm@system-suspend-devices: - shard-skl: INCOMPLETE [fdo#107807] -> PASS * igt@kms_cursor_crc@cursor-128x42-offscreen: - shard-skl: FAIL [fdo#103232] -> PASS * igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge: - shard-snb: SKIP [fdo#109271] / [fdo#109278] -> PASS * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: FAIL [fdo#104873] -> PASS * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: FAIL [fdo#102887] / [fdo#105363] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: - shard-iclb: FAIL [fdo#103167] -> PASS +14 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-iclb: FAIL [fdo#109247] -> PASS +21 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS +3 * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: FAIL [fdo#108145] -> PASS * igt@kms_psr2_su@page_flip: - shard-iclb: SKIP [fdo#109642] -> PASS * igt@kms_psr@cursor_mmap_gtt: - shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS +4 * igt@kms_psr@psr2_cursor_render: - shard-iclb: SKIP [fdo#109441] -> PASS +1 * igt@kms_setmode@basic: - shard-kbl: FAIL [fdo#99912] -> PASS Warnings * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-skl: FAIL [fdo#103191] / [fdo#103232] -> INCOMP
Re: [Intel-gfx] [PATCH] drm/i915/dp: On link train failure on eDP, retry with max params first
Hi Manasi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.1-rc3 next-20190403]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Manasi-Navare/drm-i915-dp-On-link-train-failure-on-eDP-retry-with-max-params-first/20190404-115622
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x006-201913 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/intel_dp.c: In function 'intel_dp_uses_max_link_params':
drivers/gpu/drm/i915/intel_dp.c:466:50: error: parameter name omitted
static bool intel_dp_uses_max_link_params(struct intel_dp*,
^~~~
drivers/gpu/drm/i915/intel_dp.c:470:22: error: 'intel_dp' undeclared (first
use in this function)
return link_rate == intel_dp->max_link_rate &&
^~~~
drivers/gpu/drm/i915/intel_dp.c:470:22: note: each undeclared identifier is
reported only once for each function it appears in
drivers/gpu/drm/i915/intel_dp.c: In function
'intel_dp_get_link_train_fallback_values':
>> drivers/gpu/drm/i915/intel_dp.c:484:7: error: the address of
>> 'intel_dp_uses_max_link_params' will always evaluate as 'true'
>> [-Werror=address]
if (!intel_dp_uses_max_link_params) {
^
drivers/gpu/drm/i915/intel_dp.c:486:4: error: implicit declaration of
function 'DRM_DEBUGS_KMS'; did you mean 'DRM_DEBUG_KMS'?
[-Werror=implicit-function-declaration]
DRM_DEBUGS_KMS("Retrying Link training for eDP with max link
parameters\n");
^~
DRM_DEBUG_KMS
cc1: all warnings being treated as errors
vim +484 drivers/gpu/drm/i915/intel_dp.c
465
> 466 static bool intel_dp_uses_max_link_params(struct intel_dp*,
467int link_rate,
468u8 lane_count)
469 {
470 return link_rate == intel_dp->max_link_rate &&
471 lane_count == intel_dp->max_link_lane_count;
472 }
473
474 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
475 int link_rate, u8
lane_count)
476 {
477 int index;
478
479 index = intel_dp_rate_index(intel_dp->common_rates,
480 intel_dp->num_common_rates,
481 link_rate);
482
483 if (intel_dp_is_edp(intel_dp)) {
> 484 if (!intel_dp_uses_max_link_params) {
485 intel_dp->retry_with_max_link_params = true;
486 DRM_DEBUGS_KMS("Retrying Link training for eDP
with max link parameters\n");
487 return 0;
488 } else if
(!intel_dp_can_link_train_fallback_for_edp(intel_dp,
489
intel_dp->common_rates[index - 1],
490
lane_count)) {
491 DRM_DEBUG_KMS("Retrying Link training for eDP
with same parameters\n");
492 return 0;
493 }
494 }
495 if (index > 0) {
496 intel_dp->max_link_rate = intel_dp->common_rates[index
- 1];
497 intel_dp->max_link_lane_count = lane_count;
498 } else if (lane_count > 1) {
499 intel_dp->max_link_rate =
intel_dp_max_common_rate(intel_dp);
500 intel_dp->max_link_lane_count = lane_count >> 1;
501 } else {
502 DRM_ERROR("Link Training Unsuccessful\n");
503 return -1;
504 }
505
506 return 0;
507 }
508
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Re: [Intel-gfx] [PATCH] drm/i915/dp: On link train failure on eDP, retry with max params first
Hi Manasi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.1-rc3 next-20190403]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Manasi-Navare/drm-i915-dp-On-link-train-failure-on-eDP-retry-with-max-params-first/20190404-115622
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x013-201913 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All error/warnings (new ones prefixed by >>):
drivers/gpu//drm/i915/intel_dp.c: In function
'intel_dp_uses_max_link_params':
>> drivers/gpu//drm/i915/intel_dp.c:466:50: error: parameter name omitted
static bool intel_dp_uses_max_link_params(struct intel_dp*,
^~~~
>> drivers/gpu//drm/i915/intel_dp.c:470:22: error: 'intel_dp' undeclared (first
>> use in this function)
return link_rate == intel_dp->max_link_rate &&
^~~~
drivers/gpu//drm/i915/intel_dp.c:470:22: note: each undeclared identifier is
reported only once for each function it appears in
drivers/gpu//drm/i915/intel_dp.c: In function
'intel_dp_get_link_train_fallback_values':
>> drivers/gpu//drm/i915/intel_dp.c:484:7: warning: the address of
>> 'intel_dp_uses_max_link_params' will always evaluate as 'true' [-Waddress]
if (!intel_dp_uses_max_link_params) {
^
>> drivers/gpu//drm/i915/intel_dp.c:486:4: error: implicit declaration of
>> function 'DRM_DEBUGS_KMS'; did you mean 'DRM_DEBUG_KMS'?
>> [-Werror=implicit-function-declaration]
DRM_DEBUGS_KMS("Retrying Link training for eDP with max link
parameters\n");
^~
DRM_DEBUG_KMS
cc1: some warnings being treated as errors
vim +/intel_dp +470 drivers/gpu//drm/i915/intel_dp.c
465
> 466 static bool intel_dp_uses_max_link_params(struct intel_dp*,
467int link_rate,
468u8 lane_count)
469 {
> 470 return link_rate == intel_dp->max_link_rate &&
471 lane_count == intel_dp->max_link_lane_count;
472 }
473
474 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
475 int link_rate, u8
lane_count)
476 {
477 int index;
478
479 index = intel_dp_rate_index(intel_dp->common_rates,
480 intel_dp->num_common_rates,
481 link_rate);
482
483 if (intel_dp_is_edp(intel_dp)) {
> 484 if (!intel_dp_uses_max_link_params) {
485 intel_dp->retry_with_max_link_params = true;
> 486 DRM_DEBUGS_KMS("Retrying Link training for eDP
> with max link parameters\n");
487 return 0;
488 } else if
(!intel_dp_can_link_train_fallback_for_edp(intel_dp,
489
intel_dp->common_rates[index - 1],
490
lane_count)) {
491 DRM_DEBUG_KMS("Retrying Link training for eDP
with same parameters\n");
492 return 0;
493 }
494 }
495 if (index > 0) {
496 intel_dp->max_link_rate = intel_dp->common_rates[index
- 1];
497 intel_dp->max_link_lane_count = lane_count;
498 } else if (lane_count > 1) {
499 intel_dp->max_link_rate =
intel_dp_max_common_rate(intel_dp);
500 intel_dp->max_link_lane_count = lane_count >> 1;
501 } else {
502 DRM_ERROR("Link Training Unsuccessful\n");
503 return -1;
504 }
505
506 return 0;
507 }
508
---
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Re: [Intel-gfx] [PULL] gvt-fixes
On Thu, Apr 04, 2019 at 08:32:06AM +0800, Zhenyu Wang wrote:
> On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> > On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> > >
> > > Hi,
> > >
> > > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > > vGPU display plane size calculation, shadow mm pin count,
> > > error recovery path for workload create and one kerneldoc
> > > fix which I missed to include before.
> >
> > dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size"):
> > Fixes: SHA1 needs at least 12 digits:
> > dim: e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
> > dim: ERROR: issues in commits detected, aborting
> >
> > Is it something you could fix on your side without having
> > to by-pass dim this time?
> >
>
> Sorry about that, looks people still doesn't generate Fixes tag
> properly.
dim has a great helper for all developers to generate Fixes tags.
dim fixes
Besides the right tag it will also add right cc stable and other
cc folks.
We should advertise it more ;)
> I'll fix that and resend.
I pulled the new one. Thanks for that.
>
> --
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>
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: On link train failure on eDP, retry with max params first
== Series Details ==
Series: drm/i915/dp: On link train failure on eDP, retry with max params first
URL : https://patchwork.freedesktop.org/series/58975/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_dp.o
drivers/gpu/drm/i915/intel_dp.c: In function ‘intel_dp_uses_max_link_params’:
drivers/gpu/drm/i915/intel_dp.c:466:50: error: parameter name omitted
static bool intel_dp_uses_max_link_params(struct intel_dp*,
^~~~
drivers/gpu/drm/i915/intel_dp.c:470:22: error: ‘intel_dp’ undeclared (first use
in this function)
return link_rate == intel_dp->max_link_rate &&
^~~~
drivers/gpu/drm/i915/intel_dp.c:470:22: note: each undeclared identifier is
reported only once for each function it appears in
drivers/gpu/drm/i915/intel_dp.c: In function
‘intel_dp_get_link_train_fallback_values’:
drivers/gpu/drm/i915/intel_dp.c:484:7: error: the address of
‘intel_dp_uses_max_link_params’ will always evaluate as ‘true’ [-Werror=address]
if (!intel_dp_uses_max_link_params) {
^
drivers/gpu/drm/i915/intel_dp.c:486:4: error: implicit declaration of function
‘DRM_DEBUGS_KMS’; did you mean ‘DRM_DEBUG_KMS’?
[-Werror=implicit-function-declaration]
DRM_DEBUGS_KMS("Retrying Link training for eDP with max link parameters\n");
^~
DRM_DEBUG_KMS
cc1: all warnings being treated as errors
scripts/Makefile.build:275: recipe for target 'drivers/gpu/drm/i915/intel_dp.o'
failed
make[4]: *** [drivers/gpu/drm/i915/intel_dp.o] Error 1
scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:486: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1051: recipe for target 'drivers' failed
make: *** [drivers] Error 2
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Re: [Intel-gfx] [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment
On Wed, Apr 03, 2019 at 05:39:40PM -0700, Runyan, Arthur J wrote: > I update the Bspec as general programming. SRD_CTL TP2 TP3 Select - "This > bit impacts PSR2. Clear it before enabling PSR2 and do not set it while PSR2 > is enabled." > I haven't seen the hardware bug report come through yet to establish the wa > number. Thanks Reviewed-by: Rodrigo Vivi > > > -Original Message- > > From: Vivi, Rodrigo > > Sent: Wednesday, 3 April, 2019 5:22 PM > > To: Souza, Jose ; Runyan, Arthur J > > > > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > > > > Subject: Re: [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround > > comment > > > > On Wed, Apr 03, 2019 at 04:35:33PM -0700, José Roberto de Souza wrote: > > > Turn out it is not a DMC bug it is actually a HW one, so this > > > workaround will be needed for current gens, lets update the comment > > > and remove the FIXME. > > > > Do we have a Wa #number for this? p[art of workaround page > > or just part of programming sequence? > > > > > > > > BSpec: 7723 > > > Cc: Dhinakaran Pandiyan > > > Cc: Rodrigo Vivi > > > Signed-off-by: José Roberto de Souza > > > --- > > > drivers/gpu/drm/i915/intel_psr.c | 6 ++ > > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > > index ec874d802d48..c80bb3003a7d 100644 > > > --- a/drivers/gpu/drm/i915/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > > @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > > > /* > > > - * FIXME: There is probably a issue in DMC > > firmwares(icl_dmc_ver1_07.bin > > > - * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after > > > - * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now > > > - * lets workaround the issue by cleaning PSR_CTL before enable PSR2. > > > + * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > > > + * recommending keep this bit unset while PSR2 is enabled. > > >*/ > > > I915_WRITE(EDP_PSR_CTL, 0); > > > > > > -- > > > 2.21.0 > > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-fixes
On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> >
> > Hi,
> >
> > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > vGPU display plane size calculation, shadow mm pin count,
> > error recovery path for workload create and one kerneldoc
> > fix which I missed to include before.
>
> dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size"):
> Fixes: SHA1 needs at least 12 digits:
> dim: e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
> dim: ERROR: issues in commits detected, aborting
>
> Is it something you could fix on your side without having
> to by-pass dim this time?
>
Please re-pull this one.
Thanks
--
The following changes since commit 26cdaac4793c49357d2c731f2190632cefb7efb1:
drm/i915/icl: Fix VEBOX mismatch BUG_ON() (2019-03-28 15:36:40 +0200)
are available in the Git repository at:
https://github.com/intel/gvt-linux.git tags/gvt-fixes-2019-04-04
for you to fetch changes up to cf9ed66671ec5f6cacc7b6efbad9d7c9e5e31776:
drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug (2019-04-04
08:45:45 +0800)
gvt-fixes-2019-04-04
- Fix shadow mm pin count (Yan)
- Fix cmd parser error path recover (Yan)
- Fix vGPU display plane size calculation (Xiong)
- Fix kerneldoc (Chris)
Chris Wilson (1):
drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug
Xiong Zhang (1):
drm/i915/gvt: Correct the calculation of plane size
Yan Zhao (2):
drm/i915/gvt: do not deliver a workload if its creation fails
drm/i915/gvt: do not let pin count of shadow mm go negative
drivers/gpu/drm/i915/gvt/display.c | 2 +-
drivers/gpu/drm/i915/gvt/dmabuf.c| 8 ++--
drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 5 +++--
4 files changed, 7 insertions(+), 10 deletions(-)
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Re: [Intel-gfx] [PULL] gvt-fixes
On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> >
> > Hi,
> >
> > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > vGPU display plane size calculation, shadow mm pin count,
> > error recovery path for workload create and one kerneldoc
> > fix which I missed to include before.
>
> dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size"):
> Fixes: SHA1 needs at least 12 digits:
> dim: e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
> dim: ERROR: issues in commits detected, aborting
>
> Is it something you could fix on your side without having
> to by-pass dim this time?
>
Sorry about that, looks people still doesn't generate Fixes tag
properly. I'll fix that and resend.
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Re: [Intel-gfx] [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment
I update the Bspec as general programming. SRD_CTL TP2 TP3 Select - "This bit impacts PSR2. Clear it before enabling PSR2 and do not set it while PSR2 is enabled." I haven't seen the hardware bug report come through yet to establish the wa number. > -Original Message- > From: Vivi, Rodrigo > Sent: Wednesday, 3 April, 2019 5:22 PM > To: Souza, Jose ; Runyan, Arthur J > > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > > Subject: Re: [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround > comment > > On Wed, Apr 03, 2019 at 04:35:33PM -0700, José Roberto de Souza wrote: > > Turn out it is not a DMC bug it is actually a HW one, so this > > workaround will be needed for current gens, lets update the comment > > and remove the FIXME. > > Do we have a Wa #number for this? p[art of workaround page > or just part of programming sequence? > > > > > BSpec: 7723 > > Cc: Dhinakaran Pandiyan > > Cc: Rodrigo Vivi > > Signed-off-by: José Roberto de Souza > > --- > > drivers/gpu/drm/i915/intel_psr.c | 6 ++ > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > > index ec874d802d48..c80bb3003a7d 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > /* > > -* FIXME: There is probably a issue in DMC > firmwares(icl_dmc_ver1_07.bin > > -* and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after > > -* exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now > > -* lets workaround the issue by cleaning PSR_CTL before enable PSR2. > > +* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > > +* recommending keep this bit unset while PSR2 is enabled. > > */ > > I915_WRITE(EDP_PSR_CTL, 0); > > > > -- > > 2.21.0 > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dp: On link train failure on eDP, retry with max params first
Certain eDP panels fail to link train with optimized settings for
link rate and lane count and need the max link parameters to be used
for link training to pass.
So in on link training failure for eDP, retry the link training
with max link parameters first since this tends to fix link
failures on most eDP 1.4 panels
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Albert Astals Cid
Cc: Emanuele Panigati
Cc: Ralgor
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 36
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 72c49070ed14..d65d1a9338d6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -463,6 +463,14 @@ static bool
intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
return true;
}
+static bool intel_dp_uses_max_link_params(struct intel_dp*,
+ int link_rate,
+ u8 lane_count)
+{
+ return link_rate == intel_dp->max_link_rate &&
+ lane_count == intel_dp->max_link_lane_count;
+}
+
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
int link_rate, u8 lane_count)
{
@@ -471,24 +479,23 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
index = intel_dp_rate_index(intel_dp->common_rates,
intel_dp->num_common_rates,
link_rate);
- if (index > 0) {
- if (intel_dp_is_edp(intel_dp) &&
- !intel_dp_can_link_train_fallback_for_edp(intel_dp,
-
intel_dp->common_rates[index - 1],
- lane_count)) {
+
+ if (intel_dp_is_edp(intel_dp)) {
+ if (!intel_dp_uses_max_link_params) {
+ intel_dp->retry_with_max_link_params = true;
+ DRM_DEBUGS_KMS("Retrying Link training for eDP with max
link parameters\n");
+ return 0;
+ } else if (!intel_dp_can_link_train_fallback_for_edp(intel_dp,
+
intel_dp->common_rates[index - 1],
+
lane_count)) {
DRM_DEBUG_KMS("Retrying Link training for eDP with same
parameters\n");
return 0;
}
+ }
+ if (index > 0) {
intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
intel_dp->max_link_lane_count = lane_count;
} else if (lane_count > 1) {
- if (intel_dp_is_edp(intel_dp) &&
- !intel_dp_can_link_train_fallback_for_edp(intel_dp,
-
intel_dp_max_common_rate(intel_dp),
- lane_count >> 1))
{
- DRM_DEBUG_KMS("Retrying Link training for eDP with same
parameters\n");
- return 0;
- }
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
intel_dp->max_link_lane_count = lane_count >> 1;
} else {
@@ -2028,7 +2035,8 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
limits.min_bpp = 6 * 3;
limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
- if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
+ if ((intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) ||
+ intel_dp->retry_with_max_link_params) {
/*
* Use the maximum clock and number of lanes the eDP panel
* advertizes being capable of. The eDP 1.3 and earlier panels
@@ -5432,6 +5440,8 @@ intel_dp_detect(struct drm_connector *connector,
/* Initial max link rate */
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
+ intel_dp->retry_with_max_link_params = false;
+
intel_dp->reset_link_params = false;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f8c7b291fdc3..c3cf702c1cba 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1327,6 +1327,9 @@ struct intel_dp {
/* Display stream compression testing */
bool force_dsc_en;
+
+ /* Some panels need max link params for link training */
+ bool retry_with_max_link_params;
};
enum lspcon_vendor {
--
2.19.1
___
Inte
Re: [Intel-gfx] [PATCH 6/7] drm/i915/psr: Remove partial PSR support on multiple transcoders
On Wed, Apr 03, 2019 at 04:35:38PM -0700, José Roberto de Souza wrote:
> PSR is only supported in eDP transcoder and there is only one
> instance of it, so lets drop all of this code.
Is this sentence true? I mean, in the way it is written it
seems like HW doesn't actually support it...
Or should we re-phrase for we are not really enabling support
for other transcoders than eDP and we do not have plans to do
it so soon so let's clean the code...
or something like that?
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 17 +---
> drivers/gpu/drm/i915/intel_psr.c | 147 ---
> 2 files changed, 42 insertions(+), 122 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c59cfa83dbaf..18e2991b376d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4241,13 +4241,9 @@ enum {
> /* Bspec claims those aren't shifted but stay at 0x64800 */
> #define EDP_PSR_IMR _MMIO(0x64834)
> #define EDP_PSR_IIR _MMIO(0x64838)
> -#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
> -#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
> -#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
> -#define EDP_PSR_TRANSCODER_C_SHIFT 24
> -#define EDP_PSR_TRANSCODER_B_SHIFT 16
> -#define EDP_PSR_TRANSCODER_A_SHIFT 8
> -#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
> +#define EDP_PSR_ERROR (1 << 2)
> +#define EDP_PSR_POST_EXIT (1 << 1)
> +#define EDP_PSR_PRE_ENTRY (1 << 0)
>
> #define EDP_PSR_AUX_CTL
> _MMIO(dev_priv->psr_mmio_base + 0x10)
> #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
> @@ -4312,12 +4308,7 @@ enum {
> #define EDP_PSR2_IDLE_FRAME_MASK 0xf
> #define EDP_PSR2_IDLE_FRAME_SHIFT 0
>
> -#define _PSR_EVENT_TRANS_A 0x60848
> -#define _PSR_EVENT_TRANS_B 0x61848
> -#define _PSR_EVENT_TRANS_C 0x62848
> -#define _PSR_EVENT_TRANS_D 0x63848
> -#define _PSR_EVENT_TRANS_EDP 0x6F848
> -#define PSR_EVENT(trans) _MMIO_TRANS2(trans,
> _PSR_EVENT_TRANS_A)
> +#define PSR_EVENT_MMIO(0x6F848)
> #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
> #define PSR_EVENT_PSR2_DISABLED (1 << 16)
> #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN(1 << 15)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index bb97c1657493..b984e005b72e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -84,46 +84,12 @@ static bool intel_psr2_enabled(struct drm_i915_private
> *dev_priv,
> }
> }
>
> -static int edp_psr_shift(enum transcoder cpu_transcoder)
> -{
> - switch (cpu_transcoder) {
> - case TRANSCODER_A:
> - return EDP_PSR_TRANSCODER_A_SHIFT;
> - case TRANSCODER_B:
> - return EDP_PSR_TRANSCODER_B_SHIFT;
> - case TRANSCODER_C:
> - return EDP_PSR_TRANSCODER_C_SHIFT;
> - default:
> - MISSING_CASE(cpu_transcoder);
> - /* fallthrough */
> - case TRANSCODER_EDP:
> - return EDP_PSR_TRANSCODER_EDP_SHIFT;
> - }
> -}
> -
> void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
> {
> - u32 debug_mask, mask;
> - enum transcoder cpu_transcoder;
> - u32 transcoders = BIT(TRANSCODER_EDP);
> -
> - if (INTEL_GEN(dev_priv) >= 8)
> - transcoders |= BIT(TRANSCODER_A) |
> -BIT(TRANSCODER_B) |
> -BIT(TRANSCODER_C);
> -
> - debug_mask = 0;
> - mask = 0;
> - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> - int shift = edp_psr_shift(cpu_transcoder);
> -
> - mask |= EDP_PSR_ERROR(shift);
> - debug_mask |= EDP_PSR_POST_EXIT(shift) |
> - EDP_PSR_PRE_ENTRY(shift);
> - }
> + u32 mask = EDP_PSR_ERROR;
>
> if (debug & I915_PSR_DEBUG_IRQ)
> - mask |= debug_mask;
> + mask |= EDP_PSR_POST_EXIT | EDP_PSR_PRE_ENTRY;
>
> I915_WRITE(EDP_PSR_IMR, ~mask);
> }
> @@ -167,62 +133,47 @@ static void psr_event_print(u32 val, bool psr2_enabled)
>
> void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> {
> - u32 transcoders = BIT(TRANSCODER_EDP);
> - enum transcoder cpu_transcoder;
> - ktime_t time_ns = ktime_get();
> - u32 mask = 0;
> + ktime_t time_ns = ktime_get();
>
> - if (INTEL_GEN(dev_priv) >= 8)
> - transcoders |= BIT(TRANSCODER_A) |
> -BIT(TRANSCODER_
Re: [Intel-gfx] [PATCH 4/7] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
On Wed, Apr 03, 2019 at 04:35:36PM -0700, José Roberto de Souza wrote:
> This interlaced restriction applies to all gens, not only to Haswell.
I believe this came from VLV times and I doubt we would be
impacted by it ever, but better to protect just in case:
Reviewed-by: Rodrigo Vivi
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index a84da931c3be..bb97c1657493 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -627,8 +627,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> return;
> }
>
> - if (IS_HASWELL(dev_priv) &&
> - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> return;
> }
> --
> 2.21.0
>
___
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Re: [Intel-gfx] [PATCH 3/7] drm/i915/psr: Initialize PSR mutex even when sink is not reliable
On Wed, Apr 03, 2019 at 04:35:35PM -0700, José Roberto de Souza wrote:
> Even when driver is reloaded and hits this scenario the PSR mutex
> should be initialized, otherwise reading PSR debugfs status will
> execute mutex_lock() over a mutex that was not initialized.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index c80bb3003a7d..a84da931c3be 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -1227,7 +1227,6 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> if (val) {
> DRM_DEBUG_KMS("PSR interruption error set\n");
> dev_priv->psr.sink_not_reliable = true;
> - return;
There are other returns above and if debugfs hits this case maybe it
is worth to move the mutex initialization up instead?
> }
>
> /* Set link_standby x link_off defaults */
> --
> 2.21.0
>
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Re: [Intel-gfx] [PATCH 2/7] drm/i915: Remove unused VLV/CHV PSR registers
On Wed, Apr 03, 2019 at 04:35:34PM -0700, José Roberto de Souza wrote:
> PSR support for VLV and CHV was dropped in commit ce3508fd2a77
> ("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep
> this registers around.
o.O
Reviewed-by: Rodrigo Vivi
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 36 -
> 1 file changed, 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00e03560c4e7..c59cfa83dbaf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4209,42 +4209,6 @@ enum {
> #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
> #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
>
> -/* VLV eDP PSR registers */
> -#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
> -#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
> -#define VLV_EDP_PSR_ENABLE (1 << 0)
> -#define VLV_EDP_PSR_RESET (1 << 1)
> -#define VLV_EDP_PSR_MODE_MASK (7 << 2)
> -#define VLV_EDP_PSR_MODE_HW_TIMER (1 << 3)
> -#define VLV_EDP_PSR_MODE_SW_TIMER (1 << 2)
> -#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1 << 7)
> -#define VLV_EDP_PSR_ACTIVE_ENTRY(1 << 8)
> -#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1 << 9)
> -#define VLV_EDP_PSR_DBL_FRAME (1 << 10)
> -#define VLV_EDP_PSR_FRAME_COUNT_MASK(0xff << 16)
> -#define VLV_EDP_PSR_IDLE_FRAME_SHIFT16
> -#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
> -
> -#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
> -#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
> -#define VLV_EDP_PSR_SDP_FREQ_MASK (3 << 30)
> -#define VLV_EDP_PSR_SDP_FREQ_ONCE (1 << 31)
> -#define VLV_EDP_PSR_SDP_FREQ_EVFRAME(1 << 30)
> -#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
> -
> -#define _PSRSTATA(VLV_DISPLAY_BASE + 0x60094)
> -#define _PSRSTATB(VLV_DISPLAY_BASE + 0x61094)
> -#define VLV_EDP_PSR_LAST_STATE_MASK (7 << 3)
> -#define VLV_EDP_PSR_CURR_STATE_MASK 7
> -#define VLV_EDP_PSR_DISABLED(0 << 0)
> -#define VLV_EDP_PSR_INACTIVE(1 << 0)
> -#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2 << 0)
> -#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3 << 0)
> -#define VLV_EDP_PSR_ACTIVE_SF_UPDATE(4 << 0)
> -#define VLV_EDP_PSR_EXIT(5 << 0)
> -#define VLV_EDP_PSR_IN_TRANS(1 << 7)
> -#define VLV_PSRSTAT(pipe)_MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
> -
> /* HSW+ eDP PSR registers */
> #define HSW_EDP_PSR_BASE 0x64800
> #define BDW_EDP_PSR_BASE 0x6f800
> --
> 2.21.0
>
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Re: [Intel-gfx] [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment
On Wed, Apr 03, 2019 at 04:35:33PM -0700, José Roberto de Souza wrote: > Turn out it is not a DMC bug it is actually a HW one, so this > workaround will be needed for current gens, lets update the comment > and remove the FIXME. Do we have a Wa #number for this? p[art of workaround page or just part of programming sequence? > > BSpec: 7723 > Cc: Dhinakaran Pandiyan > Cc: Rodrigo Vivi > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/intel_psr.c | 6 ++ > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index ec874d802d48..c80bb3003a7d 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > val |= EDP_PSR2_TP2_TIME_2500us; > > /* > - * FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin > - * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after > - * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now > - * lets workaround the issue by cleaning PSR_CTL before enable PSR2. > + * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > + * recommending keep this bit unset while PSR2 is enabled. >*/ > I915_WRITE(EDP_PSR_CTL, 0); > > -- > 2.21.0 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-fixes
On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> vGPU display plane size calculation, shadow mm pin count,
> error recovery path for workload create and one kerneldoc
> fix which I missed to include before.
dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size"):
Fixes: SHA1 needs at least 12 digits:
dim: e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
dim: ERROR: issues in commits detected, aborting
Is it something you could fix on your side without having
to by-pass dim this time?
Thanks,
Rodrigo.
>
> Thanks.
> --
> The following changes since commit 26cdaac4793c49357d2c731f2190632cefb7efb1:
>
> drm/i915/icl: Fix VEBOX mismatch BUG_ON() (2019-03-28 15:36:40 +0200)
>
> are available in the Git repository at:
>
> https://github.com/intel/gvt-linux.git tags/gvt-fixes-2019-04-02
>
> for you to fetch changes up to a14f068545cc13db9e0ad0ea451ec42e5abc97c0:
>
> drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug (2019-03-29
> 10:31:15 +0800)
>
>
> gvt-fixes-2019-04-02
>
> - Fix shadow mm pin count (Yan)
> - Fix cmd parser error path recover (Yan)
> - Fix vGPU display plane size calculation (Xiong)
> - Fix kerneldoc (Chris)
>
>
> Chris Wilson (1):
> drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug
>
> Xiong Zhang (1):
> drm/i915/gvt: Correct the calculation of plane size
>
> Yan Zhao (2):
> drm/i915/gvt: do not deliver a workload if its creation fails
> drm/i915/gvt: do not let pin count of shadow mm go negative
>
> drivers/gpu/drm/i915/gvt/display.c | 2 +-
> drivers/gpu/drm/i915/gvt/dmabuf.c| 8 ++--
> drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.c | 5 +++--
> 4 files changed, 7 insertions(+), 10 deletions(-)
>
>
> --
> Open Source Technology Center, Intel ltd.
>
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment
== Series Details ==
Series: series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption
workaround comment
URL : https://patchwork.freedesktop.org/series/58974/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5867 -> Patchwork_12677
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12677 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12677, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58974/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12677:
### IGT changes ###
Possible regressions
* igt@gem_close_race@basic-threads:
- fi-icl-u2: PASS -> INCOMPLETE
Known issues
Here are the changes found in Patchwork_12677 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@gem_exec_basic@readonly-bsd2:
- fi-skl-6770hq: PASS -> DMESG-WARN [fdo#105541]
* igt@i915_module_load@reload:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709]
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u3}:FAIL [fdo#103167] -> PASS
Warnings
* igt@i915_selftest@live_contexts:
- fi-icl-y: INCOMPLETE [fdo#108569] -> DMESG-FAIL [fdo#108569]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
Participating hosts (50 -> 43)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5867 -> Patchwork_12677
CI_DRM_5867: 4a41303673f5b18b2b176182dd220d455f33d204 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4926: c9a9cf357b6b2a304623790bf8dae797e12888a8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12677: 2ec4ae3c2d94eb1a433c5d6a2739fe6a8e480fb0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2ec4ae3c2d94 drm/i915: Make PSR registers relative to transcoders
39c5d9840b98 drm/i915/psr: Remove partial PSR support on multiple transcoders
1a978559512b drm/i915/bdw+: Move misc display IRQ handling to it own function
841cd7fa823e drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
997ec2ab8f6d drm/i915/psr: Initialize PSR mutex even when sink is not reliable
e483edd370ea drm/i915: Remove unused VLV/CHV PSR registers
a823afc06f70 drm/i915/psr: Update PSR2 SU corruption workaround comment
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12677/
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment
== Series Details == Series: series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment URL : https://patchwork.freedesktop.org/series/58974/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/psr: Update PSR2 SU corruption workaround comment Okay! Commit: drm/i915: Remove unused VLV/CHV PSR registers Okay! Commit: drm/i915/psr: Initialize PSR mutex even when sink is not reliable Okay! Commit: drm/i915/psr: Do not enable PSR in interlaced mode for all GENs Okay! Commit: drm/i915/bdw+: Move misc display IRQ handling to it own function Okay! Commit: drm/i915/psr: Remove partial PSR support on multiple transcoders Okay! Commit: drm/i915: Make PSR registers relative to transcoders -drivers/gpu/drm/i915/selftests/../i915_drv.h:3623:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3624:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment
== Series Details == Series: series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment URL : https://patchwork.freedesktop.org/series/58974/ State : warning == Summary == $ dim checkpatch origin/drm-tip a823afc06f70 drm/i915/psr: Update PSR2 SU corruption workaround comment e483edd370ea drm/i915: Remove unused VLV/CHV PSR registers 997ec2ab8f6d drm/i915/psr: Initialize PSR mutex even when sink is not reliable 841cd7fa823e drm/i915/psr: Do not enable PSR in interlaced mode for all GENs 1a978559512b drm/i915/bdw+: Move misc display IRQ handling to it own function 39c5d9840b98 drm/i915/psr: Remove partial PSR support on multiple transcoders 2ec4ae3c2d94 drm/i915: Make PSR registers relative to transcoders -:93: WARNING:LONG_LINE: line over 100 characters #93: FILE: drivers/gpu/drm/i915/i915_reg.h:254: + INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ -:109: WARNING:LONG_LINE: line over 100 characters #109: FILE: drivers/gpu/drm/i915/i915_reg.h:4217: +#define _TRANS2_PSR(reg) (_TRANS2(dev_priv->psr.transcoder, (reg)) - dev_priv->psr.mmio_base_adjust) -:135: WARNING:LONG_LINE_COMMENT: line over 100 characters #135: FILE: drivers/gpu/drm/i915/i915_reg.h:4266: +#define EDP_PSR_AUX_DATA(i) _MMIO(_TRANS2_PSR(_SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */ total: 0 errors, 3 warnings, 0 checks, 166 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
This interlaced restriction applies to all gens, not only to Haswell.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index a84da931c3be..bb97c1657493 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -627,8 +627,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- if (IS_HASWELL(dev_priv) &&
- adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
return;
}
--
2.21.0
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[Intel-gfx] [PATCH 7/7] drm/i915: Make PSR registers relative to transcoders
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and
using it makes more difficult for people with an PSR register address
from BSpec to search the register name in i915 as also the BSpec name
don't match with the name in i915.
The other option would be use the whole hard-coded address but this is
not future proof, so here going in the middle ground by making every
PSR register relative to transcoder(that is EDP transcoder), the only
exception is PSR_IMR/IIR that is not relative to nothing.
For the _TRANS2() macros to work it needs the address of the register
from the TRANSCODER_A, so adding it to every register together with
the register address from the EDP transcoder so it will make easy for
people searching with BSpec address also adding those with the BSpec
name.
For Haswell all the PSR register are relative to 0x64000, so
mmio_base_adjust was added and used to take care of that.
Also removing BDW_EDP_PSR_BASE from GVT because it is not used as
the only PSR register that GVT have is this one(SRD/PSR_CTL).
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gvt/handlers.c | 1 -
drivers/gpu/drm/i915/i915_drv.h | 5 ++-
drivers/gpu/drm/i915/i915_reg.h | 59 -
drivers/gpu/drm/i915/intel_psr.c| 11 --
4 files changed, 52 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 86761b1def1e..d09b798e93cb 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2739,7 +2739,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
MMIO_D(WM_MISC, D_BDW);
- MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW);
MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8f38d03b1c4e..9ce46a7dabfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -501,6 +501,8 @@ struct i915_drrs {
};
struct i915_psr {
+ /* different than zero only on HSW see _TRANS2_PSR() for more info */
+ u32 mmio_base_adjust;
struct mutex lock;
#define I915_PSR_DEBUG_MODE_MASK 0x0f
@@ -515,6 +517,7 @@ struct i915_psr {
bool enabled;
struct intel_dp *dp;
enum pipe pipe;
+ enum transcoder transcoder;
bool active;
struct work_struct work;
unsigned busy_frontbuffer_bits;
@@ -1541,8 +1544,6 @@ struct drm_i915_private {
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
- u32 psr_mmio_base;
-
u32 pps_mmio_base;
wait_queue_head_t gmbus_wait_queue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 18e2991b376d..4df56c118cd2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -250,9 +250,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE2(pipe, reg)
_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
DISPLAY_MMIO_BASE(dev_priv))
-#define _MMIO_TRANS2(pipe, reg)
_MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
-
INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
- DISPLAY_MMIO_BASE(dev_priv))
+#define _TRANS2(trans, reg)
(INTEL_INFO(dev_priv)->trans_offsets[(trans)] - \
+
INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
+DISPLAY_MMIO_BASE(dev_priv))
+#define _MMIO_TRANS2(trans, reg) _MMIO(_TRANS2(trans, reg))
#define _CURSOR2(pipe, reg)
_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
DISPLAY_MMIO_BASE(dev_priv))
@@ -4210,9 +4211,15 @@ enum {
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
/* HSW+ eDP PSR registers */
-#define HSW_EDP_PSR_BASE 0x64800
-#define BDW_EDP_PSR_BASE 0x6f800
-#define EDP_PSR_CTL_MMIO(dev_priv->psr_mmio_base +
0)
+#define HSW_EDP_PSR_BASE 0x64000
+
+/* PSR registers on HSW is not relative to eDP transcoder */
+#define _TRANS2_PSR(reg) (_TRANS2(dev_priv->psr.transcoder, (reg)) -
dev_priv->psr.mmio_base_adjust)
+#define _MMIO_TRANS2_PSR(reg) _MMIO(_TRANS2_PSR(reg))
+
+#define _SRD_CTL_A
[Intel-gfx] [PATCH 3/7] drm/i915/psr: Initialize PSR mutex even when sink is not reliable
Even when driver is reloaded and hits this scenario the PSR mutex
should be initialized, otherwise reading PSR debugfs status will
execute mutex_lock() over a mutex that was not initialized.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c80bb3003a7d..a84da931c3be 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1227,7 +1227,6 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
if (val) {
DRM_DEBUG_KMS("PSR interruption error set\n");
dev_priv->psr.sink_not_reliable = true;
- return;
}
/* Set link_standby x link_off defaults */
--
2.21.0
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[Intel-gfx] [PATCH 5/7] drm/i915/bdw+: Move misc display IRQ handling to it own function
Just moving it to reduce the tabs and avoid break code lines.
No behavior changes intended here.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 63 +++--
1 file changed, 36 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index aa107a78cb36..527d5cb21baa 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2702,41 +2702,50 @@ static u32 gen8_de_port_aux_mask(struct
drm_i915_private *dev_priv)
return mask;
}
-static irqreturn_t
-gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
+static enum irqreturn
+gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv)
{
- irqreturn_t ret = IRQ_NONE;
- u32 iir;
- enum pipe pipe;
+ u32 iir = I915_READ(GEN8_DE_MISC_IIR);
+ enum irqreturn ret = IRQ_NONE;
+ bool found = false;
- if (master_ctl & GEN8_DE_MISC_IRQ) {
- iir = I915_READ(GEN8_DE_MISC_IIR);
- if (iir) {
- bool found = false;
-
- I915_WRITE(GEN8_DE_MISC_IIR, iir);
- ret = IRQ_HANDLED;
+ if (!iir) {
+ DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
+ return ret;
+ }
- if (iir & GEN8_DE_MISC_GSE) {
- intel_opregion_asle_intr(dev_priv);
- found = true;
- }
+ I915_WRITE(GEN8_DE_MISC_IIR, iir);
+ ret = IRQ_HANDLED;
- if (iir & GEN8_DE_EDP_PSR) {
- u32 psr_iir = I915_READ(EDP_PSR_IIR);
+ if (iir & GEN8_DE_MISC_GSE) {
+ intel_opregion_asle_intr(dev_priv);
+ found = true;
+ }
- intel_psr_irq_handler(dev_priv, psr_iir);
- I915_WRITE(EDP_PSR_IIR, psr_iir);
- found = true;
- }
+ if (iir & GEN8_DE_EDP_PSR) {
+ u32 psr_iir = I915_READ(EDP_PSR_IIR);
- if (!found)
- DRM_ERROR("Unexpected DE Misc interrupt\n");
- }
- else
- DRM_ERROR("The master control interrupt lied (DE
MISC)!\n");
+ intel_psr_irq_handler(dev_priv, psr_iir);
+ I915_WRITE(EDP_PSR_IIR, psr_iir);
+ found = true;
}
+ if (!found)
+ DRM_ERROR("Unexpected DE Misc interrupt\n");
+
+ return ret;
+}
+
+static irqreturn_t
+gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
+{
+ irqreturn_t ret = IRQ_NONE;
+ u32 iir;
+ enum pipe pipe;
+
+ if (master_ctl & GEN8_DE_MISC_IRQ)
+ ret = gen8_de_misc_irq_handler(dev_priv);
+
if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
iir = I915_READ(GEN11_DE_HPD_IIR);
if (iir) {
--
2.21.0
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[Intel-gfx] [PATCH 2/7] drm/i915: Remove unused VLV/CHV PSR registers
PSR support for VLV and CHV was dropped in commit ce3508fd2a77
("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep
this registers around.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 36 -
1 file changed, 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00e03560c4e7..c59cfa83dbaf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4209,42 +4209,6 @@ enum {
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
-/* VLV eDP PSR registers */
-#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
-#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
-#define VLV_EDP_PSR_ENABLE(1 << 0)
-#define VLV_EDP_PSR_RESET (1 << 1)
-#define VLV_EDP_PSR_MODE_MASK (7 << 2)
-#define VLV_EDP_PSR_MODE_HW_TIMER (1 << 3)
-#define VLV_EDP_PSR_MODE_SW_TIMER (1 << 2)
-#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1 << 7)
-#define VLV_EDP_PSR_ACTIVE_ENTRY (1 << 8)
-#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1 << 9)
-#define VLV_EDP_PSR_DBL_FRAME (1 << 10)
-#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff << 16)
-#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
-#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
-
-#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
-#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
-#define VLV_EDP_PSR_SDP_FREQ_MASK (3 << 30)
-#define VLV_EDP_PSR_SDP_FREQ_ONCE (1 << 31)
-#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1 << 30)
-#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
-
-#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
-#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
-#define VLV_EDP_PSR_LAST_STATE_MASK (7 << 3)
-#define VLV_EDP_PSR_CURR_STATE_MASK 7
-#define VLV_EDP_PSR_DISABLED (0 << 0)
-#define VLV_EDP_PSR_INACTIVE (1 << 0)
-#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE(2 << 0)
-#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3 << 0)
-#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4 << 0)
-#define VLV_EDP_PSR_EXIT (5 << 0)
-#define VLV_EDP_PSR_IN_TRANS (1 << 7)
-#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
-
/* HSW+ eDP PSR registers */
#define HSW_EDP_PSR_BASE 0x64800
#define BDW_EDP_PSR_BASE 0x6f800
--
2.21.0
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[Intel-gfx] [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment
Turn out it is not a DMC bug it is actually a HW one, so this workaround will be needed for current gens, lets update the comment and remove the FIXME. BSpec: 7723 Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index ec874d802d48..c80bb3003a7d 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -531,10 +531,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_TP2_TIME_2500us; /* -* FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin -* and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after -* exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now -* lets workaround the issue by cleaning PSR_CTL before enable PSR2. +* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is +* recommending keep this bit unset while PSR2 is enabled. */ I915_WRITE(EDP_PSR_CTL, 0); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915/psr: Remove partial PSR support on multiple transcoders
PSR is only supported in eDP transcoder and there is only one
instance of it, so lets drop all of this code.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 17 +---
drivers/gpu/drm/i915/intel_psr.c | 147 ---
2 files changed, 42 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c59cfa83dbaf..18e2991b376d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4241,13 +4241,9 @@ enum {
/* Bspec claims those aren't shifted but stay at 0x64800 */
#define EDP_PSR_IMR_MMIO(0x64834)
#define EDP_PSR_IIR_MMIO(0x64838)
-#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
-#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
-#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
-#define EDP_PSR_TRANSCODER_C_SHIFT 24
-#define EDP_PSR_TRANSCODER_B_SHIFT 16
-#define EDP_PSR_TRANSCODER_A_SHIFT 8
-#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
+#define EDP_PSR_ERROR(1 << 2)
+#define EDP_PSR_POST_EXIT(1 << 1)
+#define EDP_PSR_PRE_ENTRY(1 << 0)
#define EDP_PSR_AUX_CTL
_MMIO(dev_priv->psr_mmio_base + 0x10)
#define EDP_PSR_AUX_CTL_TIME_OUT_MASK(3 << 26)
@@ -4312,12 +4308,7 @@ enum {
#define EDP_PSR2_IDLE_FRAME_MASK 0xf
#define EDP_PSR2_IDLE_FRAME_SHIFT0
-#define _PSR_EVENT_TRANS_A 0x60848
-#define _PSR_EVENT_TRANS_B 0x61848
-#define _PSR_EVENT_TRANS_C 0x62848
-#define _PSR_EVENT_TRANS_D 0x63848
-#define _PSR_EVENT_TRANS_EDP 0x6F848
-#define PSR_EVENT(trans) _MMIO_TRANS2(trans,
_PSR_EVENT_TRANS_A)
+#define PSR_EVENT _MMIO(0x6F848)
#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE(1 << 17)
#define PSR_EVENT_PSR2_DISABLED (1 << 16)
#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bb97c1657493..b984e005b72e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -84,46 +84,12 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
}
}
-static int edp_psr_shift(enum transcoder cpu_transcoder)
-{
- switch (cpu_transcoder) {
- case TRANSCODER_A:
- return EDP_PSR_TRANSCODER_A_SHIFT;
- case TRANSCODER_B:
- return EDP_PSR_TRANSCODER_B_SHIFT;
- case TRANSCODER_C:
- return EDP_PSR_TRANSCODER_C_SHIFT;
- default:
- MISSING_CASE(cpu_transcoder);
- /* fallthrough */
- case TRANSCODER_EDP:
- return EDP_PSR_TRANSCODER_EDP_SHIFT;
- }
-}
-
void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
{
- u32 debug_mask, mask;
- enum transcoder cpu_transcoder;
- u32 transcoders = BIT(TRANSCODER_EDP);
-
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- debug_mask = 0;
- mask = 0;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
-
- mask |= EDP_PSR_ERROR(shift);
- debug_mask |= EDP_PSR_POST_EXIT(shift) |
- EDP_PSR_PRE_ENTRY(shift);
- }
+ u32 mask = EDP_PSR_ERROR;
if (debug & I915_PSR_DEBUG_IRQ)
- mask |= debug_mask;
+ mask |= EDP_PSR_POST_EXIT | EDP_PSR_PRE_ENTRY;
I915_WRITE(EDP_PSR_IMR, ~mask);
}
@@ -167,62 +133,47 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
- u32 transcoders = BIT(TRANSCODER_EDP);
- enum transcoder cpu_transcoder;
- ktime_t time_ns = ktime_get();
- u32 mask = 0;
+ ktime_t time_ns = ktime_get();
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
-
- if (psr_iir & EDP_PSR_ERROR(shift)) {
- DRM_WARN("[transcoder %s] PSR aux error\n",
-transcoder_name(cpu_transcoder));
-
- dev_priv->psr.irq_aux_error = true;
-
- /
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use lockdep_pin_lock() over the construction of the request
== Series Details == Series: drm/i915: Use lockdep_pin_lock() over the construction of the request URL : https://patchwork.freedesktop.org/series/58932/ State : success == Summary == CI Bug Log - changes from CI_DRM_5860_full -> Patchwork_12672_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12672_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> SKIP [fdo#109314] * igt@gem_exec_parallel@bsd1: - shard-skl: NOTRUN -> SKIP [fdo#109271] +103 * igt@gem_exec_parallel@bsd2-fds: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +12 * igt@gem_exec_schedule@wide-bsd: - shard-iclb: PASS -> FAIL [fdo#109633] * igt@gem_stolen@stolen-clear: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +3 * igt@gem_tiled_fence_blits@normal: - shard-iclb: NOTRUN -> TIMEOUT [fdo#109673] * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> DMESG-WARN [fdo#108686] * igt@gem_userptr_blits@coherency-unsync: - shard-iclb: NOTRUN -> SKIP [fdo#109290] +1 * igt@i915_pm_rpm@drm-resources-equal: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@gem-execbuf-stress: - shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-iclb: NOTRUN -> SKIP [fdo#109506] * igt@i915_pm_rpm@modeset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@kms_atomic_transition@6x-modeset-transitions-fencing: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_atomic_transition@plane-all-modeset-transition-fencing: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@kms_busy@extended-modeset-hang-newfb-render-b: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-snb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +11 * igt@kms_busy@extended-pageflip-hang-newfb-render-e: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +6 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-glk: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-d: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +12 * igt@kms_chamelium@dp-hpd-storm-disable: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +4 * igt@kms_color@pipe-b-degamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_content_protection@legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109300] * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-glk: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-512x512-onscreen: - shard-iclb: NOTRUN -> SKIP [fdo#109279] +1 * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +5 * igt@kms_fbcon_fbt@fbc: - shard-iclb: PASS -> DMESG-WARN [fdo#109593] * igt@kms_flip@2x-plain-flip-ts-check: - shard-apl: NOTRUN -> SKIP [fdo#109271] +33 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: - shard-iclb: PASS -> FAIL [fdo#103167] +10 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-snb: NOTRUN -> SKIP [fdo#109271] +111 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#109247] +12 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: NOTRUN -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +18 * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-glk: NOTRUN -> SKIP [fdo#109271] +21 * igt@kms_lease@cursor_implicit_plane: - shard-skl: NOTRUN -> FAIL [fdo#110278] * igt@kms_lease@setcrtc_implicit_plane: - shard-iclb: NOTRUN -> FAIL [fdo#110281] * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-apl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_scaling@pipe-a-scaler-with-pi
[Intel-gfx] [PATCH i-g-t] lib: Rework __kms_addfb() function
The function __kms_addfb() and drmModeAddFB2WithModifiers() have a
similar code. Due to this similarity, this commit replace part of the
code inside __kms_addfb() by using drmModeAddFB2WithModifiers().
Signed-off-by: Rodrigo Siqueira
---
lib/ioctl_wrappers.c | 27 ++-
1 file changed, 6 insertions(+), 21 deletions(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 39920f87..4240d138 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -46,6 +46,7 @@
#include
#include
#include
+#include
#include "drmtest.h"
#include "i915_drm.h"
@@ -1479,29 +1480,13 @@ int __kms_addfb(int fd, uint32_t handle,
uint32_t strides[4], uint32_t offsets[4],
int num_planes, uint32_t flags, uint32_t *buf_id)
{
- struct drm_mode_fb_cmd2 f;
- int ret, i;
+ uint32_t handles[4] = {handle};
+ uint64_t modifiers[4] = {modifier};
if (flags & DRM_MODE_FB_MODIFIERS)
igt_require_fb_modifiers(fd);
- memset(&f, 0, sizeof(f));
-
- f.width = width;
- f.height = height;
- f.pixel_format = pixel_format;
- f.flags = flags;
-
- for (i = 0; i < num_planes; i++) {
- f.handles[i] = handle;
- f.modifier[i] = modifier;
- f.pitches[i] = strides[i];
- f.offsets[i] = offsets[i];
- }
-
- ret = igt_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, &f);
-
- *buf_id = f.fb_id;
-
- return ret < 0 ? -errno : ret;
+ return drmModeAddFB2WithModifiers(fd, width, height, pixel_format,
+ handles, strides, offsets, modifiers,
+ buf_id, flags);
}
--
2.21.0
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init
== Series Details == Series: drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init URL : https://patchwork.freedesktop.org/series/58921/ State : success == Summary == CI Bug Log - changes from CI_DRM_5860_full -> Patchwork_12670_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_12670_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12670_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12670_full: ### IGT changes ### Warnings * igt@kms_flip@2x-flip-vs-dpms: - shard-iclb: SKIP [fdo#109274] -> INCOMPLETE Known issues Here are the changes found in Patchwork_12670_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> SKIP [fdo#109314] * igt@gem_exec_parallel@bsd2-fds: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +15 * igt@gem_stolen@stolen-clear: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +3 * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> FAIL [fdo#108686] * igt@gem_userptr_blits@coherency-unsync: - shard-iclb: NOTRUN -> SKIP [fdo#109290] +1 * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: NOTRUN -> FAIL [fdo#107847] * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-iclb: NOTRUN -> SKIP [fdo#109506] * igt@i915_pm_rpm@legacy-planes: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@modeset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@kms_busy@extended-modeset-hang-newfb-render-b: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-snb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14 * igt@kms_busy@extended-pageflip-hang-newfb-render-e: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +6 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-glk: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-d: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +12 * igt@kms_chamelium@dp-hpd-storm-disable: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +4 * igt@kms_color@pipe-b-degamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_content_protection@legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109300] * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-glk: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-512x512-onscreen: - shard-iclb: NOTRUN -> SKIP [fdo#109279] +1 * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +6 * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-iclb: NOTRUN -> FAIL [fdo#103355] * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +122 * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-iclb: PASS -> FAIL [fdo#109247] +11 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-snb: NOTRUN -> SKIP [fdo#109271] +111 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +20 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-glk: NOTRUN -> SKIP [fdo#109271] +21 * igt@kms_lease@cursor_implicit_plane: - shard-skl: NOTRUN -> FAIL [fdo#110278] * igt@kms_lease@setcrtc_implicit_plane: - shard-iclb: NOTRUN -> FAIL [fdo#110281] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-apl: PASS -> DMESG-WARN [fdo#108566] * igt@kms_plane_alpha_blend@pi
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev3)
== Series Details == Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev3) URL : https://patchwork.freedesktop.org/series/58912/ State : success == Summary == CI Bug Log - changes from CI_DRM_5860_full -> Patchwork_12669_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12669_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-snb: PASS -> INCOMPLETE [fdo#105411] * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> SKIP [fdo#109314] * igt@gem_exec_parallel@bsd2-fds: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +16 * igt@gem_stolen@stolen-clear: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +3 * igt@gem_userptr_blits@coherency-unsync: - shard-iclb: NOTRUN -> SKIP [fdo#109290] +1 * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: NOTRUN -> FAIL [fdo#107847] * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-iclb: NOTRUN -> SKIP [fdo#109506] * igt@i915_pm_rpm@modeset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@i915_pm_rpm@pm-tiling: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@reg-read-ioctl: - shard-skl: NOTRUN -> INCOMPLETE [fdo#107807] +1 * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@kms_atomic_transition@6x-modeset-transitions-fencing: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_atomic_transition@plane-all-modeset-transition-fencing: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@kms_busy@extended-modeset-hang-newfb-render-b: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-snb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-pageflip-hang-newfb-render-e: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +7 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-glk: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-d: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +12 * igt@kms_chamelium@dp-hpd-storm-disable: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +4 * igt@kms_color@pipe-b-degamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_content_protection@legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109300] * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-glk: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-512x512-onscreen: - shard-iclb: NOTRUN -> SKIP [fdo#109279] +1 * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +6 * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-iclb: PASS -> FAIL [fdo#103355] * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: PASS -> FAIL [fdo#102670] * igt@kms_flip@2x-plain-flip-ts-check: - shard-apl: NOTRUN -> SKIP [fdo#109271] +24 * igt@kms_flip@flip-vs-suspend: - shard-skl: NOTRUN -> INCOMPLETE [fdo#109507] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-iclb: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +101 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-snb: NOTRUN -> SKIP [fdo#109271] +111 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +5 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +23 * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#106978] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt: - shard-iclb: PASS -> FAIL [fdo#109247] +1 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: NOTRUN -> FAIL [fdo#109247] +1 * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-glk: NOTRUN -> SKIP [fdo#109271] +21 * igt@kms_lease@cursor_implicit_plane: - shard-skl: NOTRUN -> FAIL [fdo#110278] * igt@kms_lease@setcrtc_implicit_plane: - shard-iclb: NOTRUN -> FAIL [fdo#110281] * igt@kms_
Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count
On Wed, Apr 03, 2019 at 10:22:16PM +0300, Ville Syrjälä wrote: > On Wed, Apr 03, 2019 at 12:07:35PM -0700, Manasi Navare wrote: > > On Wed, Apr 03, 2019 at 09:55:56PM +0300, Ville Syrjälä wrote: > > > On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote: > > > > On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote: > > > > > On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote: > > > > > > For certain eDP 1.4 panels, we need to use max lane count for the > > > > > > link training to succeed. > > > > > > > > > > > > This patch adds a EDID quirk for such eDP panels using > > > > > > their vendor ID and product ID to force using max lane count in the > > > > > > driver. > > > > > > > > > > Rather than opening the quirk can of worms I think we should consider > > > > > changing the retry loop to do something more sensible than what it's > > > > > doing now. The current behaviour of "start at optimal settings (which > > > > > can be either min lanes or min rate), and then reduce lanes/rate until > > > > > stuff works" overlooks several possible combinations. One possible > > > > > approach could be to start the retry loop with max lanes + max rate > > > > > after the optimal settings have failed. It probably won't give you > > > > > the best power consumption, but at least you get a picture on the > > > > > screen if even a single lane count + rate combo works. > > > > > > > > > > > > > So you are saying that for eDP only we should modify the retry function > > > > to > > > > retry with max lanes and max rate so what we used to do earlier with < > > > > eDP 1.4? > > > > > > > > Hmm I could try doing that, the only concern I have there is that > > > > certain eDP > > > > panels just need a retry at same parameters to work so for such panels > > > > where the lower values of link rate/lane count work with just an extra > > > > retry > > > > we would still be using max link rate /lane count now with this change. > > > > > > If the panels are borked then I wouln't worry about it as long a picture > > > appaears on the screen. And if the extra training cycle is because of > > > some bug in our code then we should figure it out what that bug is. > > > > > > > But we should do this retrain() in our existing modeset_retry() and > > intel_dp_get_fallback_values() > > and only do it for eDP right? > > Because DP we have the retrain loops as per the compliance, if we change > > that that will > > affect all the compliance tests. > > I have a rather low opinion on the compliance tests. If they are > preventing sensible real world things then what good are they? > Someone should probably figure out what it would take to make > them more useful... > > But anyways, I guess we can start with eDP. If it looks like > DP could benefit as well we might have to consider it. > I agree, i will add a patch for edp first and have the folks test it with the edp panels that needed the quirk. DP we really havent had any similar failures where we absolutely need max vales. Manasi > -- > Ville Syrjälä > Intel > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: use unsigned long for platform_mask
On Wed, Apr 03, 2019 at 10:25:33AM +0100, Tvrtko Ursulin wrote:
On 03/04/2019 09:15, Lucas De Marchi wrote:
On Tue, Apr 2, 2019 at 11:58 PM Tvrtko Ursulin
wrote:
On 03/04/2019 02:46, Lucas De Marchi wrote:
No reason to stick to u32 for platform mask if we can just use more bits
on 64 bit platforms.
$ size drivers/gpu/drm/i915/i915.ko*
text data bss dec hex filename
1884779 413345408 1931521 1d7901 drivers/gpu/drm/i915/i915.ko
1886693 413585408 1933459 1d8093 drivers/gpu/drm/i915/i915.ko.old
How did you get such a large difference, and decrease even? Could you
check in the code what is happening? Because I get an increase with this
patch:
textdata bss dec hex filename
1905314 439037424 1956641 1ddb21 i915.ko.orig
1905796 439037424 1957123 1ddd03 i915.ko.patch
the only explanation I really have is that my measurement was bogus.
Some possible explanations...
1) I compared a i386 to a x86-64 build; 2) somehow a config changed
between the builds;
3) when preparing the patch I rebased on upstream between the builds.
Checking (1), no... that's in the ~400k range. So no idea, sorry.
I was worried you'd say you compiler just behaves differently. To
eliminate this option it would still be good to double check if you
can find the time.
I tried some options, to reproduce it again, but I couldn't. Interesting
that I remember running pahole on the result .ko and getting the result
I was expecting.
I thought about looking into my .bash_history, but it already rotated.
So I think the only useful thing in this patch is to make the array to
grow automatically. Or maybe not even that?
I really liked that and then started thinking that it can still sneak
up a mistake if one changes the type of the member and forgets to
change the type in size calculation BITS_PER_TYPE. So I ended up a
little less sure. Could the calculation self-reference the struct
member?
afaik, no. Because the struct is already not defined at this point. So
the usual trick of getting the size without an insntance doesn't work.
I.e. sizeof(((struct bla *)0)->member[0]) works outside of bla, but not
while we are defining it.
Well.. it can also happen of someone changing the type here and
forgetting to change "mask" in other function (see v1). I think since
they are in the same line it's easy to spot the mistake. But no strong
opinion. We already have 64 - 6 bits of platform bits that's probably
sufficient for a long time.
Lucas De Marchi
Regards,
Tvrtko
Lucas De Marchi
Regards,
Tvrtko
Now on 64 bits we have only one long as opposed to 2 u32:
$ pahole -C intel_runtime_info drivers/gpu/drm/i915/i915.ko
struct intel_runtime_info {
long unsigned int platform_mask[1]; /* 0 8 */
...
}
On 32 bits we still have the same thing as before:
$ size drivers/gpu/drm/i915/i915.ko*
text data bss dec hex filename
1489839 324852816 1525140 174594 drivers/gpu/drm/i915/i915.ko
1489839 324852816 1525140 174594 drivers/gpu/drm/i915/i915.ko.old
Besides reducing the code on x86-64 now the array size is automatically
calculated and we don't have to worry about extending it anymore.
v2: fix sparse and checkpatch warnings
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 7 +++
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ab4826921f7..9fe765ffe878 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2309,10 +2309,6 @@ __platform_mask_index(const struct intel_runtime_info
*info,
const unsigned int pbits =
BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
- /* Expand the platform_mask array if this fails. */
- BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
- pbits * ARRAY_SIZE(info->platform_mask));
-
return p / pbits;
}
@@ -2354,7 +2350,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
const unsigned int pi = __platform_mask_index(info, p);
const unsigned int pb = __platform_mask_bit(info, p);
const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
- const u32 mask = info->platform_mask[pi];
+ const unsigned long mask = info->platform_mask[pi];
BUILD_BUG_ON(!__builtin_constant_p(p));
BUILD_BUG_ON(!__builtin_constant_p(s));
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0e579f158016..2f5ca2b6f094 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -214,11 +214,10 @@ struct intel_runtime_info {
* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
* into single runtime conditionals, and also to provide groundwork
Re: [Intel-gfx] [PATCH v2 0/7] drm/i915: Finish the GAMMA_LUT stuff
On Wed, Apr 03, 2019 at 01:57:00PM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] > >Sent: Tuesday, April 2, 2019 1:32 AM > >To: intel-gfx@lists.freedesktop.org > >Cc: Shankar, Uma ; Roper, Matthew D > > > >Subject: [PATCH v2 0/7] drm/i915: Finish the GAMMA_LUT stuff > > > >From: Ville Syrjälä > > > >Rebased due to Uma's EXT_GC_MAX fix, and I added Matt's proposed behavioural > >change (expose 1024 entry LUTs in split gamma mode and just discard half the > >entries) as an extra patch on top. > > > >Everything is reviewed except patches 2 and 7. > > Reviewed the whole series and it looks perfect. > Reviewed-by: Uma Shankar Cool. Thanks for reading through it. Now pushed to dinq. > > > > >Ville Syrjälä (7): > > drm/i915: Extract ilk_lut_10() > > drm/i915: Don't use split gamma when we don't have to > > drm/i915: Implement split/10bit gamma for ivb/hsw > > drm/i915: Add 10bit LUT for ilk/snb > > drm/i915: Add "10.6" LUT mode for i965+ > > drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props > >on gen2/3 > > drm/i915: Expose full 1024 LUT entries on ivb+ > > > > drivers/gpu/drm/i915/i915_pci.c| 23 +- > > drivers/gpu/drm/i915/i915_reg.h| 15 ++ > > drivers/gpu/drm/i915/intel_color.c | 375 - > > 3 files changed, 292 insertions(+), 121 deletions(-) > > > >-- > >2.19.2 > -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count
On Wed, Apr 03, 2019 at 12:07:35PM -0700, Manasi Navare wrote: > On Wed, Apr 03, 2019 at 09:55:56PM +0300, Ville Syrjälä wrote: > > On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote: > > > On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote: > > > > On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote: > > > > > For certain eDP 1.4 panels, we need to use max lane count for the > > > > > link training to succeed. > > > > > > > > > > This patch adds a EDID quirk for such eDP panels using > > > > > their vendor ID and product ID to force using max lane count in the > > > > > driver. > > > > > > > > Rather than opening the quirk can of worms I think we should consider > > > > changing the retry loop to do something more sensible than what it's > > > > doing now. The current behaviour of "start at optimal settings (which > > > > can be either min lanes or min rate), and then reduce lanes/rate until > > > > stuff works" overlooks several possible combinations. One possible > > > > approach could be to start the retry loop with max lanes + max rate > > > > after the optimal settings have failed. It probably won't give you > > > > the best power consumption, but at least you get a picture on the > > > > screen if even a single lane count + rate combo works. > > > > > > > > > > So you are saying that for eDP only we should modify the retry function to > > > retry with max lanes and max rate so what we used to do earlier with < > > > eDP 1.4? > > > > > > Hmm I could try doing that, the only concern I have there is that certain > > > eDP > > > panels just need a retry at same parameters to work so for such panels > > > where the lower values of link rate/lane count work with just an extra > > > retry > > > we would still be using max link rate /lane count now with this change. > > > > If the panels are borked then I wouln't worry about it as long a picture > > appaears on the screen. And if the extra training cycle is because of > > some bug in our code then we should figure it out what that bug is. > > > > But we should do this retrain() in our existing modeset_retry() and > intel_dp_get_fallback_values() > and only do it for eDP right? > Because DP we have the retrain loops as per the compliance, if we change that > that will > affect all the compliance tests. I have a rather low opinion on the compliance tests. If they are preventing sensible real world things then what good are they? Someone should probably figure out what it would take to make them more useful... But anyways, I guess we can start with eDP. If it looks like DP could benefit as well we might have to consider it. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count
On Wed, Apr 03, 2019 at 09:55:56PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote:
> > On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> > > On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > > > For certain eDP 1.4 panels, we need to use max lane count for the
> > > > link training to succeed.
> > > >
> > > > This patch adds a EDID quirk for such eDP panels using
> > > > their vendor ID and product ID to force using max lane count in the
> > > > driver.
> > >
> > > Rather than opening the quirk can of worms I think we should consider
> > > changing the retry loop to do something more sensible than what it's
> > > doing now. The current behaviour of "start at optimal settings (which
> > > can be either min lanes or min rate), and then reduce lanes/rate until
> > > stuff works" overlooks several possible combinations. One possible
> > > approach could be to start the retry loop with max lanes + max rate
> > > after the optimal settings have failed. It probably won't give you
> > > the best power consumption, but at least you get a picture on the
> > > screen if even a single lane count + rate combo works.
> > >
> >
> > So you are saying that for eDP only we should modify the retry function to
> > retry with max lanes and max rate so what we used to do earlier with < eDP
> > 1.4?
> >
> > Hmm I could try doing that, the only concern I have there is that certain
> > eDP
> > panels just need a retry at same parameters to work so for such panels
> > where the lower values of link rate/lane count work with just an extra retry
> > we would still be using max link rate /lane count now with this change.
>
> If the panels are borked then I wouln't worry about it as long a picture
> appaears on the screen. And if the extra training cycle is because of
> some bug in our code then we should figure it out what that bug is.
>
But we should do this retrain() in our existing modeset_retry() and
intel_dp_get_fallback_values()
and only do it for eDP right?
Because DP we have the retrain loops as per the compliance, if we change that
that will
affect all the compliance tests.
Manasi
> >
> > Or are you suggesting doing the retry with same params for edp < 1.4 and
> > for all
> > edp 1.4 , we retry with , max link rate lane ocunt?
>
> retrain_fail()
> {
> if (!use_max_params) {
> use_max_params = true;
> rate = max;
> lanes = max;
> } else {
> reduce rate/lanes as usual
> }
> }
>
> compute_config()
> {
> if (use_max_params) {
> limits.min = limits.max;
> }
> ...
> }
>
> or something like that.
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: add Makefile magic for testing headers are self-contained
== Series Details == Series: series starting with [1/2] drm/i915: add Makefile magic for testing headers are self-contained URL : https://patchwork.freedesktop.org/series/58963/ State : success == Summary == CI Bug Log - changes from CI_DRM_5865 -> Patchwork_12676 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58963/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12676 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@i915_selftest@live_uncore: - fi-skl-gvtdvm: DMESG-FAIL [fdo#110210] -> PASS - fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS Warnings * igt@i915_selftest@live_contexts: - fi-icl-y: INCOMPLETE [fdo#108569] -> DMESG-FAIL [fdo#108569] [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 Participating hosts (46 -> 37) -- Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_5865 -> Patchwork_12676 CI_DRM_5865: 0dafc5b0971e3e7622864fe0987d6676f0d2c7a6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4925: ca623acb8b2b6f0a4cdb01946dc9002e11d62574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12676: 73cd40065843706e3f54b2acf13bf337042844d2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 73cd40065843 drm/i915: Move GraphicsTechnology files under gt/ 5f24918578ab drm/i915: add Makefile magic for testing headers are self-contained == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12676/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count
On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote:
> On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> > On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > > For certain eDP 1.4 panels, we need to use max lane count for the
> > > link training to succeed.
> > >
> > > This patch adds a EDID quirk for such eDP panels using
> > > their vendor ID and product ID to force using max lane count in the
> > > driver.
> >
> > Rather than opening the quirk can of worms I think we should consider
> > changing the retry loop to do something more sensible than what it's
> > doing now. The current behaviour of "start at optimal settings (which
> > can be either min lanes or min rate), and then reduce lanes/rate until
> > stuff works" overlooks several possible combinations. One possible
> > approach could be to start the retry loop with max lanes + max rate
> > after the optimal settings have failed. It probably won't give you
> > the best power consumption, but at least you get a picture on the
> > screen if even a single lane count + rate combo works.
> >
>
> So you are saying that for eDP only we should modify the retry function to
> retry with max lanes and max rate so what we used to do earlier with < eDP
> 1.4?
>
> Hmm I could try doing that, the only concern I have there is that certain eDP
> panels just need a retry at same parameters to work so for such panels
> where the lower values of link rate/lane count work with just an extra retry
> we would still be using max link rate /lane count now with this change.
If the panels are borked then I wouln't worry about it as long a picture
appaears on the screen. And if the extra training cycle is because of
some bug in our code then we should figure it out what that bug is.
>
> Or are you suggesting doing the retry with same params for edp < 1.4 and for
> all
> edp 1.4 , we retry with , max link rate lane ocunt?
retrain_fail()
{
if (!use_max_params) {
use_max_params = true;
rate = max;
lanes = max;
} else {
reduce rate/lanes as usual
}
}
compute_config()
{
if (use_max_params) {
limits.min = limits.max;
}
...
}
or something like that.
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count
On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > For certain eDP 1.4 panels, we need to use max lane count for the
> > link training to succeed.
> >
> > This patch adds a EDID quirk for such eDP panels using
> > their vendor ID and product ID to force using max lane count in the driver.
>
> Rather than opening the quirk can of worms I think we should consider
> changing the retry loop to do something more sensible than what it's
> doing now. The current behaviour of "start at optimal settings (which
> can be either min lanes or min rate), and then reduce lanes/rate until
> stuff works" overlooks several possible combinations. One possible
> approach could be to start the retry loop with max lanes + max rate
> after the optimal settings have failed. It probably won't give you
> the best power consumption, but at least you get a picture on the
> screen if even a single lane count + rate combo works.
>
So you are saying that for eDP only we should modify the retry function to
retry with max lanes and max rate so what we used to do earlier with < eDP 1.4?
Hmm I could try doing that, the only concern I have there is that certain eDP
panels just need a retry at same parameters to work so for such panels
where the lower values of link rate/lane count work with just an extra retry
we would still be using max link rate /lane count now with this change.
Or are you suggesting doing the retry with same params for edp < 1.4 and for all
edp 1.4 , we retry with , max link rate lane ocunt?
Manasi
> >
> > Cc: Clint Taylor
> > Cc: Ville Syrjälä
> > Tested-by: Albert Astals Cid
> > Tested-by: Emanuele Panigati
> > Tested-by: Ralgor
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/drm_edid.c | 10 ++
> > include/drm/drm_connector.h | 5 +
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 2c22ea446075..fbc661806484 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -82,6 +82,8 @@
> > #define EDID_QUIRK_FORCE_10BPC (1 << 11)
> > /* Non desktop display (i.e. HMD) */
> > #define EDID_QUIRK_NON_DESKTOP (1 << 12)
> > +/* Force max lane count */
> > +#define EDID_QUIRK_FORCE_MAX_LANE_COUNT(1 << 13)
> >
> > struct detailed_mode_closure {
> > struct drm_connector *connector;
> > @@ -189,6 +191,10 @@ static const struct edid_quirk {
> >
> > /* OSVR HDK and HDK2 VR Headsets */
> > { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
> > +
> > + /* SHP eDP 1.4 panel only works with max lane count */
> > + { "SHP", 0x149a, EDID_QUIRK_FORCE_MAX_LANE_COUNT },
> > + { "SHP", 0x148e, EDID_QUIRK_FORCE_MAX_LANE_COUNT },
> > };
> >
> > /*
> > @@ -4463,6 +4469,7 @@ drm_reset_display_info(struct drm_connector
> > *connector)
> > memset(&info->hdmi, 0, sizeof(info->hdmi));
> >
> > info->non_desktop = 0;
> > + info->force_max_lane_count = 0;
> > }
> >
> > u32 drm_add_display_info(struct drm_connector *connector, const struct
> > edid *edid)
> > @@ -4744,6 +4751,9 @@ int drm_add_edid_modes(struct drm_connector
> > *connector, struct edid *edid)
> > if (quirks & EDID_QUIRK_FORCE_12BPC)
> > connector->display_info.bpc = 12;
> >
> > + if (quirks & EDID_QUIRK_FORCE_MAX_LANE_COUNT)
> > + connector->display_info.force_max_lane_count = true;
> > +
> > return num_modes;
> > }
> > EXPORT_SYMBOL(drm_add_edid_modes);
> > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> > index 02a131202add..45436d40ffe3 100644
> > --- a/include/drm/drm_connector.h
> > +++ b/include/drm/drm_connector.h
> > @@ -457,6 +457,11 @@ struct drm_display_info {
> > * @non_desktop: Non desktop display (HMD).
> > */
> > bool non_desktop;
> > +
> > + /**
> > +* @force_max_lane_count: Link training requires max lane count to pass
> > +*/
> > + bool force_max_lane_count;
> > };
> >
> > int drm_display_info_set_bus_formats(struct drm_display_info *info,
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: add Makefile magic for testing headers are self-contained
== Series Details == Series: series starting with [1/2] drm/i915: add Makefile magic for testing headers are self-contained URL : https://patchwork.freedesktop.org/series/58963/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: add Makefile magic for testing headers are self-contained Okay! Commit: drm/i915: Move GraphicsTechnology files under gt/ +drivers/gpu/drm/i915/gt/intel_context.c:130:22: warning: context imbalance in 'intel_context_pin_lock' - wrong count at exit +drivers/gpu/drm/i915/gt/intel_engine.h:125:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gt/intel_engine.h:125:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gt/intel_lrc.c:2551:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gt/intel_context.c:130:22: warning: context imbalance in 'intel_context_pin_lock' - wrong count at exit -drivers/gpu/drm/i915/gt/intel_lrc.c:2551:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gt/intel_engine.h:125:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gt/intel_engine.h:125:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3623:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3610:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/slab.h:666:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:666:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:666:13: warning: call with no type! +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: add Makefile magic for testing headers are self-contained
== Series Details ==
Series: series starting with [1/2] drm/i915: add Makefile magic for testing
headers are self-contained
URL : https://patchwork.freedesktop.org/series/58963/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5f24918578ab drm/i915: add Makefile magic for testing headers are self-contained
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 39e2f501c1b4 ("drm/i915: Split
struct intel_context definition to its own header")'
#10:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3a891a626794 ("drm/i915: Move
intel_engine_mask_t around for use by i915_request_types.h")'
#11:
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 8b74594aa455 ("drm/i915: Split
out i915_priolist_types into its own header")'
#12:
8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#25:
new file mode 100644
total: 3 errors, 2 warnings, 0 checks, 52 lines checked
73cd40065843 drm/i915: Move GraphicsTechnology files under gt/
-:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#87:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 538 lines checked
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add immutable zpos plane properties (rev2)
== Series Details == Series: drm/i915: add immutable zpos plane properties (rev2) URL : https://patchwork.freedesktop.org/series/58761/ State : success == Summary == CI Bug Log - changes from CI_DRM_5865 -> Patchwork_12675 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58761/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12675 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-c: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62 * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@i915_selftest@live_uncore: - fi-skl-gvtdvm: DMESG-FAIL [fdo#110210] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-byt-clapper: FAIL [fdo#107362] -> PASS Warnings * igt@i915_selftest@live_contexts: - fi-icl-y: INCOMPLETE [fdo#108569] -> DMESG-FAIL [fdo#108569] [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (46 -> 39) -- Additional (2): fi-bsw-n3050 fi-pnv-d510 Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-kbl-7500u fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5865 -> Patchwork_12675 CI_DRM_5865: 0dafc5b0971e3e7622864fe0987d6676f0d2c7a6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4925: ca623acb8b2b6f0a4cdb01946dc9002e11d62574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12675: 326627292b936af7ee6895526e8ef42147e122d6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 326627292b93 drm/i915: add immutable zpos plane properties == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12675/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: add Makefile magic for testing headers are self-contained
From: Jani Nikula
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
The idea is fine, but the implementation is a bit tedious and
inflexible, and does not really scale well.
Implement the same in make using autogenerated dummy sources to include
the headers.
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/.gitignore | 1 +
drivers/gpu/drm/i915/Makefile | 16 -
drivers/gpu/drm/i915/Makefile.header-test | 23 +++
.../i915/test_i915_active_types_standalone.c | 7 --
.../test_i915_gem_context_types_standalone.c | 7 --
.../test_i915_priolist_types_standalone.c | 7 --
.../test_i915_scheduler_types_standalone.c| 7 --
.../test_i915_timeline_types_standalone.c | 7 --
.../test_intel_context_types_standalone.c | 7 --
.../i915/test_intel_engine_types_standalone.c | 7 --
.../test_intel_workarounds_types_standalone.c | 7 --
11 files changed, 29 insertions(+), 67 deletions(-)
create mode 100644 drivers/gpu/drm/i915/.gitignore
create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
diff --git a/drivers/gpu/drm/i915/.gitignore b/drivers/gpu/drm/i915/.gitignore
new file mode 100644
index ..cff45d81f42f
--- /dev/null
+++ b/drivers/gpu/drm/i915/.gitignore
@@ -0,0 +1 @@
+header_test_*.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 30bf3301ea24..91eaccca4f4f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -32,6 +32,11 @@ CFLAGS_intel_fbdev.o = $(call cc-disable-warning,
override-init)
subdir-ccflags-y += \
$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
+# Extra header tests
+ifeq ($(CONFIG_DRM_I915_WERROR),y)
+include $(src)/Makefile.header-test
+endif
+
# Please keep these build lists sorted!
# core driver code
@@ -57,17 +62,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
-# Test the headers are compilable as standalone units
-i915-$(CONFIG_DRM_I915_WERROR) += \
- test_i915_active_types_standalone.o \
- test_i915_gem_context_types_standalone.o \
- test_i915_priolist_types_standalone.o \
- test_i915_scheduler_types_standalone.o \
- test_i915_timeline_types_standalone.o \
- test_intel_context_types_standalone.o \
- test_intel_engine_types_standalone.o \
- test_intel_workarounds_types_standalone.o
-
# GEM code
i915-y += \
i915_active.o \
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
new file mode 100644
index ..0d5fa8443a08
--- /dev/null
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: MIT
+# Copyright © 2019 Intel Corporation
+
+# Test the headers are compilable as standalone units
+header_test := \
+ i915_active_types.h \
+ i915_gem_context_types.h \
+ i915_priolist_types.h \
+ i915_scheduler_types.h \
+ i915_timeline_types.h \
+ intel_context_types.h \
+ intel_engine_types.h \
+ intel_workarounds_types.h
+
+quiet_cmd_header_test = HDRTEST$@
+ cmd_header_test = echo "\#include \"$( $@
+
+header_test_%.c: %.h
+ $(call cmd,header_test)
+
+extra-y += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
+
+clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))
diff --git a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
b/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
deleted file mode 100644
index 144ebd153e57..
--- a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * SPDX-License-Identifier: MIT
- *
- * Copyright © 2019 Intel Corporation
- */
-
-#include "i915_active_types.h"
diff --git a/drivers/gpu/drm/i915/test_i915_gem_context_types_standal
[Intel-gfx] [PATCH 2/2] drm/i915: Move GraphicsTechnology files under gt/
Start partitioning off the code that talks to the hardware (GT) from the
uapi layers and move the device facing code under gt/
One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to
subdivide that header and body further (and split out the submission
code from the ringbuffer and logical context handling). This patch aims
to be simple motion so git can fixup inflight patches with little mess.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 23 ---
drivers/gpu/drm/i915/Makefile.header-test | 5 +---
drivers/gpu/drm/i915/gt/Makefile | 4
drivers/gpu/drm/i915/gt/Makefile.header-test | 15
.../gpu/drm/i915/{ => gt}/intel_breadcrumbs.c | 0
drivers/gpu/drm/i915/{ => gt}/intel_context.c | 5 ++--
drivers/gpu/drm/i915/{ => gt}/intel_context.h | 0
.../drm/i915/{ => gt}/intel_context_types.h | 0
.../{intel_ringbuffer.h => gt/intel_engine.h} | 3 ++-
.../gpu/drm/i915/{ => gt}/intel_engine_cs.c | 7 +++---
.../drm/i915/{ => gt}/intel_engine_types.h| 14 ++-
.../drm/i915/{ => gt}/intel_gpu_commands.h| 0
drivers/gpu/drm/i915/{ => gt}/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/{ => gt}/intel_lrc.h | 5 ++--
drivers/gpu/drm/i915/{ => gt}/intel_lrc_reg.h | 0
drivers/gpu/drm/i915/{ => gt}/intel_mocs.c| 4 +++-
drivers/gpu/drm/i915/{ => gt}/intel_mocs.h| 4 +++-
.../gpu/drm/i915/{ => gt}/intel_ringbuffer.c | 0
.../gpu/drm/i915/{ => gt}/intel_workarounds.c | 0
.../gpu/drm/i915/{ => gt}/intel_workarounds.h | 8 +--
.../i915/{ => gt}/intel_workarounds_types.h | 2 +-
.../drm/i915/{selftests => gt}/mock_engine.c | 2 +-
.../drm/i915/{selftests => gt}/mock_engine.h | 2 +-
.../selftest_engine_cs.c} | 0
drivers/gpu/drm/i915/i915_cmd_parser.c| 3 ++-
drivers/gpu/drm/i915/i915_drv.c | 3 ++-
drivers/gpu/drm/i915/i915_drv.h | 21 -
drivers/gpu/drm/i915/i915_gem.c | 5 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 7 --
drivers/gpu/drm/i915/i915_gem_context.h | 3 ++-
drivers/gpu/drm/i915/i915_gem_context_types.h | 3 ++-
drivers/gpu/drm/i915/i915_gpu_error.h | 3 ++-
drivers/gpu/drm/i915/i915_perf.c | 3 ++-
drivers/gpu/drm/i915/i915_pmu.c | 4 +++-
drivers/gpu/drm/i915/i915_reset.h | 2 +-
drivers/gpu/drm/i915/i915_scheduler_types.h | 2 +-
drivers/gpu/drm/i915/i915_trace.h | 3 ++-
drivers/gpu/drm/i915/i915_vma.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 17 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 3 ++-
drivers/gpu/drm/i915/intel_guc_submission.h | 3 ++-
.../gpu/drm/i915/selftests/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/selftests/igt_reset.c| 3 ++-
drivers/gpu/drm/i915/selftests/igt_spinner.h | 3 ++-
.../gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
drivers/gpu/drm/i915/selftests/mock_request.c | 3 ++-
46 files changed, 133 insertions(+), 76 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/Makefile
create mode 100644 drivers/gpu/drm/i915/gt/Makefile.header-test
rename drivers/gpu/drm/i915/{ => gt}/intel_breadcrumbs.c (100%)
rename drivers/gpu/drm/i915/{ => gt}/intel_context.c (98%)
rename drivers/gpu/drm/i915/{ => gt}/intel_context.h (100%)
rename drivers/gpu/drm/i915/{ => gt}/intel_context_types.h (100%)
rename drivers/gpu/drm/i915/{intel_ringbuffer.h => gt/intel_engine.h} (99%)
rename drivers/gpu/drm/i915/{ => gt}/intel_engine_cs.c (99%)
rename drivers/gpu/drm/i915/{ => gt}/intel_engine_types.h (98%)
rename drivers/gpu/drm/i915/{ => gt}/intel_gpu_commands.h (100%)
rename drivers/gpu/drm/i915/{ => gt}/intel_lrc.c (99%)
rename drivers/gpu/drm/i915/{ => gt}/intel_lrc.h (98%)
rename drivers/gpu/drm/i915/{ => gt}/intel_lrc_reg.h (100%)
rename drivers/gpu/drm/i915/{ => gt}/intel_mocs.c (99%)
rename drivers/gpu/drm/i915/{ => gt}/intel_mocs.h (97%)
rename drivers/gpu/drm/i915/{ => gt}/intel_ringbuffer.c (100%)
rename drivers/gpu/drm/i915/{ => gt}/intel_workarounds.c (100%)
rename drivers/gpu/drm/i915/{ => gt}/intel_workarounds.h (87%)
rename drivers/gpu/drm/i915/{ => gt}/intel_workarounds_types.h (94%)
rename drivers/gpu/drm/i915/{selftests => gt}/mock_engine.c (99%)
rename drivers/gpu/drm/i915/{selftests => gt}/mock_engine.h (98%)
rename drivers/gpu/drm/i915/{selftests/intel_engine_cs.c =>
gt/selftest_engine_cs.c} (100%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 91eaccca4f4f..f414b211063d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -37,6 +37,8 @@ ifeq ($(CONFIG_DRM_I915_WERROR),y)
include $(src)/Makefile.header-test
endif
+subdir-ccflags-y += -I$(src)
+
# Please keep these build lists sorted!
# core driver code
@@ -55,13 +57,24 @@ i915-y := i915_drv.o \
intel_csr.o \
intel_d
Re: [Intel-gfx] [PATCH] drm/i915: FBC needs vblank before enable / disable.
On Wed, 2019-04-03 at 10:00 +0530, kiran.s.ku...@intel.com wrote:
> From: Kiran Kumar S
>
> As per the display workaround #1200, FBC needs wait for vblank before
> enabling and before disabling FBC.
>
> In some cases, depending on whether FBC was compressing in that
> frame,
> several control signals in the compression engine also will fail to
> properly
> recognize the final segment of the frame as a result of the missing
> last
> pixel indication. As a result of this, we're seeing corrupted cache
> line/compression indicators after FBC re-enables which causes
> underruns or
> corruption when they're used to decompress.
>
> WA sequence as below:
> 1) Display enables plane 1A
> 2) Wait for 1 vblank
> 3) FBC gets enabled
> 4) Wait for 1 VBLANK
> 5) Turn off FBC
>
> In GLK Chrome OS, if FBC is enabled by default, few top lines on the
> screen
> got corrupted. With the above WA, issue was resolved.
>
> Change-Id: I2465610bb0a82df99e5c53b1eb4ed74565996b1e
> Signed-off-by: Kiran Kumar S <
> kiran.s.ku...@intel.corp-partner.google.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8576a7f799f2..5118a36782eb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13207,8 +13207,11 @@ static void intel_update_crtc(struct
> drm_crtc *crtc,
>
> if (pipe_config->update_pipe && !pipe_config->enable_fbc)
> intel_fbc_disable(intel_crtc);
> - else if (new_plane_state)
> + else if (new_plane_state) {
> + /* Display WA #1200: GLK */
> + intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
Wait a vblank of partially changed state? That is not a good idea at
all.
Also it would wait a vblank even if FBC is not enabled.
> intel_fbc_enable(intel_crtc, pipe_config,
> new_plane_state);
> + }
>
> intel_begin_crtc_commit(crtc, old_crtc_state);
>
> @@ -13419,6 +13422,8 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
>
> dev_priv-
> >display.crtc_disable(old_intel_crtc_state, state);
> intel_crtc->active = false;
> + /* Display WA #1200: GLK */
> + intel_wait_for_vblank(dev_priv, intel_crtc-
> >pipe);
> intel_fbc_disable(intel_crtc);
> intel_disable_shared_dpll(old_intel_crtc_state)
> ;
>
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: use unsigned long for platform_mask (rev2)
== Series Details == Series: drm/i915: use unsigned long for platform_mask (rev2) URL : https://patchwork.freedesktop.org/series/58895/ State : success == Summary == CI Bug Log - changes from CI_DRM_5858_full -> Patchwork_12663_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12663_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@readonly-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_params@no-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_exec_params@no-bsd: - shard-apl: NOTRUN -> SKIP [fdo#109271] +11 * igt@gem_exec_parse@basic-allowed: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_stolen@stolen-clear: - shard-glk: NOTRUN -> SKIP [fdo#109271] +22 * igt@gem_stolen@stolen-no-mmap: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +2 * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@kms_atomic_transition@6x-modeset-transitions: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +4 * igt@kms_busy@extended-modeset-hang-newfb-render-d: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-pageflip-hang-newfb-render-d: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-planes-random: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_cursor_crc@cursor-64x64-onscreen: - shard-snb: PASS -> SKIP [fdo#109271] +3 * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] +1 * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +3 * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible: - shard-skl: NOTRUN -> SKIP [fdo#109271] +95 * igt@kms_force_connector_basic@force-connector-state: - shard-iclb: NOTRUN -> SKIP [fdo#109285] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: - shard-iclb: PASS -> FAIL [fdo#103167] +10 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +12 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#109247] +23 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render: - shard-iclb: NOTRUN -> FAIL [fdo#109247] * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc: - shard-snb: NOTRUN -> SKIP [fdo#109271] +46 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9 * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_plane_scaling@pipe-a-scaler-with-rotation: - shard-iclb: NOTRUN -> FAIL [fdo#109052] * igt@kms_psr2_su@frontbuffer: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: PASS -> SKIP [fdo#109441] * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: NOTRUN -> SKIP [fdo#109441] * igt@kms_psr@sprite_mmap_cpu: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +2 * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: PASS -> FAIL [fdo#109016] * igt@kms_setmode@basic: - shard-iclb: NOTRUN -> FAIL [fdo#99912] * igt@kms_sysfs_edid_timing: - shard-skl: NOTRUN -> FAIL [fdo#100047] * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-skl: PASS -> FAIL [fdo#104894] * igt@prime_nv_pcopy@test_semaphore: - shard-iclb: NOTRUN -> SKIP [fdo#109291] * igt@prime_vgem@fence-flip-hang: - shard-iclb: NOTRUN -> SKIP [fdo#109295] * igt@tools_test@sysfs_l3_parity: - shard-iclb: NOTRUN -> SKIP [fdo#109307] Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - shard-iclb: FAIL [fdo#109779] -> PASS * igt@gem_ppgtt@blt-vs-render-ctxn: - shard-iclb: INCOMPLETE [fdo#109801] -> PASS * igt@gem_tiled_pread_pwrite: - shard-iclb: INCOMPLETE [fdo#109100] -> PASS * igt@gem_tiled_swapping@non-threaded: - shard-iclb: FAIL [fdo#108686] -> PASS * igt@i915_pm_rpm@cursor-dpms:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add Makefile magic for testing headers are self-contained (rev4)
== Series Details == Series: drm/i915: add Makefile magic for testing headers are self-contained (rev4) URL : https://patchwork.freedesktop.org/series/58938/ State : success == Summary == CI Bug Log - changes from CI_DRM_5863 -> Patchwork_12674 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58938/revisions/4/mbox/ Known issues Here are the changes found in Patchwork_12674 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_store@basic-bsd1: - fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41 * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1 Possible fixes * igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-byt-clapper: FAIL [fdo#107362] -> PASS [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (47 -> 39) -- Additional (1): fi-kbl-r Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus Build changes - * Linux: CI_DRM_5863 -> Patchwork_12674 CI_DRM_5863: d2c849411d8ae6de9c718b9c0cd1e00da7f0f121 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4924: bcf2f21996b2ee5c6177f5412046690ff8017772 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12674: 5f226a4e31cdc3bbb9c26c1d6d58e6a8d582b7e9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5f226a4e31cd drm/i915: add Makefile magic for testing headers are self-contained == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12674/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: add immutable zpos plane properties
From: Ville Syrjälä
This adds basic immutable support for the zpos property. The zpos increases
from bottom to top: primary, sprites, cursor.
Signed-off-by: Ville Syrjälä
[cont...@emersion.fr: adapted for latest drm-tip]
Signed-off-by: Simon Ser
---
Changes in v2: set correct author and S-o-b tags
drivers/gpu/drm/i915/intel_display.c | 10 --
drivers/gpu/drm/i915/intel_sprite.c | 5 -
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799..f0a85a75bd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14323,7 +14323,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
const u64 *modifiers;
const u32 *formats;
int num_formats;
- int ret;
+ int ret, zpos;
if (INTEL_GEN(dev_priv) >= 9)
return skl_universal_plane_create(dev_priv, pipe,
@@ -14412,6 +14412,9 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
DRM_MODE_ROTATE_0,
supported_rotations);
+ zpos = 0;
+ drm_plane_create_zpos_immutable_property(&plane->base, zpos);
+
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
return plane;
@@ -14428,7 +14431,7 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv,
{
unsigned int possible_crtcs;
struct intel_plane *cursor;
- int ret;
+ int ret, zpos;
cursor = intel_plane_alloc();
if (IS_ERR(cursor))
@@ -14477,6 +14480,9 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv,
DRM_MODE_ROTATE_0 |
DRM_MODE_ROTATE_180);
+ zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
+ drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
+
drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
return cursor;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 65de7387bf..48bd8f9079 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -2354,7 +2354,7 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
const u64 *modifiers;
const u32 *formats;
int num_formats;
- int ret;
+ int ret, zpos;
if (INTEL_GEN(dev_priv) >= 9)
return skl_universal_plane_create(dev_priv, pipe,
@@ -2444,6 +2444,9 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
+ zpos = sprite + 1;
+ drm_plane_create_zpos_immutable_property(&plane->base, zpos);
+
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
return plane;
--
2.21.0
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
On Thu, Mar 21, 2019 at 05:56:39PM +0200, Imre Deak wrote: > On Thu, Mar 21, 2019 at 12:32:47AM +, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on > > glk/cnl when audio power is enabled > > URL : https://patchwork.freedesktop.org/series/58273/ > > State : failure Thanks for the patches and reviews, pushed to -dinq. > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_5781_full -> Patchwork_12531_full > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_12531_full absolutely need > > to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_12531_full, please notify your bug team to allow > > them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_12531_full: > > > > ### IGT changes ### > > > > Possible regressions > > > > * igt@kms_properties@connector-properties-atomic: > > - shard-iclb: PASS -> FAIL > > (kms_properties:4576) DEBUG: Testing property "max bpc" > > with the 'max bpc' property set to 6. > > This results in the driver failing the modeset with: > > <7>[ 2131.233688] [drm:intel_dp_compute_config [i915]] Force DSC en = 1 > <7>[ 2131.233716] [drm:intel_dp_compute_config [i915]] No DSC support for > less than 8bpc > <7>[ 2131.233747] [drm:intel_atomic_check [i915]] Encoder config failure: -22 > > which is in turn caused by an earlier failure in > igt@kms_dp_dsc@basic-dsc-enable-eDP: > > (kms_dp_dsc:3075) CRITICAL: Test assertion failure function update_display, > file ../tests/kms_dp_dsc.c:182: > (kms_dp_dsc:3075) CRITICAL: Failed assertion: is_dp_dsc_enabled(data) > > That one in turn is caused by an incorrect assumption by kms_dp_dsc in > that the DSC compression will only get enabled via a full modeset, while > the test does only a fastset. The test also fails to restore the > original value to the i915_dsc_fec_support debugfs file during an assert > failure, leading to kms_properties seeing the unxepcted > intel_dp->force_dsc_en=true value. > > Adding Manasi to look at the kms_dp_dsc fail. > > > > > > > Known issues > > > > > > Here are the changes found in Patchwork_12531_full that come from known > > issues: > > > > ### IGT changes ### > > > > Issues hit > > > > * igt@gem_exec_parse@batch-without-end: > > - shard-iclb: NOTRUN -> SKIP [fdo#109289] > > > > * igt@gem_exec_suspend@basic-s3: > > - shard-apl: PASS -> INCOMPLETE [fdo#103927] > > > > * igt@gem_pwrite@stolen-normal: > > - shard-skl: NOTRUN -> SKIP [fdo#109271] +117 > > > > * igt@i915_pm_rpm@gem-execbuf-stress: > > - shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] > > > > * igt@i915_pm_rpm@i2c: > > - shard-skl: PASS -> INCOMPLETE [fdo#107807] +1 > > > > * igt@i915_selftest@live_workarounds: > > - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] > > > > * igt@kms_atomic_transition@1x-modeset-transitions-fencing: > > - shard-snb: PASS -> SKIP [fdo#109271] +4 > > > > * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: > > - shard-apl: PASS -> FAIL [fdo#109660] > > > > * igt@kms_atomic_transition@5x-modeset-transitions-nonblocking: > > - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13 > > > > * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: > > - shard-kbl: PASS -> DMESG-WARN [fdo#107956] > > > > * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-d: > > - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3 > > > > * igt@kms_busy@extended-modeset-hang-oldfb-render-e: > > - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 > > > > * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: > > - shard-glk: PASS -> DMESG-WARN [fdo#107956] > > - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] > > > > * igt@kms_color@pipe-a-gamma: > > - shard-skl: PASS -> FAIL [fdo#104782] > > > > * igt@kms_cursor_crc@cursor-256x256-suspend: > > - shard-snb: PASS -> DMESG-WARN [fdo#102365] > > > > * igt@kms_cursor_legacy@cursor-vs-flip-atomic: > > - shard-iclb: PASS -> FAIL [fdo#103355] > > > > * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset: > > - shard-iclb: NOTRUN -> SKIP [fdo#109274] > > > > * igt@kms_flip@flip-vs-expired-vblank-interruptible: > > - shard-apl: PASS -> FAIL [fdo#102887] / [fdo#105363] > > > > * igt@kms_frontbuffer_tracking@fbc-rgb5
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add Makefile magic for testing headers are self-contained (rev4)
== Series Details == Series: drm/i915: add Makefile magic for testing headers are self-contained (rev4) URL : https://patchwork.freedesktop.org/series/58938/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: add Makefile magic for testing headers are self-contained -./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) -./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) -./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) + ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add Makefile magic for testing headers are self-contained (rev4)
== Series Details ==
Series: drm/i915: add Makefile magic for testing headers are self-contained
(rev4)
URL : https://patchwork.freedesktop.org/series/58938/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5f226a4e31cd drm/i915: add Makefile magic for testing headers are self-contained
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 39e2f501c1b4 ("drm/i915: Split
struct intel_context definition to its own header")'
#10:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3a891a626794 ("drm/i915: Move
intel_engine_mask_t around for use by i915_request_types.h")'
#11:
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 8b74594aa455 ("drm/i915: Split
out i915_priolist_types into its own header")'
#12:
8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
-:38: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#38:
new file mode 100644
total: 3 errors, 2 warnings, 0 checks, 55 lines checked
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Re: [Intel-gfx] [PATCH v4] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
Hi Aditya,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190403]
[cannot apply to v5.1-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Aditya-Swarup/drm-i915-icl-Set-GCP_COLOR_INDICATION-only-for-10-12-bit-deep-color/20190403-201049
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-8) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/gpu//drm/i915/intel_hdmi.c: In function
'intel_hdmi_compute_gcp_infoframe':
>> drivers/gpu//drm/i915/intel_hdmi.c:970:6: error: expected ')' before
>> 'crtc_state'
crtc_state->pipe_bpp > 24)
^~
vim +970 drivers/gpu//drm/i915/intel_hdmi.c
952
953 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder
*encoder,
954 struct intel_crtc_state
*crtc_state,
955 struct drm_connector_state
*conn_state)
956 {
957 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
958
959 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
960 return;
961
962 crtc_state->infoframes.enable |=
963
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
964
965 /* Indicate color depth whenever the sink supports deep color
966 * Also, 8bpc + color depth indication is no longer supported
967 * for HSW+ platforms.
968 * */
969 if (hdmi_sink_is_deep_color(conn_state)
> 970 crtc_state->pipe_bpp > 24)
971 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
972
973 /* Enable default_phase whenever the display mode is suitably
aligned */
974 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
975 &crtc_state->base.adjusted_mode))
976 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
977 }
978
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
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Re: [Intel-gfx] [PATCH v2 0/7] drm/i915: Finish the GAMMA_LUT stuff
>-Original Message- >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, April 2, 2019 1:32 AM >To: intel-gfx@lists.freedesktop.org >Cc: Shankar, Uma ; Roper, Matthew D > >Subject: [PATCH v2 0/7] drm/i915: Finish the GAMMA_LUT stuff > >From: Ville Syrjälä > >Rebased due to Uma's EXT_GC_MAX fix, and I added Matt's proposed behavioural >change (expose 1024 entry LUTs in split gamma mode and just discard half the >entries) as an extra patch on top. > >Everything is reviewed except patches 2 and 7. Reviewed the whole series and it looks perfect. Reviewed-by: Uma Shankar > >Ville Syrjälä (7): > drm/i915: Extract ilk_lut_10() > drm/i915: Don't use split gamma when we don't have to > drm/i915: Implement split/10bit gamma for ivb/hsw > drm/i915: Add 10bit LUT for ilk/snb > drm/i915: Add "10.6" LUT mode for i965+ > drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props >on gen2/3 > drm/i915: Expose full 1024 LUT entries on ivb+ > > drivers/gpu/drm/i915/i915_pci.c| 23 +- > drivers/gpu/drm/i915/i915_reg.h| 15 ++ > drivers/gpu/drm/i915/intel_color.c | 375 - > 3 files changed, 292 insertions(+), 121 deletions(-) > >-- >2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: Expose full 1024 LUT entries on ivb+
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, April 2, 2019 1:33 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma ; Roper, Matthew D
>
>Subject: [PATCH v2 7/7] drm/i915: Expose full 1024 LUT entries on ivb+
>
>From: Ville Syrjälä
>
>On ivb+ we can select between the regular 10bit LUT mode with
>1024 entries, and the split mode where the LUT is split into seprate degamma
>and
>gamma halves (each with 512 entries). Currently we expose the split gamma size
>of
>512 as the GAMMA/DEGAMMA_LUT_SIZE.
>
>When using only degamma or gamma (not both) we are wasting half of the hardware
>LUT entries. Let's flip that around so that we expose the full 1024 entries
>and just
>throw away half of the user provided entries when using the split gamma mode.
Changes look good to me.
Reviewed-by: Uma Shankar
>Cc: Matt Roper
>Suggested-by: Matt Roper
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/i915_pci.c| 2 +-
> drivers/gpu/drm/i915/intel_color.c | 75 +-
> 2 files changed, 34 insertions(+), 43 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index
>81d14dc2fa61..6ffb85ddac53 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -125,7 +125,7 @@
> #define ILK_COLORS \
> .color = { .gamma_lut_size = 1024 }
> #define IVB_COLORS \
>- .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
>+ .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> #define CHV_COLORS \
> .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
> .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index faebd0705adb..60f21a1fdbbe 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -538,6 +538,14 @@ static void ilk_load_luts(const struct intel_crtc_state
>*crtc_state)
> ilk_load_lut_10(crtc, gamma_lut);
> }
>
>+static int ivb_lut_10_size(u32 prec_index) {
>+ if (prec_index & PAL_PREC_SPLIT_MODE)
>+ return 512;
>+ else
>+ return 1024;
>+}
>+
> /*
> * IVB/HSW Bspec / PAL_PREC_INDEX:
> * "Restriction : Index auto increment mode is not @@ -545,31 +553,21 @@
> static
>void ilk_load_luts(const struct intel_crtc_state *crtc_state)
> */
> static void ivb_load_lut_10(struct intel_crtc *crtc,
> const struct drm_property_blob *blob,
>- u32 prec_index, bool duplicate)
>+ u32 prec_index)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+ int hw_lut_size = ivb_lut_10_size(prec_index);
> const struct drm_color_lut *lut = blob->data;
> int i, lut_size = drm_color_lut_size(blob);
> enum pipe pipe = crtc->pipe;
>
>- /*
>- * We advertize the split gamma sizes. When not using split
>- * gamma we just duplicate each entry.
>- *
>- * TODO: expose the full LUT to userspace
>- */
>- if (duplicate) {
>- for (i = 0; i < lut_size; i++) {
>- I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
>- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>- I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
>- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>- }
>- } else {
>- for (i = 0; i < lut_size; i++) {
>- I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
>- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>- }
>+ for (i = 0; i < hw_lut_size; i++) {
>+ /* We discard half the user entries in split gamma mode */
>+ const struct drm_color_lut *entry =
>+ &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
>+
>+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
>+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry));
> }
>
> /*
>@@ -582,9 +580,10 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
> /* On BDW+ the index auto increment mode actually works */ static void
>bdw_load_lut_10(struct intel_crtc *crtc,
> const struct drm_property_blob *blob,
>- u32 prec_index, bool duplicate)
>+ u32 prec_index)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+ int hw_lut_size = ivb_lut_10_size(prec_index);
> const struct drm_color_lut *lut = blob->data;
> int i, lut_size = drm_color_lut_size(blob);
> enum pipe pipe = crtc->pipe;
>@@ -592,20 +591,12 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
> PAL_PREC_AUTO_INCREMENT);
>
>-
Re: [Intel-gfx] [PATCH v3] drm/i915: add Makefile magic for testing headers are self-contained
On Wed, 03 Apr 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-04-03 14:32:36)
>> The below commits added dummy files to test that certain headers are
>> self-contained, i.e. compilable as standalone units:
>>
>> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
>> header")
>> 3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
>> i915_request_types.h")
>> 8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
>>
>> The idea is fine, but the implementation is a bit tedious and
>> inflexible, and does not really scale well.
>>
>> Implement the same in make using autogenerated dummy sources to include
>> the headers.
>>
>> v2 by Chris:
>> - Use patsubst
>> - Add .gitignore
>> - Add clean-files for generated dummy sources
>>
>> v3 by Jani:
>> - Fix make clean
>> - Add the tests to i915-y instead of extra-y
>>
>> Cc: Chris Wilson
>> Cc: Tvrtko Ursulin
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/.gitignore | 1 +
>> drivers/gpu/drm/i915/Makefile | 16 -
>> drivers/gpu/drm/i915/Makefile.header-test | 23 +++
>> .../i915/test_i915_active_types_standalone.c | 7 --
>> .../test_i915_gem_context_types_standalone.c | 7 --
>> .../test_i915_priolist_types_standalone.c | 7 --
>> .../test_i915_scheduler_types_standalone.c| 7 --
>> .../test_i915_timeline_types_standalone.c | 7 --
>> .../test_intel_context_types_standalone.c | 7 --
>> .../i915/test_intel_engine_types_standalone.c | 7 --
>> .../test_intel_workarounds_types_standalone.c | 7 --
>> 11 files changed, 28 insertions(+), 68 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/.gitignore
>> create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
>> delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
>> delete mode 100644
>> drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
>> delete mode 100644
>> drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
>> delete mode 100644
>> drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
>> delete mode 100644
>> drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
>> delete mode 100644
>> drivers/gpu/drm/i915/test_intel_context_types_standalone.c
>> delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
>> delete mode 100644
>> drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
>>
>> diff --git a/drivers/gpu/drm/i915/.gitignore
>> b/drivers/gpu/drm/i915/.gitignore
>> new file mode 100644
>> index 00..cff45d
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/.gitignore
>> @@ -0,0 +1 @@
>> +header_test_*.c
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index 30bf33..fbcb0904 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -32,10 +32,13 @@ CFLAGS_intel_fbdev.o = $(call cc-disable-warning,
>> override-init)
>> subdir-ccflags-y += \
>> $(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
>>
>> +# Extra header tests
>> +include $(src)/Makefile.header-test
>> +
>> # Please keep these build lists sorted!
>>
>> # core driver code
>> -i915-y := i915_drv.o \
>> +i915-y += i915_drv.o \
>> i915_irq.o \
>> i915_memcpy.o \
>> i915_mm.o \
>> @@ -57,17 +60,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
>> i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
>> i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
>>
>> -# Test the headers are compilable as standalone units
>> -i915-$(CONFIG_DRM_I915_WERROR) += \
>> - test_i915_active_types_standalone.o \
>> - test_i915_gem_context_types_standalone.o \
>> - test_i915_priolist_types_standalone.o \
>> - test_i915_scheduler_types_standalone.o \
>> - test_i915_timeline_types_standalone.o \
>> - test_intel_context_types_standalone.o \
>> - test_intel_engine_types_standalone.o \
>> - test_intel_workarounds_types_standalone.o
>> -
>> # GEM code
>> i915-y += \
>> i915_active.o \
>> diff --git a/drivers/gpu/drm/i915/Makefile.header-test
>> b/drivers/gpu/drm/i915/Makefile.header-test
>> new file mode 100644
>> index 00..e984cf
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/Makefile.header-test
>> @@ -0,0 +1,23 @@
>> +# SPDX-License-Identifier: MIT
>> +# Copyright © 2019 Intel Corporation
>> +
>> +# Test the headers are compilable as standalone units
>> +header_test := \
>> + i915_active_types.h \
>> + i915_gem_context_types.h \
>> + i915_priolist_types.h \
>> + i915_scheduler_types.h \
>> + i915_timeline_types.h \
>> + intel_context_types.h \
>> + intel_engine_types.h \
>> + intel_workarounds_types.h
>> +
>> +quiet_cmd_header_test = HDRTEST$@
>
> Did you look at the output alignment? v1 needed a bit of a tweak to look
> g
[Intel-gfx] [PATCH v4] drm/i915: add Makefile magic for testing headers are self-contained
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
The idea is fine, but the implementation is a bit tedious and
inflexible, and does not really scale well.
Implement the same in make using autogenerated dummy sources to include
the headers.
v2 by Chris:
- Use patsubst
- Add .gitignore
- Add clean-files for generated dummy sources
v3 by Jani:
- Fix make clean
- Add the tests to i915-y instead of extra-y
v4 by Jani:
- quiet_cmd whitespace fix
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/.gitignore | 1 +
drivers/gpu/drm/i915/Makefile | 16 -
drivers/gpu/drm/i915/Makefile.header-test | 23 +++
.../i915/test_i915_active_types_standalone.c | 7 --
.../test_i915_gem_context_types_standalone.c | 7 --
.../test_i915_priolist_types_standalone.c | 7 --
.../test_i915_scheduler_types_standalone.c| 7 --
.../test_i915_timeline_types_standalone.c | 7 --
.../test_intel_context_types_standalone.c | 7 --
.../i915/test_intel_engine_types_standalone.c | 7 --
.../test_intel_workarounds_types_standalone.c | 7 --
11 files changed, 28 insertions(+), 68 deletions(-)
create mode 100644 drivers/gpu/drm/i915/.gitignore
create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
diff --git a/drivers/gpu/drm/i915/.gitignore b/drivers/gpu/drm/i915/.gitignore
new file mode 100644
index 00..cff45d
--- /dev/null
+++ b/drivers/gpu/drm/i915/.gitignore
@@ -0,0 +1 @@
+header_test_*.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 30bf33..fbcb0904 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -32,10 +32,13 @@ CFLAGS_intel_fbdev.o = $(call cc-disable-warning,
override-init)
subdir-ccflags-y += \
$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
+# Extra header tests
+include $(src)/Makefile.header-test
+
# Please keep these build lists sorted!
# core driver code
-i915-y := i915_drv.o \
+i915-y += i915_drv.o \
i915_irq.o \
i915_memcpy.o \
i915_mm.o \
@@ -57,17 +60,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
-# Test the headers are compilable as standalone units
-i915-$(CONFIG_DRM_I915_WERROR) += \
- test_i915_active_types_standalone.o \
- test_i915_gem_context_types_standalone.o \
- test_i915_priolist_types_standalone.o \
- test_i915_scheduler_types_standalone.o \
- test_i915_timeline_types_standalone.o \
- test_intel_context_types_standalone.o \
- test_intel_engine_types_standalone.o \
- test_intel_workarounds_types_standalone.o
-
# GEM code
i915-y += \
i915_active.o \
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
new file mode 100644
index 00..f7809b
--- /dev/null
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: MIT
+# Copyright © 2019 Intel Corporation
+
+# Test the headers are compilable as standalone units
+header_test := \
+ i915_active_types.h \
+ i915_gem_context_types.h \
+ i915_priolist_types.h \
+ i915_scheduler_types.h \
+ i915_timeline_types.h \
+ intel_context_types.h \
+ intel_engine_types.h \
+ intel_workarounds_types.h
+
+quiet_cmd_header_test = HDRTEST $@
+ cmd_header_test = echo "\#include \"$( $@
+
+header_test_%.c: %.h
+ $(call cmd,header_test)
+
+i915-$(CONFIG_DRM_I915_WERROR) += $(foreach h,$(header_test),$(patsubst
%.h,header_test_%.o,$(h)))
+
+clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))
diff --git a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
b/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
deleted file mode 100644
index 144ebd..00
--- a/drivers/gpu/d
Re: [Intel-gfx] [PATCH v3] drm/i915: add Makefile magic for testing headers are self-contained
Quoting Jani Nikula (2019-04-03 14:32:36)
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
> i915_request_types.h")
> 8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
>
> The idea is fine, but the implementation is a bit tedious and
> inflexible, and does not really scale well.
>
> Implement the same in make using autogenerated dummy sources to include
> the headers.
>
> v2 by Chris:
> - Use patsubst
> - Add .gitignore
> - Add clean-files for generated dummy sources
>
> v3 by Jani:
> - Fix make clean
> - Add the tests to i915-y instead of extra-y
>
> Cc: Chris Wilson
> Cc: Tvrtko Ursulin
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/.gitignore | 1 +
> drivers/gpu/drm/i915/Makefile | 16 -
> drivers/gpu/drm/i915/Makefile.header-test | 23 +++
> .../i915/test_i915_active_types_standalone.c | 7 --
> .../test_i915_gem_context_types_standalone.c | 7 --
> .../test_i915_priolist_types_standalone.c | 7 --
> .../test_i915_scheduler_types_standalone.c| 7 --
> .../test_i915_timeline_types_standalone.c | 7 --
> .../test_intel_context_types_standalone.c | 7 --
> .../i915/test_intel_engine_types_standalone.c | 7 --
> .../test_intel_workarounds_types_standalone.c | 7 --
> 11 files changed, 28 insertions(+), 68 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/.gitignore
> create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
> delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_intel_context_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
>
> diff --git a/drivers/gpu/drm/i915/.gitignore b/drivers/gpu/drm/i915/.gitignore
> new file mode 100644
> index 00..cff45d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/.gitignore
> @@ -0,0 +1 @@
> +header_test_*.c
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 30bf33..fbcb0904 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -32,10 +32,13 @@ CFLAGS_intel_fbdev.o = $(call cc-disable-warning,
> override-init)
> subdir-ccflags-y += \
> $(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
>
> +# Extra header tests
> +include $(src)/Makefile.header-test
> +
> # Please keep these build lists sorted!
>
> # core driver code
> -i915-y := i915_drv.o \
> +i915-y += i915_drv.o \
> i915_irq.o \
> i915_memcpy.o \
> i915_mm.o \
> @@ -57,17 +60,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
> i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
> i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
>
> -# Test the headers are compilable as standalone units
> -i915-$(CONFIG_DRM_I915_WERROR) += \
> - test_i915_active_types_standalone.o \
> - test_i915_gem_context_types_standalone.o \
> - test_i915_priolist_types_standalone.o \
> - test_i915_scheduler_types_standalone.o \
> - test_i915_timeline_types_standalone.o \
> - test_intel_context_types_standalone.o \
> - test_intel_engine_types_standalone.o \
> - test_intel_workarounds_types_standalone.o
> -
> # GEM code
> i915-y += \
> i915_active.o \
> diff --git a/drivers/gpu/drm/i915/Makefile.header-test
> b/drivers/gpu/drm/i915/Makefile.header-test
> new file mode 100644
> index 00..e984cf
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/Makefile.header-test
> @@ -0,0 +1,23 @@
> +# SPDX-License-Identifier: MIT
> +# Copyright © 2019 Intel Corporation
> +
> +# Test the headers are compilable as standalone units
> +header_test := \
> + i915_active_types.h \
> + i915_gem_context_types.h \
> + i915_priolist_types.h \
> + i915_scheduler_types.h \
> + i915_timeline_types.h \
> + intel_context_types.h \
> + intel_engine_types.h \
> + intel_workarounds_types.h
> +
> +quiet_cmd_header_test = HDRTEST$@
Did you look at the output alignment? v1 needed a bit of a tweak to look
good here.
> + cmd_header_test = echo "\#include \"$( $@
> +
> +header_test_%.c: %.h
> + $(call cmd,header_test)
> +
> +i915-$(CONFIG_DRM_I915_WERROR) += $(foreach h,$(header_
[Intel-gfx] [PATCH v3] drm/i915: add Makefile magic for testing headers are self-contained
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
The idea is fine, but the implementation is a bit tedious and
inflexible, and does not really scale well.
Implement the same in make using autogenerated dummy sources to include
the headers.
v2 by Chris:
- Use patsubst
- Add .gitignore
- Add clean-files for generated dummy sources
v3 by Jani:
- Fix make clean
- Add the tests to i915-y instead of extra-y
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/.gitignore | 1 +
drivers/gpu/drm/i915/Makefile | 16 -
drivers/gpu/drm/i915/Makefile.header-test | 23 +++
.../i915/test_i915_active_types_standalone.c | 7 --
.../test_i915_gem_context_types_standalone.c | 7 --
.../test_i915_priolist_types_standalone.c | 7 --
.../test_i915_scheduler_types_standalone.c| 7 --
.../test_i915_timeline_types_standalone.c | 7 --
.../test_intel_context_types_standalone.c | 7 --
.../i915/test_intel_engine_types_standalone.c | 7 --
.../test_intel_workarounds_types_standalone.c | 7 --
11 files changed, 28 insertions(+), 68 deletions(-)
create mode 100644 drivers/gpu/drm/i915/.gitignore
create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
diff --git a/drivers/gpu/drm/i915/.gitignore b/drivers/gpu/drm/i915/.gitignore
new file mode 100644
index 00..cff45d
--- /dev/null
+++ b/drivers/gpu/drm/i915/.gitignore
@@ -0,0 +1 @@
+header_test_*.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 30bf33..fbcb0904 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -32,10 +32,13 @@ CFLAGS_intel_fbdev.o = $(call cc-disable-warning,
override-init)
subdir-ccflags-y += \
$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
+# Extra header tests
+include $(src)/Makefile.header-test
+
# Please keep these build lists sorted!
# core driver code
-i915-y := i915_drv.o \
+i915-y += i915_drv.o \
i915_irq.o \
i915_memcpy.o \
i915_mm.o \
@@ -57,17 +60,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
-# Test the headers are compilable as standalone units
-i915-$(CONFIG_DRM_I915_WERROR) += \
- test_i915_active_types_standalone.o \
- test_i915_gem_context_types_standalone.o \
- test_i915_priolist_types_standalone.o \
- test_i915_scheduler_types_standalone.o \
- test_i915_timeline_types_standalone.o \
- test_intel_context_types_standalone.o \
- test_intel_engine_types_standalone.o \
- test_intel_workarounds_types_standalone.o
-
# GEM code
i915-y += \
i915_active.o \
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
new file mode 100644
index 00..e984cf
--- /dev/null
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: MIT
+# Copyright © 2019 Intel Corporation
+
+# Test the headers are compilable as standalone units
+header_test := \
+ i915_active_types.h \
+ i915_gem_context_types.h \
+ i915_priolist_types.h \
+ i915_scheduler_types.h \
+ i915_timeline_types.h \
+ intel_context_types.h \
+ intel_engine_types.h \
+ intel_workarounds_types.h
+
+quiet_cmd_header_test = HDRTEST$@
+ cmd_header_test = echo "\#include \"$( $@
+
+header_test_%.c: %.h
+ $(call cmd,header_test)
+
+i915-$(CONFIG_DRM_I915_WERROR) += $(foreach h,$(header_test),$(patsubst
%.h,header_test_%.o,$(h)))
+
+clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))
diff --git a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
b/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
deleted file mode 100644
index 144ebd..00
--- a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
+++ /dev/null
@@
Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count
On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > For certain eDP 1.4 panels, we need to use max lane count for the
> > link training to succeed.
> >
> > This patch adds a EDID quirk for such eDP panels using
> > their vendor ID and product ID to force using max lane count in the driver.
>
> Rather than opening the quirk can of worms I think we should consider
> changing the retry loop to do something more sensible than what it's
> doing now. The current behaviour of "start at optimal settings (which
> can be either min lanes or min rate), and then reduce lanes/rate until
> stuff works" overlooks several possible combinations. One possible
> approach could be to start the retry loop with max lanes + max rate
> after the optimal settings have failed. It probably won't give you
> the best power consumption, but at least you get a picture on the
> screen if even a single lane count + rate combo works.
Hm yeah I guess this is an approach we haven't tried yet ... I think we've
tried everything else already.
-Daniel
>
> >
> > Cc: Clint Taylor
> > Cc: Ville Syrjälä
> > Tested-by: Albert Astals Cid
> > Tested-by: Emanuele Panigati
> > Tested-by: Ralgor
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/drm_edid.c | 10 ++
> > include/drm/drm_connector.h | 5 +
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 2c22ea446075..fbc661806484 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -82,6 +82,8 @@
> > #define EDID_QUIRK_FORCE_10BPC (1 << 11)
> > /* Non desktop display (i.e. HMD) */
> > #define EDID_QUIRK_NON_DESKTOP (1 << 12)
> > +/* Force max lane count */
> > +#define EDID_QUIRK_FORCE_MAX_LANE_COUNT(1 << 13)
> >
> > struct detailed_mode_closure {
> > struct drm_connector *connector;
> > @@ -189,6 +191,10 @@ static const struct edid_quirk {
> >
> > /* OSVR HDK and HDK2 VR Headsets */
> > { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
> > +
> > + /* SHP eDP 1.4 panel only works with max lane count */
> > + { "SHP", 0x149a, EDID_QUIRK_FORCE_MAX_LANE_COUNT },
> > + { "SHP", 0x148e, EDID_QUIRK_FORCE_MAX_LANE_COUNT },
> > };
> >
> > /*
> > @@ -4463,6 +4469,7 @@ drm_reset_display_info(struct drm_connector
> > *connector)
> > memset(&info->hdmi, 0, sizeof(info->hdmi));
> >
> > info->non_desktop = 0;
> > + info->force_max_lane_count = 0;
> > }
> >
> > u32 drm_add_display_info(struct drm_connector *connector, const struct
> > edid *edid)
> > @@ -4744,6 +4751,9 @@ int drm_add_edid_modes(struct drm_connector
> > *connector, struct edid *edid)
> > if (quirks & EDID_QUIRK_FORCE_12BPC)
> > connector->display_info.bpc = 12;
> >
> > + if (quirks & EDID_QUIRK_FORCE_MAX_LANE_COUNT)
> > + connector->display_info.force_max_lane_count = true;
> > +
> > return num_modes;
> > }
> > EXPORT_SYMBOL(drm_add_edid_modes);
> > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> > index 02a131202add..45436d40ffe3 100644
> > --- a/include/drm/drm_connector.h
> > +++ b/include/drm/drm_connector.h
> > @@ -457,6 +457,11 @@ struct drm_display_info {
> > * @non_desktop: Non desktop display (HMD).
> > */
> > bool non_desktop;
> > +
> > + /**
> > +* @force_max_lane_count: Link training requires max lane count to pass
> > +*/
> > + bool force_max_lane_count;
> > };
> >
> > int drm_display_info_set_bus_formats(struct drm_display_info *info,
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Move the decision to use the breadcrumb tasklet to the backend
On 03/04/2019 14:00, Chris Wilson wrote:
Quoting Chris Wilson (2019-03-29 15:49:12)
Use the engine->flags to store whether we want to kick the submission
tasklet on receipt of a breadcrumb interrupt, so that this decision can
be made by the submission backend and not dependent on a limited feature
test within the interrupt handler. This should make it easier to adapt
different submission backends.
This comes with a cherry on top!
add/remove: 0/1 grow/shrink: 2/2 up/down: 20/-86 (-66)
Function old new delta
guc_submission_park5 18 +13
guc_submission_unpark 5 12 +7
gen8_cs_irq_handler 97 77 -20
gen8_cs_irq_handler.cold 33 - -33
__func__ 28208 28175 -33
The function name was as large as the function itself?
Cherry on the top is just GEM_BUG_ON in intel_uc_is_using_guc_submission
I suspect. Nevertheless, patch makes sense.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
Cc: Xiaolin Zhang
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_engine_types.h | 7 +++
drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 455b2bf691b5..aa107a78cb36 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1470,7 +1470,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir)
if (iir & GT_RENDER_USER_INTERRUPT) {
intel_engine_breadcrumbs_irq(engine);
- tasklet |= USES_GUC_SUBMISSION(engine->i915);
+ tasklet |= intel_engine_needs_breadcrumb_tasklet(engine);
}
if (tasklet)
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h
b/drivers/gpu/drm/i915/intel_engine_types.h
index b3249bf6a65f..5c3f567a7a20 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -425,6 +425,7 @@ struct intel_engine_cs {
#define I915_ENGINE_SUPPORTS_STATS BIT(1)
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
+#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
unsigned int flags;
/*
@@ -508,6 +509,12 @@ intel_engine_has_semaphores(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
}
+static inline bool
+intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+}
+
#define instdone_slice_mask(dev_priv__) \
(IS_GEN(dev_priv__, 7) ? \
1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index c4ad73980988..c5896d47 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1262,10 +1262,12 @@ static void guc_interrupts_release(struct
drm_i915_private *dev_priv)
static void guc_submission_park(struct intel_engine_cs *engine)
{
intel_engine_unpin_breadcrumbs_irq(engine);
+ engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
static void guc_submission_unpark(struct intel_engine_cs *engine)
{
+ engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
intel_engine_pin_breadcrumbs_irq(engine);
}
--
2.20.1
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Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have to
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Wednesday, April 3, 2019 6:10 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D
>
>Subject: Re: [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have
>to
>
>On Wed, Apr 03, 2019 at 12:23:06PM +, Shankar, Uma wrote:
>>
>>
>> >-Original Message-
>> >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>> >Sent: Tuesday, April 2, 2019 1:32 AM
>> >To: intel-gfx@lists.freedesktop.org
>> >Cc: Shankar, Uma ; Roper, Matthew D
>> >
>> >Subject: [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't
>> >have to
>> >
>> >From: Ville Syrjälä
>> >
>> >Using the split gamma mode when we don't have to has the annoying
>> >requirement of loading a linear LUT to the unused half. Instead let's
>> >make life simpler by switching to the 10bit gamma mode and duplicating each
>entry.
>> >
>> >This also allows us to load the software gamma LUT into the hardware
>> >degamma LUT, thus removing some of the buggy configurations we
>> >currently allow (YCbCr/limited range RGB
>> >+ gamma LUT). We do still have other configurations that are
>> >also buggy, but those will need more complicated fixes or they just
>> >need to be rejected. Sadly GLK doesn't have this flexibility anymore
>> >and the degamma and gamma LUTs are very different so no help there.
>> >
>> >v2: Apply a mask when checking gamma_mode on icl since it
>> >contains more bits than just the gamma mode
>> >v3: Rebase due to EXT_GC_MAX/EXT2_GC_MAX changes
>> >
>> >Signed-off-by: Ville Syrjälä
>> >---
>> > drivers/gpu/drm/i915/i915_reg.h| 2 +
>> > drivers/gpu/drm/i915/intel_color.c | 185
>> >++---
>> > 2 files changed, 92 insertions(+), 95 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> >b/drivers/gpu/drm/i915/i915_reg.h index
>> >341f03e00536..bed2c52aebd8 100644
>> >--- a/drivers/gpu/drm/i915/i915_reg.h
>> >+++ b/drivers/gpu/drm/i915/i915_reg.h
>> >@@ -7214,6 +7214,7 @@ enum {
>> > #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
>> >_GAMMA_MODE_B)
>> > #define PRE_CSC_GAMMA_ENABLE (1 << 31)
>> > #define POST_CSC_GAMMA_ENABLE (1 << 30)
>> >+#define GAMMA_MODE_MODE_MASK (3 << 0)
>> > #define GAMMA_MODE_MODE_8BIT (0 << 0)
>> > #define GAMMA_MODE_MODE_10BIT (1 << 0)
>> > #define GAMMA_MODE_MODE_12BIT (2 << 0)
>> >@@ -10127,6 +10128,7 @@ enum skl_power_gate {
>> > #define PAL_PREC_SPLIT_MODE (1 << 31)
>> > #define PAL_PREC_AUTO_INCREMENT (1 << 15)
>> > #define PAL_PREC_INDEX_VALUE_MASK(0x3ff << 0)
>> >+#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
>> > #define _PAL_PREC_DATA_A 0x4A404
>> > #define _PAL_PREC_DATA_B 0x4AC04
>> > #define _PAL_PREC_DATA_C 0x4B404
>> >diff --git a/drivers/gpu/drm/i915/intel_color.c
>> >b/drivers/gpu/drm/i915/intel_color.c
>> >index d5b3060c2645..5ef93c43afcf 100644
>> >--- a/drivers/gpu/drm/i915/intel_color.c
>> >+++ b/drivers/gpu/drm/i915/intel_color.c
>> >@@ -466,115 +466,83 @@ static void skl_color_commit(const struct
>> >intel_crtc_state
>> >*crtc_state)
>> >ilk_load_csc_matrix(crtc_state);
>> > }
>> >
>> >-static void bdw_load_degamma_lut(const struct intel_crtc_state
>> >*crtc_state)
>> >+static void bdw_load_lut_10(struct intel_crtc *crtc,
>> >+ const struct drm_property_blob *blob,
>> >+ u32 prec_index, bool duplicate)
>> > {
>> >- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> >struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >- const struct drm_property_blob *degamma_lut = crtc_state-
>> >>base.degamma_lut;
>> >- u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>> >+ const struct drm_color_lut *lut = blob->data;
>> >+ int i, lut_size = drm_color_lut_size(blob);
>> >enum pipe pipe = crtc->pipe;
>> >
>> >- I915_WRITE(PREC_PAL_INDEX(pipe),
>> >- PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
>> >-
>> >- if (degamma_lut) {
>> >- const struct drm_color_lut *lut = degamma_lut->data;
>> >+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
>> >+ PAL_PREC_AUTO_INCREMENT);
>> >
>> >- for (i = 0; i < lut_size; i++)
>> >- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>> >- } else {
>> >+ /*
>> >+* We advertize the split gamma sizes. When not using split
>>
>> Typo in advertise.
>
>Just a different language. Though maybe the 'z' isn't quite right even for US
>English.
>"Consistency not included" should be on the packaging.
Yeah agree :). Opened this on outlook and got this spell check.
>>
>> >+* gamma we just duplicate each entry.
>> >+*
>> >+* TODO: expose the full LUT to userspace
>> >+*/
>> >+ if (duplicate) {
>> >for (i = 0; i < lut_size; i++) {
>> >- u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
>> >
Re: [Intel-gfx] [PATCH] drm/i915: Move the decision to use the breadcrumb tasklet to the backend
Quoting Chris Wilson (2019-03-29 15:49:12)
> Use the engine->flags to store whether we want to kick the submission
> tasklet on receipt of a breadcrumb interrupt, so that this decision can
> be made by the submission backend and not dependent on a limited feature
> test within the interrupt handler. This should make it easier to adapt
> different submission backends.
This comes with a cherry on top!
add/remove: 0/1 grow/shrink: 2/2 up/down: 20/-86 (-66)
Function old new delta
guc_submission_park5 18 +13
guc_submission_unpark 5 12 +7
gen8_cs_irq_handler 97 77 -20
gen8_cs_irq_handler.cold 33 - -33
__func__ 28208 28175 -33
The function name was as large as the function itself?
> Signed-off-by: Chris Wilson
> Cc: Michal Wajdeczko
> Cc: Xiaolin Zhang
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_engine_types.h | 7 +++
> drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
> 3 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 455b2bf691b5..aa107a78cb36 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1470,7 +1470,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
> iir)
>
> if (iir & GT_RENDER_USER_INTERRUPT) {
> intel_engine_breadcrumbs_irq(engine);
> - tasklet |= USES_GUC_SUBMISSION(engine->i915);
> + tasklet |= intel_engine_needs_breadcrumb_tasklet(engine);
> }
>
> if (tasklet)
> diff --git a/drivers/gpu/drm/i915/intel_engine_types.h
> b/drivers/gpu/drm/i915/intel_engine_types.h
> index b3249bf6a65f..5c3f567a7a20 100644
> --- a/drivers/gpu/drm/i915/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/intel_engine_types.h
> @@ -425,6 +425,7 @@ struct intel_engine_cs {
> #define I915_ENGINE_SUPPORTS_STATS BIT(1)
> #define I915_ENGINE_HAS_PREEMPTION BIT(2)
> #define I915_ENGINE_HAS_SEMAPHORES BIT(3)
> +#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
> unsigned int flags;
>
> /*
> @@ -508,6 +509,12 @@ intel_engine_has_semaphores(const struct intel_engine_cs
> *engine)
> return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
> }
>
> +static inline bool
> +intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
> +{
> + return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> +}
> +
> #define instdone_slice_mask(dev_priv__) \
> (IS_GEN(dev_priv__, 7) ? \
> 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index c4ad73980988..c5896d47 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -1262,10 +1262,12 @@ static void guc_interrupts_release(struct
> drm_i915_private *dev_priv)
> static void guc_submission_park(struct intel_engine_cs *engine)
> {
> intel_engine_unpin_breadcrumbs_irq(engine);
> + engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> }
>
> static void guc_submission_unpark(struct intel_engine_cs *engine)
> {
> + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> intel_engine_pin_breadcrumbs_irq(engine);
> }
>
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have to
On Wed, Apr 03, 2019 at 12:23:06PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, April 2, 2019 1:32 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Shankar, Uma ; Roper, Matthew D
> >
> >Subject: [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have to
> >
> >From: Ville Syrjälä
> >
> >Using the split gamma mode when we don't have to has the annoying
> >requirement of
> >loading a linear LUT to the unused half. Instead let's make life simpler by
> >switching to
> >the 10bit gamma mode and duplicating each entry.
> >
> >This also allows us to load the software gamma LUT into the hardware degamma
> >LUT, thus removing some of the buggy configurations we currently allow
> >(YCbCr/limited range RGB
> >+ gamma LUT). We do still have other configurations that are
> >also buggy, but those will need more complicated fixes or they just need to
> >be
> >rejected. Sadly GLK doesn't have this flexibility anymore and the degamma and
> >gamma LUTs are very different so no help there.
> >
> >v2: Apply a mask when checking gamma_mode on icl since it
> >contains more bits than just the gamma mode
> >v3: Rebase due to EXT_GC_MAX/EXT2_GC_MAX changes
> >
> >Signed-off-by: Ville Syrjälä
> >---
> > drivers/gpu/drm/i915/i915_reg.h| 2 +
> > drivers/gpu/drm/i915/intel_color.c | 185 ++---
> > 2 files changed, 92 insertions(+), 95 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >b/drivers/gpu/drm/i915/i915_reg.h index
> >341f03e00536..bed2c52aebd8 100644
> >--- a/drivers/gpu/drm/i915/i915_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_reg.h
> >@@ -7214,6 +7214,7 @@ enum {
> > #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
> >_GAMMA_MODE_B)
> > #define PRE_CSC_GAMMA_ENABLE (1 << 31)
> > #define POST_CSC_GAMMA_ENABLE (1 << 30)
> >+#define GAMMA_MODE_MODE_MASK (3 << 0)
> > #define GAMMA_MODE_MODE_8BIT (0 << 0)
> > #define GAMMA_MODE_MODE_10BIT (1 << 0)
> > #define GAMMA_MODE_MODE_12BIT (2 << 0)
> >@@ -10127,6 +10128,7 @@ enum skl_power_gate {
> > #define PAL_PREC_SPLIT_MODE (1 << 31)
> > #define PAL_PREC_AUTO_INCREMENT (1 << 15)
> > #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
> >+#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
> > #define _PAL_PREC_DATA_A0x4A404
> > #define _PAL_PREC_DATA_B0x4AC04
> > #define _PAL_PREC_DATA_C0x4B404
> >diff --git a/drivers/gpu/drm/i915/intel_color.c
> >b/drivers/gpu/drm/i915/intel_color.c
> >index d5b3060c2645..5ef93c43afcf 100644
> >--- a/drivers/gpu/drm/i915/intel_color.c
> >+++ b/drivers/gpu/drm/i915/intel_color.c
> >@@ -466,115 +466,83 @@ static void skl_color_commit(const struct
> >intel_crtc_state
> >*crtc_state)
> > ilk_load_csc_matrix(crtc_state);
> > }
> >
> >-static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> >+static void bdw_load_lut_10(struct intel_crtc *crtc,
> >+const struct drm_property_blob *blob,
> >+u32 prec_index, bool duplicate)
> > {
> >-struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >-const struct drm_property_blob *degamma_lut = crtc_state-
> >>base.degamma_lut;
> >-u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> >+const struct drm_color_lut *lut = blob->data;
> >+int i, lut_size = drm_color_lut_size(blob);
> > enum pipe pipe = crtc->pipe;
> >
> >-I915_WRITE(PREC_PAL_INDEX(pipe),
> >- PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
> >-
> >-if (degamma_lut) {
> >-const struct drm_color_lut *lut = degamma_lut->data;
> >+I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
> >+ PAL_PREC_AUTO_INCREMENT);
> >
> >-for (i = 0; i < lut_size; i++)
> >-I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> >-} else {
> >+/*
> >+ * We advertize the split gamma sizes. When not using split
>
> Typo in advertise.
Just a different language. Though maybe the 'z' isn't quite right even
for US English. "Consistency not included" should be on the packaging.
>
> >+ * gamma we just duplicate each entry.
> >+ *
> >+ * TODO: expose the full LUT to userspace
> >+ */
> >+if (duplicate) {
> > for (i = 0; i < lut_size; i++) {
> >-u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
> >-
> >-I915_WRITE(PREC_PAL_DATA(pipe),
> >- (v << 20) | (v << 10) | v);
> >+I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> >+I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> > }
> >+} else {
> >+for (i = 0; i < lut_size; i++)
> >+I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[
Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have to
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, April 2, 2019 1:32 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma ; Roper, Matthew D
>
>Subject: [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have to
>
>From: Ville Syrjälä
>
>Using the split gamma mode when we don't have to has the annoying requirement
>of
>loading a linear LUT to the unused half. Instead let's make life simpler by
>switching to
>the 10bit gamma mode and duplicating each entry.
>
>This also allows us to load the software gamma LUT into the hardware degamma
>LUT, thus removing some of the buggy configurations we currently allow
>(YCbCr/limited range RGB
>+ gamma LUT). We do still have other configurations that are
>also buggy, but those will need more complicated fixes or they just need to be
>rejected. Sadly GLK doesn't have this flexibility anymore and the degamma and
>gamma LUTs are very different so no help there.
>
>v2: Apply a mask when checking gamma_mode on icl since it
>contains more bits than just the gamma mode
>v3: Rebase due to EXT_GC_MAX/EXT2_GC_MAX changes
>
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/i915_reg.h| 2 +
> drivers/gpu/drm/i915/intel_color.c | 185 ++---
> 2 files changed, 92 insertions(+), 95 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index
>341f03e00536..bed2c52aebd8 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7214,6 +7214,7 @@ enum {
> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
>_GAMMA_MODE_B)
> #define PRE_CSC_GAMMA_ENABLE (1 << 31)
> #define POST_CSC_GAMMA_ENABLE(1 << 30)
>+#define GAMMA_MODE_MODE_MASK (3 << 0)
> #define GAMMA_MODE_MODE_8BIT (0 << 0)
> #define GAMMA_MODE_MODE_10BIT(1 << 0)
> #define GAMMA_MODE_MODE_12BIT(2 << 0)
>@@ -10127,6 +10128,7 @@ enum skl_power_gate {
> #define PAL_PREC_SPLIT_MODE (1 << 31)
> #define PAL_PREC_AUTO_INCREMENT (1 << 15)
> #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
>+#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
> #define _PAL_PREC_DATA_A 0x4A404
> #define _PAL_PREC_DATA_B 0x4AC04
> #define _PAL_PREC_DATA_C 0x4B404
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index d5b3060c2645..5ef93c43afcf 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -466,115 +466,83 @@ static void skl_color_commit(const struct
>intel_crtc_state
>*crtc_state)
> ilk_load_csc_matrix(crtc_state);
> }
>
>-static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>+static void bdw_load_lut_10(struct intel_crtc *crtc,
>+ const struct drm_property_blob *blob,
>+ u32 prec_index, bool duplicate)
> {
>- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>- const struct drm_property_blob *degamma_lut = crtc_state-
>>base.degamma_lut;
>- u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>+ const struct drm_color_lut *lut = blob->data;
>+ int i, lut_size = drm_color_lut_size(blob);
> enum pipe pipe = crtc->pipe;
>
>- I915_WRITE(PREC_PAL_INDEX(pipe),
>- PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
>-
>- if (degamma_lut) {
>- const struct drm_color_lut *lut = degamma_lut->data;
>+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
>+ PAL_PREC_AUTO_INCREMENT);
>
>- for (i = 0; i < lut_size; i++)
>- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>- } else {
>+ /*
>+ * We advertize the split gamma sizes. When not using split
Typo in advertise.
>+ * gamma we just duplicate each entry.
>+ *
>+ * TODO: expose the full LUT to userspace
>+ */
>+ if (duplicate) {
> for (i = 0; i < lut_size; i++) {
>- u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
>-
>- I915_WRITE(PREC_PAL_DATA(pipe),
>- (v << 20) | (v << 10) | v);
>+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> }
>+ } else {
>+ for (i = 0; i < lut_size; i++)
>+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> }
>+
>+ /*
>+ * Reset the index, otherwise it prevents the legacy palette to be
>+ * written properly.
>+ */
>+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> }
>
>-static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32
>offset)
>+static void bdw_load_lut_10_max(struct intel_crtc *crtc)
> {
>- struct intel_crtc
Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count
On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> For certain eDP 1.4 panels, we need to use max lane count for the
> link training to succeed.
>
> This patch adds a EDID quirk for such eDP panels using
> their vendor ID and product ID to force using max lane count in the driver.
Rather than opening the quirk can of worms I think we should consider
changing the retry loop to do something more sensible than what it's
doing now. The current behaviour of "start at optimal settings (which
can be either min lanes or min rate), and then reduce lanes/rate until
stuff works" overlooks several possible combinations. One possible
approach could be to start the retry loop with max lanes + max rate
after the optimal settings have failed. It probably won't give you
the best power consumption, but at least you get a picture on the
screen if even a single lane count + rate combo works.
>
> Cc: Clint Taylor
> Cc: Ville Syrjälä
> Tested-by: Albert Astals Cid
> Tested-by: Emanuele Panigati
> Tested-by: Ralgor
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/drm_edid.c | 10 ++
> include/drm/drm_connector.h | 5 +
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 2c22ea446075..fbc661806484 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -82,6 +82,8 @@
> #define EDID_QUIRK_FORCE_10BPC (1 << 11)
> /* Non desktop display (i.e. HMD) */
> #define EDID_QUIRK_NON_DESKTOP (1 << 12)
> +/* Force max lane count */
> +#define EDID_QUIRK_FORCE_MAX_LANE_COUNT (1 << 13)
>
> struct detailed_mode_closure {
> struct drm_connector *connector;
> @@ -189,6 +191,10 @@ static const struct edid_quirk {
>
> /* OSVR HDK and HDK2 VR Headsets */
> { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
> +
> + /* SHP eDP 1.4 panel only works with max lane count */
> + { "SHP", 0x149a, EDID_QUIRK_FORCE_MAX_LANE_COUNT },
> + { "SHP", 0x148e, EDID_QUIRK_FORCE_MAX_LANE_COUNT },
> };
>
> /*
> @@ -4463,6 +4469,7 @@ drm_reset_display_info(struct drm_connector *connector)
> memset(&info->hdmi, 0, sizeof(info->hdmi));
>
> info->non_desktop = 0;
> + info->force_max_lane_count = 0;
> }
>
> u32 drm_add_display_info(struct drm_connector *connector, const struct edid
> *edid)
> @@ -4744,6 +4751,9 @@ int drm_add_edid_modes(struct drm_connector *connector,
> struct edid *edid)
> if (quirks & EDID_QUIRK_FORCE_12BPC)
> connector->display_info.bpc = 12;
>
> + if (quirks & EDID_QUIRK_FORCE_MAX_LANE_COUNT)
> + connector->display_info.force_max_lane_count = true;
> +
> return num_modes;
> }
> EXPORT_SYMBOL(drm_add_edid_modes);
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 02a131202add..45436d40ffe3 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -457,6 +457,11 @@ struct drm_display_info {
>* @non_desktop: Non desktop display (HMD).
>*/
> bool non_desktop;
> +
> + /**
> + * @force_max_lane_count: Link training requires max lane count to pass
> + */
> + bool force_max_lane_count;
> };
>
> int drm_display_info_set_bus_formats(struct drm_display_info *info,
> --
> 2.19.1
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add Makefile magic for testing headers are self-contained (rev2)
== Series Details == Series: drm/i915: add Makefile magic for testing headers are self-contained (rev2) URL : https://patchwork.freedesktop.org/series/58938/ State : success == Summary == CI Bug Log - changes from CI_DRM_5862 -> Patchwork_12673 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58938/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12673 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@basic-bsd2: - fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@gtt-bsd1: - fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-rejected: - fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1 - fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: PASS -> FAIL [fdo#108511] * igt@i915_selftest@live_contexts: - fi-icl-u3: NOTRUN -> DMESG-FAIL [fdo#108569] - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] - fi-icl-y: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_chamelium@dp-crc-fast: - fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8 * igt@kms_chamelium@hdmi-edid-read: - fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8 * igt@kms_force_connector_basic@force-load-detect: - fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#107362] * igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_psr@primary_mmap_gtt: - fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3 - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27 * igt@prime_vgem@basic-fence-flip: - fi-icl-y: NOTRUN -> SKIP [fdo#109294] Possible fixes * igt@debugfs_test@read_all_entries: - fi-icl-y: INCOMPLETE [fdo#110246] -> PASS * igt@gem_basic@bad-close: - fi-icl-u3: INCOMPLETE -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [fdo#110246]: https://bugs.freedesktop.org/show_bug.cgi?id=110246 Participating hosts (45 -> 39) -- Missing(6): fi-kbl-soraka fi-ilk-m540 fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_5862 -> Patchwork_12673 CI_DRM_5862: c97de10a1caf7b856efe273c901fceea3fc78367 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4923: 6285eec4f3b8f21833d9d2d852883569d6551822 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12673: fc28b7a305b35b247fb27075d9afc2c0e1d9f329 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fc28b7a305b3 drm/i915: add Makefile magic for testing headers are self-contained == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12673/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count
== Series Details == Series: series starting with [1/2] drm/edid: Add a EDID edp panel quirk for forcing max lane count URL : https://patchwork.freedesktop.org/series/58893/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5857_full -> Patchwork_12661_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12661_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12661_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12661_full: ### IGT changes ### Possible regressions * igt@gem_tiled_pread_pwrite: - shard-iclb: PASS -> DMESG-WARN * igt@runner@aborted: - shard-iclb: NOTRUN -> FAIL Known issues Here are the changes found in Patchwork_12661_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s4-devices: - shard-iclb: PASS -> DMESG-WARN [fdo#109638] * igt@gem_mmap_gtt@hang: - shard-iclb: PASS -> FAIL [fdo#109677] * igt@gem_pwrite@big-gtt-fbr: - shard-iclb: PASS -> TIMEOUT [fdo#109673] * igt@i915_pm_rpm@legacy-planes-dpms: - shard-iclb: PASS -> INCOMPLETE [fdo#108840] / [fdo#109369] * igt@i915_pm_rpm@system-suspend-modeset: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107807] * igt@i915_pm_rps@reset: - shard-iclb: NOTRUN -> FAIL [fdo#108059] * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13 * igt@kms_busy@extended-pageflip-hang-newfb-render-d: - shard-iclb: NOTRUN -> SKIP [fdo#109278] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-glk: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_cursor_crc@cursor-128x42-sliding: - shard-glk: NOTRUN -> FAIL [fdo#103232] +1 * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-glk: PASS -> FAIL [fdo#104873] * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: NOTRUN -> FAIL [fdo#105363] * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-apl: PASS -> FAIL [fdo#103060] * igt@kms_flip_tiling@flip-y-tiled: - shard-iclb: PASS -> FAIL [fdo#108303] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#103167] +9 * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-iclb: NOTRUN -> FAIL [fdo#103167] / [fdo#105682] * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render: - shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +7 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: NOTRUN -> SKIP [fdo#109280] * igt@kms_frontbuffer_tracking@fbcpsr-tilingchange: - shard-iclb: PASS -> FAIL [fdo#109247] +4 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render: - shard-skl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-glk: NOTRUN -> SKIP [fdo#109271] +57 * igt@kms_frontbuffer_tracking@psr-farfromfence: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +4 * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5 * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr@cursor_plane_onoff: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] * igt@kms_psr@psr2_cursor_render: - shard-iclb: PASS -> SKIP [fdo#109441] +1 * igt@kms_psr@psr2_primary_render: - shard-apl: NOTRUN -> SKIP [fdo#109271] +2 * igt@kms_se
Re: [Intel-gfx] [PATCH] drm/i915: add Makefile magic for testing headers are self-contained
On Wed, 03 Apr 2019, Chris Wilson wrote:
> From: Jani Nikula
>
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
> i915_request_types.h")
> 8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
>
> The idea is fine, but the implementation is a bit tedious and
> inflexible, and does not really scale well.
>
> Implement the same in make using autogenerated dummy sources to include
> the headers.
>
> Cc: Chris Wilson
> Cc: Tvrtko Ursulin
> Signed-off-by: Jani Nikula
> ---
> Use patsubst liberally to reduce the chore of adding more headers.
> make clean doesn't quite work yet, although it seems to be the right
> style.
I don't know what gives, I'm unable to make it work. I've been trying
with O= builds.
> ---
> drivers/gpu/drm/i915/.gitignore | 1 +
> drivers/gpu/drm/i915/Makefile | 16 -
> drivers/gpu/drm/i915/Makefile.header-test | 24 +++
> .../i915/test_i915_active_types_standalone.c | 7 --
> .../test_i915_gem_context_types_standalone.c | 7 --
> .../test_i915_priolist_types_standalone.c | 7 --
> .../test_i915_scheduler_types_standalone.c| 7 --
> .../test_i915_timeline_types_standalone.c | 7 --
> .../test_intel_context_types_standalone.c | 7 --
> .../i915/test_intel_engine_types_standalone.c | 7 --
> .../test_intel_workarounds_types_standalone.c | 7 --
> 11 files changed, 30 insertions(+), 67 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/.gitignore
> create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
> delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_intel_context_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
>
> diff --git a/drivers/gpu/drm/i915/.gitignore b/drivers/gpu/drm/i915/.gitignore
> new file mode 100644
> index ..cff45d81f42f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/.gitignore
> @@ -0,0 +1 @@
> +header_test_*.c
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 30bf3301ea24..91eaccca4f4f 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -32,6 +32,11 @@ CFLAGS_intel_fbdev.o = $(call cc-disable-warning,
> override-init)
> subdir-ccflags-y += \
> $(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
>
> +# Extra header tests
> +ifeq ($(CONFIG_DRM_I915_WERROR),y)
> +include $(src)/Makefile.header-test
> +endif
> +
Agreed on adding this first, though you'll need to omit -j to actually
make it happen first.
> # Please keep these build lists sorted!
>
> # core driver code
> @@ -57,17 +62,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
> i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
> i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
>
> -# Test the headers are compilable as standalone units
> -i915-$(CONFIG_DRM_I915_WERROR) += \
> - test_i915_active_types_standalone.o \
> - test_i915_gem_context_types_standalone.o \
> - test_i915_priolist_types_standalone.o \
> - test_i915_scheduler_types_standalone.o \
> - test_i915_timeline_types_standalone.o \
> - test_intel_context_types_standalone.o \
> - test_intel_engine_types_standalone.o \
> - test_intel_workarounds_types_standalone.o
> -
> # GEM code
> i915-y += \
> i915_active.o \
> diff --git a/drivers/gpu/drm/i915/Makefile.header-test
> b/drivers/gpu/drm/i915/Makefile.header-test
> new file mode 100644
> index ..5396bd6bae4c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/Makefile.header-test
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: MIT
> +# Copyright © 2019 Intel Corporation
> +
> +# Test the headers are compilable as standalone units
> +header_test := \
> + i915_active_types.h \
> + i915_gem_context_types.h \
> + i915_priolist_types.h \
> + i915_scheduler_types.h \
> + i915_timeline_types.h \
> + intel_context_types.h \
> + intel_engine_types.h \
> + intel_workarounds_types.h
> +
> +quiet_cmd_header_test = HDRTEST $@
> + cmd_header_test = echo "\#include \"$( $@
> +
> +header_test_%.c: %.h
> + $(call cmd,header_test)
> +
> +# To test .h add header_test_.o here
The comment just beca
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add Makefile magic for testing headers are self-contained (rev2)
== Series Details ==
Series: drm/i915: add Makefile magic for testing headers are self-contained
(rev2)
URL : https://patchwork.freedesktop.org/series/58938/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fc28b7a305b3 drm/i915: add Makefile magic for testing headers are self-contained
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 39e2f501c1b4 ("drm/i915: Split
struct intel_context definition to its own header")'
#10:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3a891a626794 ("drm/i915: Move
intel_engine_mask_t around for use by i915_request_types.h")'
#11:
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 8b74594aa455 ("drm/i915: Split
out i915_priolist_types into its own header")'
#12:
8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#25:
new file mode 100644
total: 3 errors, 2 warnings, 0 checks, 53 lines checked
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add Makefile magic for testing headers are self-contained (rev2)
== Series Details == Series: drm/i915: add Makefile magic for testing headers are self-contained (rev2) URL : https://patchwork.freedesktop.org/series/58938/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: add Makefile magic for testing headers are self-contained -./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) -./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) -./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) + ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
On Tue, Apr 02, 2019 at 10:17:25PM -0700, Aditya Swarup wrote:
> From: Clinton Taylor
>
> v2: Fix commit msg to reflect why issue occurs(Jani)
> Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
>
> Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> doesn't work correctly using xrandr max bpc property. When we
> connect a monitor which supports deep color, the highest deep color
> setting is selected; which sets GCP_COLOR_INDICATION. When we change
> the setting to 8 bit color, we still set GCP_COLOR_INDICATION which
> doesn't allow the switch back to 8 bit color.
>
> v3: Add comments & explain changes in intel_hdmi_compute_config(Ville)
> Since HSW+, GCP_COLOR_INDICATION is not required for 8bpc.
>
> Also, remove unnecessary calls to hdmi_deep_color_possible() from
> intel_hdmi_compute_config()
Nope. Please drop those hunsk.
>
> Ideally, hdmi_deep_color_possible() should be called only
> once to determine whether it is possible to set 10 or 12 bit
> deep color mode and adjust the desired bpp based on pipe_bpp
> instead of hard coding the values.
>
> Signed-off-by: Clinton Taylor
> Signed-off-by: Aditya Swarup
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Cc: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 36 ---
> 1 file changed, 19 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 5ccb305a6e1c..a93736fb1950 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -962,8 +962,13 @@ static void intel_hdmi_compute_gcp_infoframe(struct
> intel_encoder *encoder,
> crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
>
> - /* Indicate color depth whenever the sink supports deep color */
> - if (hdmi_sink_is_deep_color(conn_state))
> + /* Indicate color depth whenever the sink supports deep color.
> + * Also, 8bpc + color depth indication is no longer supported
> + * for HSW+ platforms.
> + * */
> +
> + if (hdmi_sink_is_deep_color(conn_state) &&
> + crtc_state->pipe_bpp > 24)
> crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
>
> /* Enable default_phase whenever the display mode is suitably aligned */
> @@ -2260,6 +2265,7 @@ int intel_hdmi_compute_config(struct intel_encoder
> *encoder,
> int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
> int clock_10bpc = clock_8bpc * 5 / 4;
> int clock_12bpc = clock_8bpc * 3 / 2;
> + int dc_clock = clock_12bpc;
> int desired_bpp;
> bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
>
> @@ -2314,22 +2320,18 @@ int intel_hdmi_compute_config(struct intel_encoder
> *encoder,
>* Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
>* to check that the higher clock still fits within limits.
>*/
> - if (hdmi_deep_color_possible(pipe_config, 12) &&
> - hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
> + if (pipe_config->pipe_bpp == 30)
> + dc_clock = clock_10bpc;
> +
> + if (hdmi_deep_color_possible(pipe_config, pipe_config->pipe_bpp / 3) &&
> + hdmi_port_clock_valid(intel_hdmi, dc_clock,
> true, force_dvi) == MODE_OK) {
> - DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
> - desired_bpp = 12*3;
> -
> - /* Need to adjust the port link by 1.5x for 12bpc. */
> - pipe_config->port_clock = clock_12bpc;
> - } else if (hdmi_deep_color_possible(pipe_config, 10) &&
> -hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
> - true, force_dvi) == MODE_OK) {
> - DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
> - desired_bpp = 10 * 3;
> -
> - /* Need to adjust the port link by 1.25x for 10bpc. */
> - pipe_config->port_clock = clock_10bpc;
> + DRM_DEBUG_KMS("picking bpc to %d for HDMI output\n",
> +pipe_config->pipe_bpp / 3);
> + desired_bpp = pipe_config->pipe_bpp;
> +
> + /* Need to adjust the port link dc modes. */
> + pipe_config->port_clock = dc_clock;
> } else {
> DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
> desired_bpp = 8*3;
> --
> 2.17.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915: add Makefile magic for testing headers are self-contained
Quoting Jani Nikula (2019-04-03 11:06:36)
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
> i915_request_types.h")
> 8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
>
> The idea is fine, but the implementation is a bit tedious and
> inflexible, and does not really scale well.
>
> Implement the same in make using autogenerated dummy sources to include
> the headers.
The next question is to how to handle subdirs?
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[Intel-gfx] [PATCH] drm/i915: add Makefile magic for testing headers are self-contained
From: Jani Nikula
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
The idea is fine, but the implementation is a bit tedious and
inflexible, and does not really scale well.
Implement the same in make using autogenerated dummy sources to include
the headers.
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Signed-off-by: Jani Nikula
---
Use patsubst liberally to reduce the chore of adding more headers.
make clean doesn't quite work yet, although it seems to be the right
style.
---
drivers/gpu/drm/i915/.gitignore | 1 +
drivers/gpu/drm/i915/Makefile | 16 -
drivers/gpu/drm/i915/Makefile.header-test | 24 +++
.../i915/test_i915_active_types_standalone.c | 7 --
.../test_i915_gem_context_types_standalone.c | 7 --
.../test_i915_priolist_types_standalone.c | 7 --
.../test_i915_scheduler_types_standalone.c| 7 --
.../test_i915_timeline_types_standalone.c | 7 --
.../test_intel_context_types_standalone.c | 7 --
.../i915/test_intel_engine_types_standalone.c | 7 --
.../test_intel_workarounds_types_standalone.c | 7 --
11 files changed, 30 insertions(+), 67 deletions(-)
create mode 100644 drivers/gpu/drm/i915/.gitignore
create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
diff --git a/drivers/gpu/drm/i915/.gitignore b/drivers/gpu/drm/i915/.gitignore
new file mode 100644
index ..cff45d81f42f
--- /dev/null
+++ b/drivers/gpu/drm/i915/.gitignore
@@ -0,0 +1 @@
+header_test_*.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 30bf3301ea24..91eaccca4f4f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -32,6 +32,11 @@ CFLAGS_intel_fbdev.o = $(call cc-disable-warning,
override-init)
subdir-ccflags-y += \
$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
+# Extra header tests
+ifeq ($(CONFIG_DRM_I915_WERROR),y)
+include $(src)/Makefile.header-test
+endif
+
# Please keep these build lists sorted!
# core driver code
@@ -57,17 +62,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
-# Test the headers are compilable as standalone units
-i915-$(CONFIG_DRM_I915_WERROR) += \
- test_i915_active_types_standalone.o \
- test_i915_gem_context_types_standalone.o \
- test_i915_priolist_types_standalone.o \
- test_i915_scheduler_types_standalone.o \
- test_i915_timeline_types_standalone.o \
- test_intel_context_types_standalone.o \
- test_intel_engine_types_standalone.o \
- test_intel_workarounds_types_standalone.o
-
# GEM code
i915-y += \
i915_active.o \
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
new file mode 100644
index ..5396bd6bae4c
--- /dev/null
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: MIT
+# Copyright © 2019 Intel Corporation
+
+# Test the headers are compilable as standalone units
+header_test := \
+ i915_active_types.h \
+ i915_gem_context_types.h \
+ i915_priolist_types.h \
+ i915_scheduler_types.h \
+ i915_timeline_types.h \
+ intel_context_types.h \
+ intel_engine_types.h \
+ intel_workarounds_types.h
+
+quiet_cmd_header_test = HDRTEST$@
+ cmd_header_test = echo "\#include \"$( $@
+
+header_test_%.c: %.h
+ $(call cmd,header_test)
+
+# To test .h add header_test_.o here
+extra-y += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
+
+clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))
diff --git a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
b/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
deleted file mode 100644
index 144ebd153e57..
--- a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
Re: [Intel-gfx] [PATCH] drm/i915: add Makefile magic for testing headers are self-contained
Quoting Jani Nikula (2019-04-03 11:06:36)
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
> i915_request_types.h")
> 8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
>
> The idea is fine, but the implementation is a bit tedious and
> inflexible, and does not really scale well.
>
> Implement the same in make using autogenerated dummy sources to include
> the headers.
Also wants
i915/.gitignore: header_test_*.c
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: add Makefile magic for testing headers are self-contained
Quoting Chris Wilson (2019-04-03 11:10:31)
> Quoting Jani Nikula (2019-04-03 11:06:36)
> > The below commits added dummy files to test that certain headers are
> > self-contained, i.e. compilable as standalone units:
> >
> > 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> > header")
> > 3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
> > i915_request_types.h")
> > 8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
> >
> > The idea is fine, but the implementation is a bit tedious and
> > inflexible, and does not really scale well.
> >
> > Implement the same in make using autogenerated dummy sources to include
> > the headers.
>
> I knew it would work :-p
>
> > Cc: Chris Wilson
> > Cc: Tvrtko Ursulin
> > Signed-off-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/Makefile | 16 +-
> > drivers/gpu/drm/i915/Makefile.header-test | 21 +++
> > .../i915/test_i915_active_types_standalone.c | 7 ---
> > .../test_i915_gem_context_types_standalone.c | 7 ---
> > .../test_i915_priolist_types_standalone.c | 7 ---
> > .../test_i915_scheduler_types_standalone.c| 7 ---
> > .../test_i915_timeline_types_standalone.c | 7 ---
> > .../test_intel_context_types_standalone.c | 7 ---
> > .../i915/test_intel_engine_types_standalone.c | 7 ---
> > .../test_intel_workarounds_types_standalone.c | 7 ---
> > 10 files changed, 26 insertions(+), 67 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
> > delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
> > delete mode 100644
> > drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
> > delete mode 100644
> > drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
> > delete mode 100644
> > drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
> > delete mode 100644
> > drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
> > delete mode 100644
> > drivers/gpu/drm/i915/test_intel_context_types_standalone.c
> > delete mode 100644
> > drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
> > delete mode 100644
> > drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 30bf33..dba77b 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -57,17 +57,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
> > i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
> > i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
> >
> > -# Test the headers are compilable as standalone units
> > -i915-$(CONFIG_DRM_I915_WERROR) += \
> > - test_i915_active_types_standalone.o \
> > - test_i915_gem_context_types_standalone.o \
> > - test_i915_priolist_types_standalone.o \
> > - test_i915_scheduler_types_standalone.o \
> > - test_i915_timeline_types_standalone.o \
> > - test_intel_context_types_standalone.o \
> > - test_intel_engine_types_standalone.o \
> > - test_intel_workarounds_types_standalone.o
> > -
> > # GEM code
> > i915-y += \
> > i915_active.o \
> > @@ -218,3 +207,8 @@ i915-y += intel_lpe_audio.o
> >
> > obj-$(CONFIG_DRM_I915) += i915.o
> > obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o
> > +
> > +# Extra header tests
> > +ifeq ($(CONFIG_DRM_I915_WERROR),y)
> > +include $(src)/Makefile.header-test
> > +endif
>
> Can we get the headers tested first?
>
> Fixing the standalone tests is a lot easier than traversing the
> dependency chain of includes in a regular compile file.
>
> > diff --git a/drivers/gpu/drm/i915/Makefile.header-test
> > b/drivers/gpu/drm/i915/Makefile.header-test
> > new file mode 100644
> > index 00..0cae6e3
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/Makefile.header-test
> > @@ -0,0 +1,21 @@
> > +# SPDX-License-Identifier: MIT
> > +# Copyright © 2019 Intel Corporation
> > +
> > +# Test the headers are compilable as standalone units
> > +
> > +quiet_cmd_header_test = HDRTEST$@
> > + cmd_header_test = echo "\#include \"$( $@
> > +
> > +header_test_%.c: %.h
> > + $(call cmd,header_test)
> > +
> > +# To test .h add header_test_.o here
> > +extra-y += \
> > + header_test_i915_active_types.o \
> > + header_test_i915_gem_context_types.o \
> > + header_test_i915_priolist_types.o \
> > + header_test_i915_scheduler_types.o \
> > + header_test_i915_timeline_types.o \
> > + header_test_intel_context_types.o \
> > + header_test_intel_engine_types.o \
> > + header_test_intel_workarounds_types.o
>
> Should there be a way to add the autogenerated files to make clean?
clean-files += header_test_*.c
No idea if that works.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: add Makefile magic for testing headers are self-contained
Quoting Jani Nikula (2019-04-03 11:06:36)
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
> i915_request_types.h")
> 8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
>
> The idea is fine, but the implementation is a bit tedious and
> inflexible, and does not really scale well.
>
> Implement the same in make using autogenerated dummy sources to include
> the headers.
I knew it would work :-p
> Cc: Chris Wilson
> Cc: Tvrtko Ursulin
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/Makefile | 16 +-
> drivers/gpu/drm/i915/Makefile.header-test | 21 +++
> .../i915/test_i915_active_types_standalone.c | 7 ---
> .../test_i915_gem_context_types_standalone.c | 7 ---
> .../test_i915_priolist_types_standalone.c | 7 ---
> .../test_i915_scheduler_types_standalone.c| 7 ---
> .../test_i915_timeline_types_standalone.c | 7 ---
> .../test_intel_context_types_standalone.c | 7 ---
> .../i915/test_intel_engine_types_standalone.c | 7 ---
> .../test_intel_workarounds_types_standalone.c | 7 ---
> 10 files changed, 26 insertions(+), 67 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
> delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_intel_context_types_standalone.c
> delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
> delete mode 100644
> drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 30bf33..dba77b 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -57,17 +57,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
> i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
> i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
>
> -# Test the headers are compilable as standalone units
> -i915-$(CONFIG_DRM_I915_WERROR) += \
> - test_i915_active_types_standalone.o \
> - test_i915_gem_context_types_standalone.o \
> - test_i915_priolist_types_standalone.o \
> - test_i915_scheduler_types_standalone.o \
> - test_i915_timeline_types_standalone.o \
> - test_intel_context_types_standalone.o \
> - test_intel_engine_types_standalone.o \
> - test_intel_workarounds_types_standalone.o
> -
> # GEM code
> i915-y += \
> i915_active.o \
> @@ -218,3 +207,8 @@ i915-y += intel_lpe_audio.o
>
> obj-$(CONFIG_DRM_I915) += i915.o
> obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o
> +
> +# Extra header tests
> +ifeq ($(CONFIG_DRM_I915_WERROR),y)
> +include $(src)/Makefile.header-test
> +endif
Can we get the headers tested first?
Fixing the standalone tests is a lot easier than traversing the
dependency chain of includes in a regular compile file.
> diff --git a/drivers/gpu/drm/i915/Makefile.header-test
> b/drivers/gpu/drm/i915/Makefile.header-test
> new file mode 100644
> index 00..0cae6e3
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/Makefile.header-test
> @@ -0,0 +1,21 @@
> +# SPDX-License-Identifier: MIT
> +# Copyright © 2019 Intel Corporation
> +
> +# Test the headers are compilable as standalone units
> +
> +quiet_cmd_header_test = HDRTEST$@
> + cmd_header_test = echo "\#include \"$( $@
> +
> +header_test_%.c: %.h
> + $(call cmd,header_test)
> +
> +# To test .h add header_test_.o here
> +extra-y += \
> + header_test_i915_active_types.o \
> + header_test_i915_gem_context_types.o \
> + header_test_i915_priolist_types.o \
> + header_test_i915_scheduler_types.o \
> + header_test_i915_timeline_types.o \
> + header_test_intel_context_types.o \
> + header_test_intel_engine_types.o \
> + header_test_intel_workarounds_types.o
Should there be a way to add the autogenerated files to make clean?
-Chris
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[Intel-gfx] [PATCH] drm/i915: add Makefile magic for testing headers are self-contained
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header")
The idea is fine, but the implementation is a bit tedious and
inflexible, and does not really scale well.
Implement the same in make using autogenerated dummy sources to include
the headers.
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 16 +-
drivers/gpu/drm/i915/Makefile.header-test | 21 +++
.../i915/test_i915_active_types_standalone.c | 7 ---
.../test_i915_gem_context_types_standalone.c | 7 ---
.../test_i915_priolist_types_standalone.c | 7 ---
.../test_i915_scheduler_types_standalone.c| 7 ---
.../test_i915_timeline_types_standalone.c | 7 ---
.../test_intel_context_types_standalone.c | 7 ---
.../i915/test_intel_engine_types_standalone.c | 7 ---
.../test_intel_workarounds_types_standalone.c | 7 ---
10 files changed, 26 insertions(+), 67 deletions(-)
create mode 100644 drivers/gpu/drm/i915/Makefile.header-test
delete mode 100644 drivers/gpu/drm/i915/test_i915_active_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_i915_timeline_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_context_types_standalone.c
delete mode 100644 drivers/gpu/drm/i915/test_intel_engine_types_standalone.c
delete mode 100644
drivers/gpu/drm/i915/test_intel_workarounds_types_standalone.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 30bf33..dba77b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,17 +57,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
-# Test the headers are compilable as standalone units
-i915-$(CONFIG_DRM_I915_WERROR) += \
- test_i915_active_types_standalone.o \
- test_i915_gem_context_types_standalone.o \
- test_i915_priolist_types_standalone.o \
- test_i915_scheduler_types_standalone.o \
- test_i915_timeline_types_standalone.o \
- test_intel_context_types_standalone.o \
- test_intel_engine_types_standalone.o \
- test_intel_workarounds_types_standalone.o
-
# GEM code
i915-y += \
i915_active.o \
@@ -218,3 +207,8 @@ i915-y += intel_lpe_audio.o
obj-$(CONFIG_DRM_I915) += i915.o
obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o
+
+# Extra header tests
+ifeq ($(CONFIG_DRM_I915_WERROR),y)
+include $(src)/Makefile.header-test
+endif
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
new file mode 100644
index 00..0cae6e3
--- /dev/null
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: MIT
+# Copyright © 2019 Intel Corporation
+
+# Test the headers are compilable as standalone units
+
+quiet_cmd_header_test = HDRTEST$@
+ cmd_header_test = echo "\#include \"$( $@
+
+header_test_%.c: %.h
+ $(call cmd,header_test)
+
+# To test .h add header_test_.o here
+extra-y += \
+ header_test_i915_active_types.o \
+ header_test_i915_gem_context_types.o \
+ header_test_i915_priolist_types.o \
+ header_test_i915_scheduler_types.o \
+ header_test_i915_timeline_types.o \
+ header_test_intel_context_types.o \
+ header_test_intel_engine_types.o \
+ header_test_intel_workarounds_types.o
diff --git a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
b/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
deleted file mode 100644
index 144ebd..00
--- a/drivers/gpu/drm/i915/test_i915_active_types_standalone.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * SPDX-License-Identifier: MIT
- *
- * Copyright © 2019 Intel Corporation
- */
-
-#include "i915_active_types.h"
diff --git a/drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
b/drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
deleted file mode 100644
index 4e4da486..00
--- a/drivers/gpu/drm/i915/test_i915_gem_context_types_standalone.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * SPDX-License-Identifier: MIT
- *
- * Copyright © 2019 Intel Corporation
- */
-
-#include "i915_gem_context_types.h"
diff --git a/drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
b/drivers/gpu/drm/i915/test_i915_priolist_types_standalone.c
deleted file mode 100644
index f465eb.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use lockdep_pin_lock() over the construction of the request
== Series Details == Series: drm/i915: Use lockdep_pin_lock() over the construction of the request URL : https://patchwork.freedesktop.org/series/58932/ State : success == Summary == CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12672 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58932/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12672 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_workarounds@basic-read: - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] +57 * igt@i915_selftest@live_contexts: - fi-icl-y: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_module_load@reload: - fi-icl-y: INCOMPLETE [fdo#107713] -> PASS * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS * igt@i915_selftest@live_hangcheck: - fi-icl-u3: INCOMPLETE [fdo#108569] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (46 -> 41) -- Additional (2): fi-hsw-4770r fi-snb-2600 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-icl-u2 fi-ctg-p8600 fi-bdw-samus fi-skl-6600u Build changes - * Linux: CI_DRM_5860 -> Patchwork_12672 CI_DRM_5860: 837ba3cd997b59e53903ba29f4fe65c81f86f1e9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4923: 6285eec4f3b8f21833d9d2d852883569d6551822 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12672: 5d983be6f468826e12805c63cf1e6c76b09204bc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5d983be6f468 drm/i915: Use lockdep_pin_lock() over the construction of the request == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12672/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: use unsigned long for platform_mask
On 03/04/2019 09:15, Lucas De Marchi wrote:
On Tue, Apr 2, 2019 at 11:58 PM Tvrtko Ursulin
wrote:
On 03/04/2019 02:46, Lucas De Marchi wrote:
No reason to stick to u32 for platform mask if we can just use more bits
on 64 bit platforms.
$ size drivers/gpu/drm/i915/i915.ko*
text data bss dec hex filename
1884779 413345408 1931521 1d7901 drivers/gpu/drm/i915/i915.ko
1886693 413585408 1933459 1d8093 drivers/gpu/drm/i915/i915.ko.old
How did you get such a large difference, and decrease even? Could you
check in the code what is happening? Because I get an increase with this
patch:
textdata bss dec hex filename
1905314 439037424 1956641 1ddb21 i915.ko.orig
1905796 439037424 1957123 1ddd03 i915.ko.patch
the only explanation I really have is that my measurement was bogus.
Some possible explanations...
1) I compared a i386 to a x86-64 build; 2) somehow a config changed
between the builds;
3) when preparing the patch I rebased on upstream between the builds.
Checking (1), no... that's in the ~400k range. So no idea, sorry.
I was worried you'd say you compiler just behaves differently. To
eliminate this option it would still be good to double check if you can
find the time.
So I think the only useful thing in this patch is to make the array to
grow automatically. Or maybe not even that?
I really liked that and then started thinking that it can still sneak up
a mistake if one changes the type of the member and forgets to change
the type in size calculation BITS_PER_TYPE. So I ended up a little less
sure. Could the calculation self-reference the struct member?
Regards,
Tvrtko
Lucas De Marchi
Regards,
Tvrtko
Now on 64 bits we have only one long as opposed to 2 u32:
$ pahole -C intel_runtime_info drivers/gpu/drm/i915/i915.ko
struct intel_runtime_info {
long unsigned int platform_mask[1]; /* 0 8 */
...
}
On 32 bits we still have the same thing as before:
$ size drivers/gpu/drm/i915/i915.ko*
text data bss dec hex filename
1489839 324852816 1525140 174594 drivers/gpu/drm/i915/i915.ko
1489839 324852816 1525140 174594 drivers/gpu/drm/i915/i915.ko.old
Besides reducing the code on x86-64 now the array size is automatically
calculated and we don't have to worry about extending it anymore.
v2: fix sparse and checkpatch warnings
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 7 +++
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ab4826921f7..9fe765ffe878 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2309,10 +2309,6 @@ __platform_mask_index(const struct intel_runtime_info
*info,
const unsigned int pbits =
BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
- /* Expand the platform_mask array if this fails. */
- BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
- pbits * ARRAY_SIZE(info->platform_mask));
-
return p / pbits;
}
@@ -2354,7 +2350,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
const unsigned int pi = __platform_mask_index(info, p);
const unsigned int pb = __platform_mask_bit(info, p);
const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
- const u32 mask = info->platform_mask[pi];
+ const unsigned long mask = info->platform_mask[pi];
BUILD_BUG_ON(!__builtin_constant_p(p));
BUILD_BUG_ON(!__builtin_constant_p(s));
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0e579f158016..2f5ca2b6f094 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -214,11 +214,10 @@ struct intel_runtime_info {
* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
* into single runtime conditionals, and also to provide groundwork
* for future per platform, or per SKU build optimizations.
- *
- * Array can be extended when necessary if the corresponding
- * BUILD_BUG_ON is hit.
*/
- u32 platform_mask[2];
+ unsigned long platform_mask[DIV_ROUND_UP(INTEL_MAX_PLATFORMS,
+ BITS_PER_TYPE(unsigned long)
+ - INTEL_SUBPLATFORM_BITS)];
u16 device_id;
___
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___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/16] drm/fb-helper: Remove unused gamma_size variable
Den 26.03.2019 19.23, skrev Daniel Vetter:
> On Tue, Mar 26, 2019 at 06:55:31PM +0100, Noralf Trønnes wrote:
>> The gamma_size variable has not been used since
>> commit 4abe35204af8 ("drm/kms/fb: use slow work mechanism for normal hotplug
>> also.")
>>
>> While in the area move a comment back to its code block.
>> They got separated by
>> commit d50ba256b5f1 ("drm/kms: start adding command line interface using
>> fb.").
>>
>> Signed-off-by: Noralf Trønnes
>
> Reviewed-by: Daniel Vetter
Thanks, patches 1 & 2 applied to drm-misc-next.
Noralf.
>
>> ---
>> drivers/gpu/drm/drm_fb_helper.c | 6 +-
>> 1 file changed, 1 insertion(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_fb_helper.c
>> b/drivers/gpu/drm/drm_fb_helper.c
>> index 04d23cb430bf..eea15465da7a 100644
>> --- a/drivers/gpu/drm/drm_fb_helper.c
>> +++ b/drivers/gpu/drm/drm_fb_helper.c
>> @@ -1873,7 +1873,6 @@ static int drm_fb_helper_single_fb_probe(struct
>> drm_fb_helper *fb_helper,
>> int crtc_count = 0;
>> int i;
>> struct drm_fb_helper_surface_size sizes;
>> -int gamma_size = 0;
>> int best_depth = 0;
>>
>> memset(&sizes, 0, sizeof(struct drm_fb_helper_surface_size));
>> @@ -1889,7 +1888,6 @@ static int drm_fb_helper_single_fb_probe(struct
>> drm_fb_helper *fb_helper,
>> if (preferred_bpp != sizes.surface_bpp)
>> sizes.surface_depth = sizes.surface_bpp = preferred_bpp;
>>
>> -/* first up get a count of crtcs now in use and new min/maxes
>> width/heights */
>> drm_fb_helper_for_each_connector(fb_helper, i) {
>> struct drm_fb_helper_connector *fb_helper_conn =
>> fb_helper->connector_info[i];
>> struct drm_cmdline_mode *cmdline_mode;
>> @@ -1969,6 +1967,7 @@ static int drm_fb_helper_single_fb_probe(struct
>> drm_fb_helper *fb_helper,
>> sizes.surface_depth = best_depth;
>> }
>>
>> +/* first up get a count of crtcs now in use and new min/maxes
>> width/heights */
>> crtc_count = 0;
>> for (i = 0; i < fb_helper->crtc_count; i++) {
>> struct drm_display_mode *desired_mode;
>> @@ -1991,9 +1990,6 @@ static int drm_fb_helper_single_fb_probe(struct
>> drm_fb_helper *fb_helper,
>> x = fb_helper->crtc_info[i].x;
>> y = fb_helper->crtc_info[i].y;
>>
>> -if (gamma_size == 0)
>> -gamma_size =
>> fb_helper->crtc_info[i].mode_set.crtc->gamma_size;
>> -
>> sizes.surface_width = max_t(u32, desired_mode->hdisplay + x,
>> sizes.surface_width);
>> sizes.surface_height = max_t(u32, desired_mode->vdisplay + y,
>> sizes.surface_height);
>>
>> --
>> 2.20.1
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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Re: [Intel-gfx] [PATCH 16/16] drm/vc4: Call drm_dev_register() after all setup is done
Den 27.03.2019 17.36, skrev Eric Anholt: > Noralf Trønnes writes: > >> drm_dev_register() initializes internal clients like bootsplash as the >> last thing it does, so all setup needs to be done at this point. >> >> Fix by calling vc4_kms_load() before registering. >> Also check the error code returned from that function. >> >> Cc: Eric Anholt >> Signed-off-by: Noralf Trønnes > > Reviewed-by: Eric Anholt > Applied to drm-misc-next. Noralf. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: add intel_uncore_init_early
Quoting Patchwork (2019-04-03 09:49:14) > == Series Details == > > Series: series starting with [CI,1/2] drm/i915: add intel_uncore_init_early > URL : https://patchwork.freedesktop.org/series/58891/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_5856_full -> Patchwork_12660_full > > > Summary > --- > > **WARNING** > > Minor unknown changes coming with Patchwork_12660_full need to be verified > manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_12660_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. No worries. Thanks for the patch, pushed. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init
On Wed, Apr 03, 2019 at 09:13:59AM +0100, Tvrtko Ursulin wrote: > P.S. Also the assert about no junk in high bits did not fire in CI which > would suggest stack slot was either zero or no more than three low bits > sets. Strange luck. GCC happens to initialize it to zero. It's also why GCC didn't trigger an uninialized variable warning. The bug was reported to GCC years ago. regards, dan carpenter ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: add intel_uncore_init_early
== Series Details == Series: series starting with [CI,1/2] drm/i915: add intel_uncore_init_early URL : https://patchwork.freedesktop.org/series/58891/ State : success == Summary == CI Bug Log - changes from CI_DRM_5856_full -> Patchwork_12660_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_12660_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12660_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12660_full: ### IGT changes ### Warnings * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render: - shard-iclb: SKIP [fdo#109280] -> INCOMPLETE Known issues Here are the changes found in Patchwork_12660_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_store@cachelines-bsd2: - shard-glk: NOTRUN -> SKIP [fdo#109271] +20 * igt@gem_mmap_gtt@hang: - shard-iclb: PASS -> FAIL [fdo#109677] * igt@gem_softpin@noreloc-s3: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@i915_pm_rpm@pm-tiling: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@kms_atomic_transition@3x-modeset-transitions: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +8 * igt@kms_available_modes_crc@available_mode_test_crc: - shard-snb: NOTRUN -> FAIL [fdo#106641] * igt@kms_busy@basic-modeset-e: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: PASS -> FAIL [fdo#104873] * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@2x-wf_vblank-ts-check: - shard-snb: NOTRUN -> SKIP [fdo#109271] +73 * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-apl: PASS -> FAIL [fdo#102887] / [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#103167] +5 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +21 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] * igt@kms_frontbuffer_tracking@psr-suspend: - shard-iclb: PASS -> FAIL [fdo#109247] +7 * igt@kms_lease@atomic_implicit_crtc: - shard-kbl: NOTRUN -> FAIL [fdo#110279] - shard-skl: NOTRUN -> FAIL [fdo#110279] * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +2 - shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590] * igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@cursor_render: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: PASS -> SKIP [fdo#109441] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] - shard-kbl: PASS -> FAIL [fdo#99912] * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9 * igt@kms_vblank@pipe-c-ts-continuation-dpms-rpm: - shard-apl: PASS -> FAIL [fdo#104894] * igt@perf@blocking: - shard-iclb: PASS -> FAIL [fdo#108587] * igt@perf_pmu@busy-accuracy-98-vcs1: - shard-skl: NOTRUN -> SKIP [fdo#109271] +100 Possible fixes * igt@gem_create@create-clear: - shard-snb: INCOMPLETE [fdo#105411] -> PASS * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: - shard-glk: FAIL [fdo#106509] / [fdo#107409] -> PASS * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-iclb: FAIL [fdo#103355] -> PASS * igt@km
Re: [Intel-gfx] [PATCH] drm/i915: add immutable zpos plane properties
Quoting Simon Ser (2019-04-02 17:36:33) > On Tuesday, April 2, 2019 3:35 PM, Joonas Lahtinen > wrote: > > Quoting Simon Ser (2019-03-30 00:19:25) > > > > > From: emersion cont...@emersion.fr > > > > Please fix your From: field. > > Gah. > > > > This adds basic immutable support for the zpos property. The zpos > > > increases > > > from bottom to top: primary, sprites, cursor. > > > Signed-off-by: Simon Ser cont...@emersion.fr > > > > This is just Ville's patch rebased, so it's incorrect to strip the S-o-b, > > please read: > > > > https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin > > Honestly I wasn't sure what to do, especially considering that I've > edited most of the lines. I tried to ask on IRC but I got no reply. > > Thanks for clearing that up! So just to be sure I don't mess up v2: > > - This is Ville's patch so he definitely should be the author. > - Ville's S-o-b should definitely be kept as-is. > - Now, should I add my own S-o-b? It seems like I should. > - Co-Authored-By probably doesn't make sense here. > - I originally wanted to add my Reviewed-by tag, but it probably > wouldn't make sense if I have a S-o-b tag. > > Is this correct? You should git am (maybe with --3way) the original patch, and add a change log entry explaining what you modified about the patch and finally add your own S-o-b. That way the From: will correctly point to the original patch owner and it is clear what modifications you made. For review just poke somebody working in that area (git blame is your friend here). Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: FBC needs vblank before enable / disable. (rev6)
== Series Details == Series: drm/i915: FBC needs vblank before enable / disable. (rev6) URL : https://patchwork.freedesktop.org/series/58843/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12671 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12671 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12671, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/58843/revisions/6/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12671: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-no-display: - fi-icl-y: NOTRUN -> INCOMPLETE Known issues Here are the changes found in Patchwork_12671 that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@basic-read: - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] +57 * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744] * igt@i915_selftest@live_uncore: - fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110210] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@runner@aborted: - fi-skl-iommu: NOTRUN -> FAIL [fdo#104108] / [fdo#108602] Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_module_load@reload: - fi-icl-y: INCOMPLETE [fdo#107713] -> PASS * igt@i915_selftest@live_hangcheck: - fi-icl-u3: INCOMPLETE [fdo#108569] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 Participating hosts (46 -> 41) -- Additional (2): fi-hsw-4770r fi-snb-2600 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-icl-u2 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus Build changes - * Linux: CI_DRM_5860 -> Patchwork_12671 CI_DRM_5860: 837ba3cd997b59e53903ba29f4fe65c81f86f1e9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4923: 6285eec4f3b8f21833d9d2d852883569d6551822 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12671: 7ee6b083d8fad8d032a8c5be119475080f38b4b0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7ee6b083d8fa drm/i915: FBC needs vblank before enable / disable. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12671/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use lockdep_pin_lock() over the construction of the request
During request construction, we take the timeline->mutex to ensure
exclusive access to the ringbuffer (for command emission) and the
timeline itself (for command ordering). The timeline->mutex should not
be dropped by callers until we release it in i915_request_add().
lockdep provides a pin/unpin lock facility to detect accidental unlocks
inside critical sections, so put it to use for request construction.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 5 +
drivers/gpu/drm/i915/i915_request.h | 10 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 82094b9f5ba7..7f8a4eba98b8 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -751,7 +751,10 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->infix = rq->ring->emit; /* end of header; start of user payload */
/* Check that we didn't interrupt ourselves with a new request */
+ lockdep_assert_held(&rq->timeline->mutex);
GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno);
+ rq->cookie = lockdep_pin_lock(&rq->timeline->mutex);
+
return rq;
err_unwind:
@@ -1070,6 +1073,8 @@ void i915_request_add(struct i915_request *request)
engine->name, request->fence.context, request->fence.seqno);
lockdep_assert_held(&request->timeline->mutex);
+ lockdep_unpin_lock(&request->timeline->mutex, request->cookie);
+
trace_i915_request_add(request);
/*
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index cd6c130964cd..875be6f71412 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -26,6 +26,7 @@
#define I915_REQUEST_H
#include
+#include
#include "i915_gem.h"
#include "i915_scheduler.h"
@@ -120,6 +121,15 @@ struct i915_request {
*/
unsigned long rcustate;
+ /*
+* We pin the timeline->mutex while constructing the request to
+* ensure that no caller accidentally drops it during construction.
+* The timeline->mutex must be held to ensure that only this caller
+* can use the ring and manipulate the associated timeline during
+* construction.
+*/
+ struct pin_cookie cookie;
+
/*
* Fences for the various phases in the request's lifetime.
*
--
2.20.1
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Re: [Intel-gfx] [PATCH v2] drm/i915: use unsigned long for platform_mask
On Tue, Apr 2, 2019 at 11:58 PM Tvrtko Ursulin
wrote:
>
>
> On 03/04/2019 02:46, Lucas De Marchi wrote:
> > No reason to stick to u32 for platform mask if we can just use more bits
> > on 64 bit platforms.
> >
> > $ size drivers/gpu/drm/i915/i915.ko*
> > text data bss dec hex filename
> > 1884779 413345408 1931521 1d7901 drivers/gpu/drm/i915/i915.ko
> > 1886693 413585408 1933459 1d8093
> > drivers/gpu/drm/i915/i915.ko.old
>
> How did you get such a large difference, and decrease even? Could you
> check in the code what is happening? Because I get an increase with this
> patch:
>
> textdata bss dec hex filename
> 1905314 439037424 1956641 1ddb21 i915.ko.orig
> 1905796 439037424 1957123 1ddd03 i915.ko.patch
the only explanation I really have is that my measurement was bogus.
Some possible explanations...
1) I compared a i386 to a x86-64 build; 2) somehow a config changed
between the builds;
3) when preparing the patch I rebased on upstream between the builds.
Checking (1), no... that's in the ~400k range. So no idea, sorry.
So I think the only useful thing in this patch is to make the array to
grow automatically. Or maybe not even that?
Lucas De Marchi
>
> Regards,
>
> Tvrtko
>
> >
> > Now on 64 bits we have only one long as opposed to 2 u32:
> >
> > $ pahole -C intel_runtime_info drivers/gpu/drm/i915/i915.ko
> > struct intel_runtime_info {
> > long unsigned int platform_mask[1]; /* 0 8 */
> > ...
> > }
> >
> > On 32 bits we still have the same thing as before:
> > $ size drivers/gpu/drm/i915/i915.ko*
> > text data bss dec hex filename
> > 1489839 324852816 1525140 174594 drivers/gpu/drm/i915/i915.ko
> > 1489839 324852816 1525140 174594
> > drivers/gpu/drm/i915/i915.ko.old
> >
> > Besides reducing the code on x86-64 now the array size is automatically
> > calculated and we don't have to worry about extending it anymore.
> >
> > v2: fix sparse and checkpatch warnings
> >
> > Signed-off-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 6 +-
> > drivers/gpu/drm/i915/intel_device_info.h | 7 +++
> > 2 files changed, 4 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 0ab4826921f7..9fe765ffe878 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2309,10 +2309,6 @@ __platform_mask_index(const struct
> > intel_runtime_info *info,
> > const unsigned int pbits =
> > BITS_PER_TYPE(info->platform_mask[0]) -
> > INTEL_SUBPLATFORM_BITS;
> >
> > - /* Expand the platform_mask array if this fails. */
> > - BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> > - pbits * ARRAY_SIZE(info->platform_mask));
> > -
> > return p / pbits;
> > }
> >
> > @@ -2354,7 +2350,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > const unsigned int pi = __platform_mask_index(info, p);
> > const unsigned int pb = __platform_mask_bit(info, p);
> > const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
> > - const u32 mask = info->platform_mask[pi];
> > + const unsigned long mask = info->platform_mask[pi];
> >
> > BUILD_BUG_ON(!__builtin_constant_p(p));
> > BUILD_BUG_ON(!__builtin_constant_p(s));
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index 0e579f158016..2f5ca2b6f094 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -214,11 +214,10 @@ struct intel_runtime_info {
> >* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
> >* into single runtime conditionals, and also to provide groundwork
> >* for future per platform, or per SKU build optimizations.
> > - *
> > - * Array can be extended when necessary if the corresponding
> > - * BUILD_BUG_ON is hit.
> >*/
> > - u32 platform_mask[2];
> > + unsigned long platform_mask[DIV_ROUND_UP(INTEL_MAX_PLATFORMS,
> > + BITS_PER_TYPE(unsigned long)
> > + - INTEL_SUBPLATFORM_BITS)];
> >
> > u16 device_id;
> >
> >
>
> ___
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--
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Re: [Intel-gfx] [PATCH] drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init
On 03/04/2019 08:13, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-03 07:44:07)
From: Tvrtko Ursulin
Mask need to be initialized to zero since device id checks may not match.
Signed-off-by: Tvrtko Ursulin
Reported-by: Dan Carpenter
Fixes: 805446c8347c ("drm/i915: Introduce concept of a sub-platform")
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Jose Souza
Cc: Ville Syrjälä
Cc: Paulo Zanoni
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Dan Carpenter
Bots are doing a better job than me, but still
Reviewed-by: Chris Wilson
It's my bad, probably introduced due various refactoring of the patch
itself. Since I definitely remember changing the mask initialization
back and forth.
No huge harm done since caught quickly by this very valuable service
provided by Dan.
Regards,
Tvrtko
P.S. Also the assert about no junk in high bits did not fire in CI which
would suggest stack slot was either zero or no more than three low bits
sets. Strange luck.
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: FBC needs vblank before enable / disable. (rev6)
== Series Details == Series: drm/i915: FBC needs vblank before enable / disable. (rev6) URL : https://patchwork.freedesktop.org/series/58843/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7ee6b083d8fa drm/i915: FBC needs vblank before enable / disable. -:53: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #53: FILE: drivers/gpu/drm/i915/intel_display.c:13432: + intel_wait_for_vblank(dev_priv, + intel_crtc->pipe); total: 0 errors, 0 warnings, 1 checks, 23 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init
== Series Details == Series: drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init URL : https://patchwork.freedesktop.org/series/58921/ State : success == Summary == CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12670 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58921/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12670 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_workarounds@basic-read: - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] +57 * igt@i915_selftest@live_contexts: - fi-icl-y: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_module_load@reload: - fi-icl-y: INCOMPLETE [fdo#107713] -> PASS * igt@i915_selftest@live_hangcheck: - fi-icl-u3: INCOMPLETE [fdo#108569] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 Participating hosts (46 -> 41) -- Additional (2): fi-hsw-4770r fi-snb-2600 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-j1900 fi-byt-squawks fi-icl-u2 fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5860 -> Patchwork_12670 CI_DRM_5860: 837ba3cd997b59e53903ba29f4fe65c81f86f1e9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4923: 6285eec4f3b8f21833d9d2d852883569d6551822 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12670: f7bf7a1e62a83500e47beaab3973ff1cffa60984 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f7bf7a1e62a8 drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12670/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/22] drm/i915: Pass intel_context to i915_request_create()
Quoting Chris Wilson (2019-04-03 08:54:41)
> Quoting Tvrtko Ursulin (2019-04-02 14:17:30)
> >
> > On 25/03/2019 09:03, Chris Wilson wrote:
> > > @@ -727,17 +695,19 @@ i915_request_alloc(struct intel_engine_cs *engine,
> > > struct i915_gem_context *ctx)
> > > if (ret)
> > > goto err_unwind;
> > >
> > > - ret = engine->request_alloc(rq);
> > > + ret = rq->engine->request_alloc(rq);
> > > if (ret)
> > > goto err_unwind;
> > >
> > > + rq->infix = rq->ring->emit; /* end of header; start of user payload
> > > */
> > > +
> > > /* Keep a second pin for the dual retirement along engine and ring
> > > */
> > > __intel_context_pin(ce);
> > > -
> > > - rq->infix = rq->ring->emit; /* end of header; start of user payload
> > > */
> > > + atomic_inc(&i915->gt.active_requests);
> >
> > Oh I hate this..
> >
> > >
> > > /* Check that we didn't interrupt ourselves with a new request */
> > > GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno);
> > > + lockdep_assert_held(&tl->mutex);
> > > return rq;
>
> [snip]
>
> > > + /*
> > > + * Pinning the contexts may generate requests in order to acquire
> > > + * GGTT space, so do this first before we reserve a seqno for
> > > + * ourselves.
> > > + */
> > > + ce = intel_context_pin(ctx, engine);
> > > + if (IS_ERR(ce))
> > > + return ERR_CAST(ce);
> > > +
> > > + i915_gem_unpark(i915);
> > > +
> > > + rq = i915_request_create(ce);
> > > +
> > > + i915_gem_park(i915);
> >
> > ... because it is so anti-self-documenting.
> >
> > Maybe we could have something like:
> >
> > __i915_gem_unpark(...)
> > {
> > GEM_BUG_ON(!atomic_read(active_requests));
> > atomic_inc(active_requests);
> > }
> >
> > Similar to __intel_context_pin, just so it is more obvious what the code
> > is doing.
>
> But not here though. Since this is the path that has to wake up the
> device itself, pin the context (eventually run retirement, handle
> allocation fallback) and not presume the caller already has (or will).
>
> Inside i915_require_create we do have the assert that the device is
> awake, which should be has GT wakeref instead. (Note, not GEM wakeref at
> this point, that's the troubling bit.)
>
> Post snip: Saw the connected argument.
The problem with that is no, we are not putting a __i915_gem_unpark()
into i915_request_create. At this point, we care about the gt.wakeref.
Maybe I should take another shot at splitting the GEM wakeref from GT.
i915_gem_runtime_pm_get()
i915_gt_unpark()
i915_gt_park()
i915_gem_runtime_pm_put()
-Chris
___
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Re: [Intel-gfx] [PATCH 06/22] drm/i915: Pass intel_context to i915_request_create()
Quoting Tvrtko Ursulin (2019-04-02 14:17:30)
>
> On 25/03/2019 09:03, Chris Wilson wrote:
> > @@ -727,17 +695,19 @@ i915_request_alloc(struct intel_engine_cs *engine,
> > struct i915_gem_context *ctx)
> > if (ret)
> > goto err_unwind;
> >
> > - ret = engine->request_alloc(rq);
> > + ret = rq->engine->request_alloc(rq);
> > if (ret)
> > goto err_unwind;
> >
> > + rq->infix = rq->ring->emit; /* end of header; start of user payload */
> > +
> > /* Keep a second pin for the dual retirement along engine and ring */
> > __intel_context_pin(ce);
> > -
> > - rq->infix = rq->ring->emit; /* end of header; start of user payload */
> > + atomic_inc(&i915->gt.active_requests);
>
> Oh I hate this..
>
> >
> > /* Check that we didn't interrupt ourselves with a new request */
> > GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno);
> > + lockdep_assert_held(&tl->mutex);
> > return rq;
[snip]
> > + /*
> > + * Pinning the contexts may generate requests in order to acquire
> > + * GGTT space, so do this first before we reserve a seqno for
> > + * ourselves.
> > + */
> > + ce = intel_context_pin(ctx, engine);
> > + if (IS_ERR(ce))
> > + return ERR_CAST(ce);
> > +
> > + i915_gem_unpark(i915);
> > +
> > + rq = i915_request_create(ce);
> > +
> > + i915_gem_park(i915);
>
> ... because it is so anti-self-documenting.
>
> Maybe we could have something like:
>
> __i915_gem_unpark(...)
> {
> GEM_BUG_ON(!atomic_read(active_requests));
> atomic_inc(active_requests);
> }
>
> Similar to __intel_context_pin, just so it is more obvious what the code
> is doing.
But not here though. Since this is the path that has to wake up the
device itself, pin the context (eventually run retirement, handle
allocation fallback) and not presume the caller already has (or will).
Inside i915_require_create we do have the assert that the device is
awake, which should be has GT wakeref instead. (Note, not GEM wakeref at
this point, that's the troubling bit.)
Post snip: Saw the connected argument.
-Chris
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev3)
== Series Details == Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev3) URL : https://patchwork.freedesktop.org/series/58912/ State : success == Summary == CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12669 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58912/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_12669 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_workarounds@basic-read: - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] +57 * igt@i915_selftest@live_contexts: - fi-icl-y: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1 Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_module_load@reload: - fi-icl-y: INCOMPLETE [fdo#107713] -> PASS * igt@i915_selftest@live_hangcheck: - fi-icl-u3: INCOMPLETE [fdo#108569] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 Participating hosts (46 -> 41) -- Additional (2): fi-hsw-4770r fi-snb-2600 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-icl-u2 fi-kbl-guc fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5860 -> Patchwork_12669 CI_DRM_5860: 837ba3cd997b59e53903ba29f4fe65c81f86f1e9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4923: 6285eec4f3b8f21833d9d2d852883569d6551822 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12669: 464216adb29404090c53b7f8f39e2c511eb4e3dd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 464216adb294 drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12669/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for linux-next: build failure after merge of the drm-misc tree (rev2)
== Series Details == Series: linux-next: build failure after merge of the drm-misc tree (rev2) URL : https://patchwork.freedesktop.org/series/58857/ State : success == Summary == CI Bug Log - changes from CI_DRM_5856_full -> Patchwork_12658_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12658_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vecs0-s3: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@gem_exec_schedule@preempt-self-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] * igt@gem_exec_store@cachelines-bsd2: - shard-glk: NOTRUN -> SKIP [fdo#109271] +20 * igt@gem_pwrite@stolen-normal: - shard-skl: NOTRUN -> SKIP [fdo#109271] +93 * igt@gem_stolen@stolen-no-mmap: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@i915_pm_rpm@gem-mmap-cpu: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@system-suspend-execbuf: - shard-iclb: PASS -> DMESG-WARN [fdo#109638] * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@kms_available_modes_crc@available_mode_test_crc: - shard-snb: NOTRUN -> FAIL [fdo#106641] * igt@kms_busy@basic-modeset-e: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-oldfb-render-e: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9 * igt@kms_concurrent@pipe-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@2x-wf_vblank-ts-check: - shard-snb: NOTRUN -> SKIP [fdo#109271] +73 * igt@kms_force_connector_basic@force-connector-state: - shard-iclb: NOTRUN -> SKIP [fdo#109285] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render: - shard-iclb: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +1 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +24 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] * igt@kms_frontbuffer_tracking@fbcpsr-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render: - shard-skl: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-iclb: PASS -> FAIL [fdo#109247] +23 * igt@kms_lease@atomic_implicit_crtc: - shard-kbl: NOTRUN -> FAIL [fdo#110279] - shard-skl: NOTRUN -> FAIL [fdo#110279] * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +2 - shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590] * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: PASS -> SKIP [fdo#109441] +1 * igt@kms_psr@suspend: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: PASS -> DMESG-FAIL [fdo#105763] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] - shard-iclb: NOTRUN -> FAIL [fdo#99912] - shard-kbl: PASS -> FAIL [fdo#99912] * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9 * igt@perf@blocking: - shard-iclb: PASS -> FAIL [fdo#108587] +1 Possible fixes * igt@gem_create@create-clear: - shard-snb: INCOMPLETE [fdo#105411] -> PASS * igt@gem_ppgtt@blt-vs-render-ctxn: - shard-iclb: INCOMPLETE [fdo#109801] -> PASS * igt@gem_tiled_swapping@non-threaded: - shard-iclb: DMESG-WARN [fdo#108686] -> PASS * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_create: Do not build create-clear for MIPS
On 02/04/2019 09:35, Petri Latvala wrote:
> On Mon, Apr 01, 2019 at 04:39:24PM +0200, Guillaume Tucker wrote:
>> The MIPS architecture doesn't provide the hardware atomics that are
>> required for the "create-clear" sub-test such as
>> __sync_add_and_fetch(). As a simple and pragmatic solution, disable
>> this sub-test when building for MIPS. A better approach would be to
>> add a fallback implementation for these operations.
>>
>> Fixes: 6727e17c00b2 ("i915/gem_create: Verify that all new objects are
>> clear")
>> Signed-off-by: Guillaume Tucker
>> ---
>> tests/i915/gem_create.c | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
>> index 2a861ca8a7ec..8a48496e6c19 100644
>> --- a/tests/i915/gem_create.c
>> +++ b/tests/i915/gem_create.c
>> @@ -142,6 +142,7 @@ static void invalid_nonaligned_size(int fd)
>> gem_close(fd, handle);
>> }
>>
>> +#if !defined(__mips__) /* MIPS doesn't provide the required hardware
>> atomics */
>> static uint64_t get_npages(uint64_t *global, uint64_t npages)
>> {
>> uint64_t try, old, max;
>> @@ -208,6 +209,7 @@ static void always_clear(int i915, int timeout)
>> for (int i = 0; i < ncpus; i++)
>> pthread_join(thread[i], NULL);
>> }
>> +#endif /* !defined(__mips__) */
>>
>> igt_main
>> {
>> @@ -231,6 +233,8 @@ igt_main
>> igt_subtest("create-invalid-nonaligned")
>> invalid_nonaligned_size(fd);
>>
>> +#if !defined(__mips__)
>> igt_subtest("create-clear")
>> always_clear(fd, 30);
>> +#endif
>> }
>
>
> It's a bit ugly. I wonder how much work a fallback mechanism would be?
Sorry I should have sent this as RFC.
> The test is i915 specific and using those on non-x86 architectures
> sounds silly. We could limit building tests/i915/* only if
> host_machine.cpu_family() is x86 or x86_64. But that requires
> revisiting this issue if ever the day comes when i915 can be used on
> other architectures *cough*.
Right, I thought it might not be worth implementing fallback
functions if there is no MIPS hardware on which this test can be
run. Still it would be a shame to leave i-g-t failing to build
on MIPS.
> Apropos, compile-testing on MIPS in gitlab-CI?
This issue was actually hit while building the KernelCI root file
system with i-g-t tests. We're starting to add some MIPS
platforms, so running the generic DRM/KMS tests on them might
start to make sense at some point (cc khilman).
And yes I guess it seems worth considering adding MIPS to
Gitlab-CI as it only appears to be covering x86, armhf and
arm64 (although I did fix an armhf build issue a few weeks ago).
> A compile-tested-only fallback mechanism suggestion, and a bad spot
> for placing the fallback functions:
Thanks, I agree that does look like a sustainable way forward.
We don't quite have a MIPS platform to test that yet in KernelCI,
so hopefully QEMU can be used to test a fallback implementation.
I guess adding placeholder functions as in your example with
igt_assert_f() statements would just add some technical debt with
little added benefit, so I'll work on a v2 with something that
works. Meanwhile we'll just skip i-g-t KernelCI builds on MIPS.
> diff --git a/meson.build b/meson.build
> index 557400a5..0552e858 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -246,6 +246,9 @@ endif
> have = cc.has_function('memfd_create', prefix : '''#include ''',
> args : '-D_GNU_SOURCE')
> config.set10('HAVE_MEMFD_CREATE', have)
>
> +have_atomics = cc.compiles('void f() { int x, y; __sync_add_and_fetch(&x,
> y); }')
> +config.set10('HAVE_BUILTIN_ATOMICS', have_atomics)
> +
> add_project_arguments('-D_GNU_SOURCE', language : 'c')
> add_project_arguments('-include', 'config.h', language : 'c')
>
> diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
> index 2a861ca8..615bb475 100644
> --- a/tests/i915/gem_create.c
> +++ b/tests/i915/gem_create.c
> @@ -62,6 +62,18 @@ IGT_TEST_DESCRIPTION("This is a test for the extended &
> old gem_create ioctl,"
>" that includes allocation of object from stolen memory"
>" and shmem.");
>
> +#if !HAVE_BUILTIN_ATOMICS
> +int __sync_add_and_fetch(void *ptr, uint64_t val)
> +{
> + igt_assert_f(false, "Don't have builtin atomics\n");
> +}
> +
> +int __sync_val_compare_and_swap(void *ptr, uint64_t old, uint64_t new)
> +{
> + igt_assert_f(false, "Don't have builtin atomics\n");
> +}
> +#endif
> +
> #define CLEAR(s) memset(&s, 0, sizeof(s))
> #define PAGE_SIZE 4096
Thanks,
Guillaume
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[Intel-gfx] [PATCH] drm/i915: FBC needs vblank before enable / disable.
From: Kiran Kumar S
As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.
In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final segment of the frame as a result of the
missing last pixel indication. As a result of this, we're seeing
corrupted cache line/compression indicators after FBC re-enables
which causes underruns or corruption when they're used to decompress.
WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC
In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.
Signed-off-by: Kiran Kumar S
---
drivers/gpu/drm/i915/intel_display.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..97c9af921ae1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13207,8 +13207,12 @@ static void intel_update_crtc(struct drm_crtc *crtc,
if (pipe_config->update_pipe && !pipe_config->enable_fbc)
intel_fbc_disable(intel_crtc);
- else if (new_plane_state)
+ else if (new_plane_state) {
+ /* Display WA #1200: GLK */
+ if (IS_GEMINILAKE(dev_priv))
+ intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
+ }
intel_begin_crtc_commit(crtc, old_crtc_state);
@@ -13419,6 +13423,10 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
dev_priv->display.crtc_disable(old_intel_crtc_state,
state);
intel_crtc->active = false;
+ /* Display WA #1200: GLK */
+ if (IS_GEMINILAKE(dev_priv))
+ intel_wait_for_vblank(dev_priv,
+ intel_crtc->pipe);
intel_fbc_disable(intel_crtc);
intel_disable_shared_dpll(old_intel_crtc_state);
--
2.7.4
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Re: [Intel-gfx] [PATCH] drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init
Quoting Tvrtko Ursulin (2019-04-03 07:44:07)
> From: Tvrtko Ursulin
>
> Mask need to be initialized to zero since device id checks may not match.
>
> Signed-off-by: Tvrtko Ursulin
> Reported-by: Dan Carpenter
> Fixes: 805446c8347c ("drm/i915: Introduce concept of a sub-platform")
> Cc: Tvrtko Ursulin
> Cc: Chris Wilson
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> Cc: Jose Souza
> Cc: Ville Syrjälä
> Cc: Paulo Zanoni
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Dan Carpenter
Bots are doing a better job than me, but still
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH] drm/i915: FBC needs vblank before enable / disable.
From: Kiran Kumar S
As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.
In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final segment of the frame as a result of the
missing last pixel indication. As a result of this, we're seeing
corrupted cache line/compression indicators after FBC re-enables
which causes underruns or corruption when they're used to decompress.
WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC
In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.
Signed-off-by: Kiran Kumar S
---
drivers/gpu/drm/i915/intel_display.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..90360dfc674b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13207,8 +13207,12 @@ static void intel_update_crtc(struct drm_crtc *crtc,
if (pipe_config->update_pipe && !pipe_config->enable_fbc)
intel_fbc_disable(intel_crtc);
- else if (new_plane_state)
+ else if (new_plane_state) {
+ /* Display WA #1200: GLK */
+ if (IS_GEMINILAKE(dev_priv))
+ intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
+ }
intel_begin_crtc_commit(crtc, old_crtc_state);
@@ -13419,6 +13423,8 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
dev_priv->display.crtc_disable(old_intel_crtc_state,
state);
intel_crtc->active = false;
+ /* Display WA #1200: GLK */
+ intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
intel_fbc_disable(intel_crtc);
intel_disable_shared_dpll(old_intel_crtc_state);
--
2.7.4
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: FBC needs vblank before enable / disable. (rev4)
== Series Details == Series: drm/i915: FBC needs vblank before enable / disable. (rev4) URL : https://patchwork.freedesktop.org/series/58843/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12668 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12668 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12668, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/58843/revisions/4/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12668: ### IGT changes ### Possible regressions * igt@debugfs_test@read_all_entries: - fi-byt-j1900: PASS -> DMESG-WARN * igt@gem_ctx_create@basic: - fi-icl-y: PASS -> INCOMPLETE * igt@gem_exec_suspend@basic-s3: - fi-kbl-r: PASS -> DMESG-WARN - fi-skl-lmem:PASS -> DMESG-WARN - fi-bdw-gvtdvm: PASS -> DMESG-WARN - fi-skl-iommu: PASS -> DMESG-WARN - fi-icl-u2: PASS -> DMESG-WARN - fi-bsw-kefka: PASS -> DMESG-WARN - fi-byt-clapper: PASS -> DMESG-WARN - fi-skl-gvtdvm: PASS -> DMESG-WARN - fi-skl-6600u: PASS -> DMESG-WARN * igt@runner@aborted: - fi-ilk-650: NOTRUN -> FAIL - fi-pnv-d510:NOTRUN -> FAIL - fi-bdw-gvtdvm: NOTRUN -> FAIL - fi-hsw-peppy: NOTRUN -> FAIL - fi-icl-u2: NOTRUN -> FAIL - fi-gdg-551: NOTRUN -> FAIL - fi-snb-2520m: NOTRUN -> FAIL - fi-hsw-4770:NOTRUN -> FAIL - fi-whl-u: NOTRUN -> FAIL - fi-icl-u3: NOTRUN -> FAIL - fi-ivb-3770:NOTRUN -> FAIL - fi-byt-j1900: NOTRUN -> FAIL - fi-blb-e6850: NOTRUN -> FAIL - fi-bsw-kefka: NOTRUN -> FAIL - fi-hsw-4770r: NOTRUN -> FAIL - fi-byt-clapper: NOTRUN -> FAIL - fi-bdw-5557u: NOTRUN -> FAIL - fi-bwr-2160:NOTRUN -> FAIL - fi-byt-n2820: NOTRUN -> FAIL - fi-elk-e7500: NOTRUN -> FAIL Known issues Here are the changes found in Patchwork_12668 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-icl-u3: PASS -> DMESG-WARN [fdo#109638] * igt@runner@aborted: - fi-cfl-8109u: NOTRUN -> FAIL [k.org#202107] / [k.org#202109] - fi-bxt-j4205: NOTRUN -> FAIL [fdo#109516] - fi-skl-iommu: NOTRUN -> FAIL [fdo#104108] - fi-cfl-guc: NOTRUN -> FAIL [k.org#202107] / [k.org#202109] - fi-kbl-7567u: NOTRUN -> FAIL [fdo#108903] / [fdo#108904] / [fdo#108905] - fi-skl-guc: NOTRUN -> FAIL [fdo#104108] - fi-skl-6700k2: NOTRUN -> FAIL [fdo#104108] - fi-kbl-x1275: NOTRUN -> FAIL [fdo#108903] / [fdo#108904] / [fdo#108905] - fi-cfl-8700k: NOTRUN -> FAIL [k.org#202107] / [k.org#202109] - fi-skl-6600u: NOTRUN -> FAIL [fdo#104108] - fi-skl-lmem:NOTRUN -> FAIL [fdo#104108] - fi-kbl-r: NOTRUN -> FAIL [fdo#109383] - fi-skl-6770hq: NOTRUN -> FAIL [fdo#104108] - fi-skl-gvtdvm: NOTRUN -> FAIL [fdo#104108] - fi-snb-2600:NOTRUN -> FAIL [fdo#108929] Warnings * igt@gem_exec_suspend@basic-s3: - fi-whl-u: FAIL [fdo#103375] -> DMESG-FAIL [fdo#103375] [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#108903]: https://bugs.freedesktop.org/show_bug.cgi?id=108903 [fdo#108904]: https://bugs.freedesktop.org/show_bug.cgi?id=108904 [fdo#108905]: https://bugs.freedesktop.org/show_bug.cgi?id=108905 [fdo#108929]: https://bugs.freedesktop.org/show_bug.cgi?id=108929 [fdo#109383]: https://bugs.freedesktop.org/show_bug.cgi?id=109383 [fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516 [fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638 [k.org#202107]: https://bugzilla.kernel.org/show_bug.cgi?id=202107 [k.org#202109]: https://bugzilla.kernel.org/show_bug.cgi?id=202109 Participating hosts (46 -> 41) -- Additional (2): fi-hsw-4770r fi-snb-2600 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-bsw-n3050 fi-byt-squawks fi-ctg-p8600 fi-icl-dsi fi-bdw-samus Build changes - * Linux: CI_DRM_5860 -> Patchwork_12668 CI_DRM_5860: 837ba3cd997b59e53903ba29f4fe65c81f86f1e9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4923: 6285eec4f3b8f21833d9d2d852883569d6551822 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12668: 02d1d129c0901cf4cc393c4bc26da
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev3)
== Series Details == Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev3) URL : https://patchwork.freedesktop.org/series/58912/ State : warning == Summary == $ dim checkpatch origin/drm-tip 464216adb294 drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color -:47: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #47: FILE: drivers/gpu/drm/i915/intel_hdmi.c:968: +* */ total: 0 errors, 1 warnings, 0 checks, 14 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
