[PATCH V3] powerpc/85xx: Add support for 85xx cpu type detection

2013-07-10 Thread Haijun Zhang 
Add this file to help detect cpu type in runtime.
These macros will be more favorable for driver
to apply errata and workaround to specified cpu type.

Signed-off-by: Haijun Zhang 
Signed-off-by: Zhao Chenhui 
---
changes for v3:
- remove get_svr and is_svr_rev

 arch/powerpc/include/asm/mpc85xx.h | 47 ++
 1 file changed, 47 insertions(+)
 create mode 100644 arch/powerpc/include/asm/mpc85xx.h

diff --git a/arch/powerpc/include/asm/mpc85xx.h 
b/arch/powerpc/include/asm/mpc85xx.h
new file mode 100644
index 000..824b619
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc85xx.h
@@ -0,0 +1,47 @@
+/*
+ * MPC85xx cpu type detection
+ *
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_MPC85XX_H
+#define __ASM_PPC_MPC85XX_H
+
+#define SVR_REV(svr)   ((svr) & 0xFF)  /* SOC design resision */
+#define SVR_MAJ(svr)   (((svr) >>  4) & 0xF)   /* Major revision field*/
+#define SVR_MIN(svr)   (((svr) >>  0) & 0xF)   /* Minor revision field*/
+
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC Version fields */
+
+#define SVR_8533   0x803400
+#define SVR_8535   0x803701
+#define SVR_8536   0x803700
+#define SVR_8540   0x803000
+#define SVR_8541   0x807200
+#define SVR_8543   0x803200
+#define SVR_8544   0x803401
+#define SVR_8545   0x803102
+#define SVR_8547   0x803101
+#define SVR_8548   0x803100
+#define SVR_8555   0x807100
+#define SVR_8560   0x807000
+#define SVR_8567   0x807501
+#define SVR_8568   0x807500
+#define SVR_8569   0x808000
+#define SVR_8572   0x80E000
+#define SVR_P1010  0x80f900
+#define SVR_P2041  0x821001
+#define SVR_P3041  0x821103
+#define SVR_P5010  0x822100
+#define SVR_P5020  0x822000
+#define SVR_P5040  0x820400
+#define SVR_T4240  0x824800
+#define SVR_B4860  0x868800
+
+#endif
-- 
1.8.0


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Re: [PATCH 3/5] mmc: dw_mmc: Add exynos resume callback to clear WAKEUP_INT

2013-07-10 Thread Grant Grundler 
On Tue, Jul 9, 2013 at 12:09 PM, Doug Anderson  wrote:
> Hi,
>
> On Tue, Jul 9, 2013 at 10:31 AM, Doug Anderson  wrote:
>> If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
>> looping around forever.
>>
>> Signed-off-by: Doug Anderson 
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c | 23 +++
>>  1 file changed, 23 insertions(+)
>
> Grant just pointed out that the WAKEUP_INT is supposed to only be
> enabled if bits 8, 9, or 10 are 1.  Our driver never sets those so we
> _should_ never get a WAKEUP_INT.  Bits 8-10 are marked as RESERVED on
> the exynos5420 manual, so the current guess is that they're broken on
> that silicon but that sometimes the interrupt fires anyway.
>
> In any case, it is still a reasonable thing to clear this interrupt at
> wakeup if it has fired, even if we're on an exynos device without any
> problems.

I agree. Can add:
  Reviewed-by: Grant Grundler 

thanks,
grant

>
> -Doug
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Re: [PATCH v2] mmc: omap_hsmmc: use the generic config for omap2plus devices

2013-07-10 Thread Ezequiel Garcia 
On Wed, Jul 10, 2013 at 09:36:24PM +0530, a-bin...@ti.com wrote:
> From: Amarinder Bindra 
> 
> OMAP's hs_mmc driver is used for MMC controller operation on many
> omap2plus SoCs (OMAP2430, OMAP3, 4, 5 and AM335x).
> 
> Considering that the device tree entries are already present for these,
> allow the driver to be built using the config ARCH_OMAP2PLUS rather
> than individually adding a config for each SoC to enable the
> support.
> 
> Use COMPILE_TEST to enable the build for other platforms.
> 
> Signed-off-by: Amarinder Bindra 
> Cc: Ezequiel Garcia 
> Cc: Felipe Balbi 
> Cc: Nishanth Menon 

Acked-by: Ezequiel Garcia 

-- 
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Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
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Re: [PATCH 1/4 V2] powerpc/85xx: Add support for 85xx cpu type detection

2013-07-10 Thread Scott Wood 

On 07/10/2013 02:39:01 AM, Haijun Zhang wrote:

+/* Get current SOC Version */
+#define GET_SVR()  (mfspr(SPRN_SVR))


Unnecessary parens.  Why do we need GET_SVR(), versus opencoding it?   
Note that U-Boot (which this is patterned after) doesn't have  
GET_SVR(), so code that wants to work on both can't use it anyway.



+#define IS_SVR_REV(svr, maj, min) \
+   ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))


I don't think IS_SVR_REV is needed.  Callers can just do "if  
(SVR_REV(svr) == 0x30)" or whatever, especially since we're relying on  
them to do this for greater/less than comparisons.


-Scott
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Re: [PATCH v2] mmc: omap_hsmmc: use the generic config for omap2plus devices

2013-07-10 Thread Nishanth Menon 
On 21:36-20130710, a-bin...@ti.com wrote:
> From: Amarinder Bindra 
> 
> OMAP's hs_mmc driver is used for MMC controller operation on many
> omap2plus SoCs (OMAP2430, OMAP3, 4, 5 and AM335x).
> 
> Considering that the device tree entries are already present for these,
> allow the driver to be built using the config ARCH_OMAP2PLUS rather
> than individually adding a config for each SoC to enable the
> support.
> 
> Use COMPILE_TEST to enable the build for other platforms.
> 
> Signed-off-by: Amarinder Bindra 
> Cc: Ezequiel Garcia 
> Cc: Felipe Balbi 
> Cc: Nishanth Menon 
works for O5.

Acked-by: Nishanth Menon 

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Re: 答复: [PATCH] Powerpc/t4240: change the compatible flags for t4240qds board

2013-07-10 Thread Scott Wood 

On 07/09/2013 10:41:22 PM, Zhang Haijun-B42677 wrote:
> No.  It's still supposed to be describing the sdhc block itself,  
not the
> board -- and any workarounds that key off of this will still fail  
to work

> with existing device trees.
[Haijun Wrote:] So, leave dts unchanged and to check compitable for  
board in sdhci-pltfm.c

e.g.:
unsigned long root = of_get_flat_dt_root();

if (of_flat_dt_is_compatible(root, "fsl,T4240QDS"))
host->quirks |= XXX;


Why are you looking at the flat tree at this point?  Use the normal OF  
accessors.  The flat stuff is only for early boot.


Also make sure that you only do this for quirks that are actually  
board-specific.  In your last patch you had two quirks keyed off of the  
board, one of which is keyed off of the SoC for other chips.


-SCott
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Re: [PATCH 04/12] drivers/mmc/host: don't use devm_pinctrl_get_select_default() in probe

2013-07-10 Thread Marek Vasut 
Dear Wolfram Sang,

> Since commit ab78029 (drivers/pinctrl: grab default handles from device
> core), we can rely on device core for setting the default pins. Compile
> tested only.
> 
> Acked-by: Linus Walleij  (personally at LCE13)
> Signed-off-by: Wolfram Sang 

Something like that is already in -next:

mmc: mxs-mmc: Let device core handle pinctrl

Otherwise

Tested-by: Marek Vasut 

Best regards,
Marek Vasut
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[PATCH 5/6] ARM: shmobile: ape6evm: disable MMCIF Command Completion Signal

2013-07-10 Thread Guennadi Liakhovetski 
MMCIF on r8a73a4 doesn't support Command Completion Signal, a platform
parameter has to be added to disable it on ape6evm.

Signed-off-by: Guennadi Liakhovetski 
---
 arch/arm/mach-shmobile/board-ape6evm.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ape6evm.c 
b/arch/arm/mach-shmobile/board-ape6evm.c
index e9e2108e..96a6994 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -77,6 +77,7 @@ static struct sh_mmcif_plat_data mmcif0_pdata = {
.caps   = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
.slave_id_tx= SHDMA_SLAVE_MMCIF0_TX,
.slave_id_rx= SHDMA_SLAVE_MMCIF0_RX,
+   .ccs_unsupported = true,
 };
 
 static struct resource mmcif0_resources[] = {
-- 
1.7.2.5

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[PATCH 1/6] mmc: sh_mmcif: revision-specific Command Completion Signal handling

2013-07-10 Thread Guennadi Liakhovetski 
Some earlier MMCIF IP revisions contained Command Completion Signal
support, which has been dropped again in modern versions. Sopport for
this feature is added in a way to preserve the current behaviour by
default, i.e. when it is not enabled in platform data. Patch is based
on work by Nobuyuki HIRAI.

Signed-off-by: Guennadi Liakhovetski 
---
 drivers/mmc/host/sh_mmcif.c  |   27 +--
 include/linux/mmc/sh_mmcif.h |1 +
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index 06caaae..7be20c9 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -133,6 +133,8 @@
 INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
 INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
 
+#define INT_CCS(INT_CCSTO | INT_CCSRCV | INT_CCSDE)
+
 /* CE_INT_MASK */
 #define MASK_ALL   0x
 #define MASK_MCCSDE(1 << 29)
@@ -161,7 +163,7 @@
 
 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | 
\
-MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
+MASK_MCRCSTO | MASK_MWDATTO | \
 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 
 #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE |  
\
@@ -243,6 +245,7 @@ struct sh_mmcif_host {
int sg_blkidx;
bool power;
bool card_present;
+   bool ccs_enable;/* Command Completion Signal support */
struct mutex thread_lock;
 
/* DMA support */
@@ -485,8 +488,10 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
+   if (host->ccs_enable)
+   tmp |= SCCSTO_29;
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
-   SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
+   SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
/* byte swap on */
sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 }
@@ -866,6 +871,9 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
break;
}
 
+   if (host->ccs_enable)
+   mask |= MASK_MCCSTO;
+
if (mrq->data) {
sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
@@ -873,7 +881,10 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
}
opc = sh_mmcif_set_cmd(host, mrq);
 
-   sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
+   if (host->ccs_enable)
+   sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
+   else
+   sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
/* set arg */
sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
@@ -1241,11 +1252,14 @@ static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
 {
struct sh_mmcif_host *host = dev_id;
-   u32 state;
+   u32 state, mask;
 
state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
-   sh_mmcif_writel(host->addr, MMCIF_CE_INT,
-   ~(state & sh_mmcif_readl(host->addr, 
MMCIF_CE_INT_MASK)));
+   mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
+   if (host->ccs_enable)
+   sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
+   else
+   sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & 
mask));
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
 
if (state & ~MASK_CLEAN)
@@ -1375,6 +1389,7 @@ static int sh_mmcif_probe(struct platform_device *pdev)
host->mmc   = mmc;
host->addr  = reg;
host->timeout   = msecs_to_jiffies(1000);
+   host->ccs_enable = !pd || !pd->ccs_unsupported;
 
host->pd = pdev;
 
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index e7d5dd6..b2a22b6 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -39,6 +39,7 @@ struct sh_mmcif_plat_data {
unsigned intslave_id_tx;/* embedded slave_id_[tr]x */
unsigned intslave_id_rx;
booluse_cd_gpio : 1;
+   boolccs_unsupported : 1;
unsigned intcd_gpio;
u8  sup_pclk;   /* 1 :SH7757, 0: SH7724/SH7372 
*/
unsigned long   caps;
-- 
1.7.2.5

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[PATCH 3/6] ARM: shmobile: armadillo800eva: disable MMCIF Command Completion Signal

2013-07-10 Thread Guennadi Liakhovetski 
MMCIF on r8a7740 doesn't support Command Completion Signal, a platform
parameter has to be added to disable it on armadillo800eva.

Signed-off-by: Guennadi Liakhovetski 
---
 arch/arm/mach-shmobile/board-armadillo800eva.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c 
b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 41ff7d65..3cb006b 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -778,6 +778,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
.caps   = MMC_CAP_4_BIT_DATA |
  MMC_CAP_8_BIT_DATA |
  MMC_CAP_NONREMOVABLE,
+   .ccs_unsupported = true,
.slave_id_tx= SHDMA_SLAVE_MMCIF_TX,
.slave_id_rx= SHDMA_SLAVE_MMCIF_RX,
 };
-- 
1.7.2.5

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[PATCH 0/6] mmc: sh_mmcif: revision-specific CCS and CLK_CTRL2 handling

2013-07-10 Thread Guennadi Liakhovetski 
This patch series adds version-specific support for Command Completion 
Signal and the CE_CLK_CTRL2 register. Presumably, the first two patches 
will go via the MMC tree, the rest should be applied after them.

Cc: Guennadi Liakhovetski 

Guennadi Liakhovetski (6):
  mmc: sh_mmcif: revision-specific Command Completion Signal handling
  mmc: sh_mmcif: revision-specific CLK_CTRL2 handling
  ARM: shmobile: armadillo800eva: disable MMCIF Command Completion
Signal
  ARM: shmobile: kzm9g: disable MMCIF Command Completion Signal
  ARM: shmobile: ape6evm: disable MMCIF Command Completion Signal
  ARM: shmobile: lager: disable MMCIF Command Completion Signal, add
CLK_CTRL2

 arch/arm/mach-shmobile/board-ape6evm.c |1 +
 arch/arm/mach-shmobile/board-armadillo800eva.c |1 +
 arch/arm/mach-shmobile/board-kzm9g.c   |1 +
 arch/arm/mach-shmobile/board-lager.c   |2 +
 drivers/mmc/host/sh_mmcif.c|   31 +++
 include/linux/mmc/sh_mmcif.h   |3 ++
 6 files changed, 33 insertions(+), 6 deletions(-)

-- 
1.7.2.5

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
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[PATCH 2/6] mmc: sh_mmcif: revision-specific CLK_CTRL2 handling

2013-07-10 Thread Guennadi Liakhovetski 
Some newer MMCIF IP revisions contain a CE_CLK_CTRL2 register, that has to
be set for proper operation. Support for this feature is added in a way to
preserve the current behaviour by default, i.e. when it is not enabled
in platform data. Patch is based on work by Nobuyuki HIRAI.

Signed-off-by: Guennadi Liakhovetski 
---
 drivers/mmc/host/sh_mmcif.c  |4 
 include/linux/mmc/sh_mmcif.h |2 ++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index 7be20c9..dc3ce52 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -246,6 +246,7 @@ struct sh_mmcif_host {
bool power;
bool card_present;
bool ccs_enable;/* Command Completion Signal support */
+   bool clk_ctrl2_enable;
struct mutex thread_lock;
 
/* DMA support */
@@ -490,6 +491,8 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
if (host->ccs_enable)
tmp |= SCCSTO_29;
+   if (host->clk_ctrl2_enable)
+   sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F);
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
/* byte swap on */
@@ -1390,6 +1393,7 @@ static int sh_mmcif_probe(struct platform_device *pdev)
host->addr  = reg;
host->timeout   = msecs_to_jiffies(1000);
host->ccs_enable = !pd || !pd->ccs_unsupported;
+   host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
 
host->pd = pdev;
 
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index b2a22b6..d4277d9 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -40,6 +40,7 @@ struct sh_mmcif_plat_data {
unsigned intslave_id_rx;
booluse_cd_gpio : 1;
boolccs_unsupported : 1;
+   boolclk_ctrl2_present : 1;
unsigned intcd_gpio;
u8  sup_pclk;   /* 1 :SH7757, 0: SH7724/SH7372 
*/
unsigned long   caps;
@@ -63,6 +64,7 @@ struct sh_mmcif_plat_data {
 #define MMCIF_CE_INT_MASK  0x0044
 #define MMCIF_CE_HOST_STS1 0x0048
 #define MMCIF_CE_HOST_STS2 0x004C
+#define MMCIF_CE_CLK_CTRL2 0x0070
 #define MMCIF_CE_VERSION   0x007C
 
 /* CE_BUF_ACC */
-- 
1.7.2.5

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[PATCH 4/6] ARM: shmobile: kzm9g: disable MMCIF Command Completion Signal

2013-07-10 Thread Guennadi Liakhovetski 
MMCIF on sh73a0 doesn't support Command Completion Signal, a platform
parameter has to be added to disable it on kzm9g.

Signed-off-by: Guennadi Liakhovetski 
---
 arch/arm/mach-shmobile/board-kzm9g.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-kzm9g.c 
b/arch/arm/mach-shmobile/board-kzm9g.c
index 165483c..7ec26a5 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -365,6 +365,7 @@ static struct resource sh_mmcif_resources[] = {
 static struct sh_mmcif_plat_data sh_mmcif_platdata = {
.ocr= MMC_VDD_165_195,
.caps   = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+   .ccs_unsupported = true,
.slave_id_tx= SHDMA_SLAVE_MMCIF_TX,
.slave_id_rx= SHDMA_SLAVE_MMCIF_RX,
 };
-- 
1.7.2.5

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[PATCH 6/6] ARM: shmobile: lager: disable MMCIF Command Completion Signal, add CLK_CTRL2

2013-07-10 Thread Guennadi Liakhovetski 
MMCIF on r8a7790 doesn't support Command Completion Signal, but it does
implement a CE_CLK_CTRL2 register. Platform parameters have to be added to
account for these features on lager.

Signed-off-by: Guennadi Liakhovetski 
---
 arch/arm/mach-shmobile/board-lager.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-lager.c 
b/arch/arm/mach-shmobile/board-lager.c
index 3c67b2a..9b3085f 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -84,6 +84,8 @@ static struct regulator_consumer_supply 
fixed3v3_power_consumers[] =
 /* MMCIF */
 static struct sh_mmcif_plat_data mmcif1_pdata = {
.caps   = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+   .clk_ctrl2_present = true,
+   .ccs_unsupported = true,
 };
 
 static struct resource mmcif1_resources[] = {
-- 
1.7.2.5

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[PATCH v2] mmc: omap_hsmmc: use the generic config for omap2plus devices

2013-07-10 Thread a-bindra 
From: Amarinder Bindra 

OMAP's hs_mmc driver is used for MMC controller operation on many
omap2plus SoCs (OMAP2430, OMAP3, 4, 5 and AM335x).

Considering that the device tree entries are already present for these,
allow the driver to be built using the config ARCH_OMAP2PLUS rather
than individually adding a config for each SoC to enable the
support.

Use COMPILE_TEST to enable the build for other platforms.

Signed-off-by: Amarinder Bindra 
Cc: Ezequiel Garcia 
Cc: Felipe Balbi 
Cc: Nishanth Menon 
---
Changes in v2:
- Use the config ARCH_OMAP2PLUS to enable the driver
- Use COMPILE_TEST
- Update the commit message

v1: https://patchwork.kernel.org/patch/2824632/ 

 drivers/mmc/host/Kconfig |6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 009dabd..48f6fe7 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -254,11 +254,11 @@ config MMC_OMAP
 
 config MMC_OMAP_HS
tristate "TI OMAP High Speed Multimedia Card Interface support"
-   depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4
+   depends on ARCH_OMAP2PLUS || COMPILE_TEST
help
  This selects the TI OMAP High Speed Multimedia card Interface.
- If you have an OMAP2430 or OMAP3 board or OMAP4 board with a
- Multimedia Card slot, say Y or M here.
+ If you have an omap2plus board with a Multimedia Card slot,
+ say Y or M here.
 
  If unsure, say N.
 
-- 
1.7.9.5

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[PATCH 04/12] drivers/mmc/host: don't use devm_pinctrl_get_select_default() in probe

2013-07-10 Thread Wolfram Sang 
Since commit ab78029 (drivers/pinctrl: grab default handles from device core),
we can rely on device core for setting the default pins. Compile tested only.

Acked-by: Linus Walleij  (personally at LCE13)
Signed-off-by: Wolfram Sang 
---
 drivers/mmc/host/mvsdio.c  |6 --
 drivers/mmc/host/mxs-mmc.c |8 
 drivers/mmc/host/omap_hsmmc.c  |7 ---
 drivers/mmc/host/sdhci-esdhc-imx.c |8 
 drivers/mmc/host/sdhci-sirf.c  |8 
 5 files changed, 37 deletions(-)

diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c
index 8960fc8..ed5edc2 100644
--- a/drivers/mmc/host/mvsdio.c
+++ b/drivers/mmc/host/mvsdio.c
@@ -25,7 +25,6 @@
 #include 
 #include 
 #include 
-#include 
 
 #include 
 #include 
@@ -686,7 +685,6 @@ static int __init mvsd_probe(struct platform_device *pdev)
struct resource *r;
int ret, irq;
int gpio_card_detect, gpio_write_protect;
-   struct pinctrl *pinctrl;
 
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
@@ -703,10 +701,6 @@ static int __init mvsd_probe(struct platform_device *pdev)
host->mmc = mmc;
host->dev = &pdev->dev;
 
-   pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-   if (IS_ERR(pinctrl))
-   dev_warn(&pdev->dev, "no pins associated\n");
-
/*
 * Some non-DT platforms do not pass a clock, and the clock
 * frequency is passed through platform_data. On DT platforms,
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index 4278a17..1eb3224 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -41,7 +41,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
@@ -580,7 +579,6 @@ static int mxs_mmc_probe(struct platform_device *pdev)
struct mxs_mmc_host *host;
struct mmc_host *mmc;
struct resource *iores;
-   struct pinctrl *pinctrl;
int ret = 0, irq_err;
struct regulator *reg_vmmc;
enum of_gpio_flags flags;
@@ -620,12 +618,6 @@ static int mxs_mmc_probe(struct platform_device *pdev)
}
}
 
-   pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-   if (IS_ERR(pinctrl)) {
-   ret = PTR_ERR(pinctrl);
-   goto out_mmc_free;
-   }
-
ssp->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(ssp->clk)) {
ret = PTR_ERR(ssp->clk);
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index eccedc7..332ce51 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -37,7 +37,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
@@ -1776,7 +1775,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
const struct of_device_id *match;
dma_cap_mask_t mask;
unsigned tx_req, rx_req;
-   struct pinctrl *pinctrl;
 
match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
if (match) {
@@ -1995,11 +1993,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 
omap_hsmmc_disable_irq(host);
 
-   pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-   if (IS_ERR(pinctrl))
-   dev_warn(&pdev->dev,
-   "pins are not configured from the driver\n");
-
omap_hsmmc_protect_card(host);
 
mmc_add_host(mmc);
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c 
b/drivers/mmc/host/sdhci-esdhc-imx.c
index d5f0d59..0880e3a 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -25,7 +25,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include "sdhci-pltfm.h"
 #include "sdhci-esdhc.h"
@@ -80,7 +79,6 @@ struct pltfm_imx_data {
int flags;
u32 scratchpad;
enum imx_esdhc_type devtype;
-   struct pinctrl *pinctrl;
struct esdhc_platform_data boarddata;
struct clk *clk_ipg;
struct clk *clk_ahb;
@@ -544,12 +542,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device 
*pdev)
clk_prepare_enable(imx_data->clk_ipg);
clk_prepare_enable(imx_data->clk_ahb);
 
-   imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
-   if (IS_ERR(imx_data->pinctrl)) {
-   err = PTR_ERR(imx_data->pinctrl);
-   goto disable_clk;
-   }
-
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 
if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
index 09805af..ccf12dd 100644
--- a/drivers/mmc/host/sdhci-sirf.c
+++ b/drivers/mmc/host/sdhci-sirf.c
@@ -13,7 +13,6 @@
 #include 
 #include 
 #include 
-#include 
 #include "sdhci-pltfm.h"
 
 struct sdhci_sirf_priv {
@@ -46,15 +45,8 @@ static int sdhci_sirf_probe(struct platform_device *pdev)
struct sdhci_host *host;
struct sdhci_pltfm_

[PATCH v3 0/5] mmc: dw_mmc: fixes for suspend/resume on exynos

2013-07-10 Thread Doug Anderson 
This series of patches addresses some suspend/resume problems with
dw_mmc on exynos platforms.  Since suspend/resume is not fully working
on ToT Linux (3.10) on exynos5250-snow, this series was tested against
the current ToT ChromeOS 3.8 tree.  I have confirmed basic booting
and eMMC / SD card usage (and compiling, honest!) against ToT Linux.

Changes in v3:
- Add freeze/thaw and poweroff/restore noirq entries.

Changes in v2:
- Fix typo (some -> come)
- Use ~0 instead of 0x; add comment about value
- Use suspend_noirq as per James Hogan.

Doug Anderson (5):
  mmc: dw_mmc: Invalidate cache of current_speed after suspend/resume
  mmc: dw_mmc: Add suspend_noirq/resume_noirq callbacks for dw_mmc-pltfm
  mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
  mmc: dw_mmc: Always setup the bus after suspend/resume
  mmc: dw_mmc: Set timeout to max upon resume

 drivers/mmc/host/dw_mmc-exynos.c | 23 ++
 drivers/mmc/host/dw_mmc-pltfm.c  | 41 +---
 drivers/mmc/host/dw_mmc.c| 15 +++
 drivers/mmc/host/dw_mmc.h|  4 
 4 files changed, 76 insertions(+), 7 deletions(-)

-- 
1.8.3

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[PATCH v3 4/5] mmc: dw_mmc: Always setup the bus after suspend/resume

2013-07-10 Thread Doug Anderson 
After suspend/resume all of the dw_mmc registers are reset to
defaults.  We restore most of them, but specifically don't setup the
clock registers after resume unless we've got a powered card.  Things
still work because the core will eventually call set_ios() and we'll
set things up.

There doesn't seem to be any reason that I can see _not_ to set things
up after resume.  Restoring this state makes the code easier to reason
about and should help prevent bugs.  It also allows us to do a
register dump before and after suspend/resume to confirm that we've
set things up OK.

I examined the state of the dw_mmc instance before and after suspend
after this patch.  I had no card inserted in an SD card slot.

Before this patch, differences were:
* CLKDIV (0x08)
* CLKENA (0x10)
* TMOUT (0x14)
* CMD (0x2C) - difference is not important
* CLKSEL (0x9C - exynos specific)

After this patch, only TMOUT was different.  I have a separate patch
for that.

Signed-off-by: Doug Anderson 
---
Changes in v3: None
Changes in v2: None

 drivers/mmc/host/dw_mmc.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 7a5ce6a..be095b7 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2499,9 +2499,7 @@ int dw_mci_resume(struct dw_mci *host)
struct dw_mci_slot *slot = host->slot[i];
if (!slot)
continue;
-   if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
-   dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
-   }
+   dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
 
ret = mmc_resume_host(host->slot[i]->mmc);
if (ret < 0)
-- 
1.8.3

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[PATCH v3 3/5] mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT

2013-07-10 Thread Doug Anderson 
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever.  This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events.

Signed-off-by: Doug Anderson 
---
Changes in v3: None
Changes in v2:
- Use suspend_noirq as per James Hogan.

 drivers/mmc/host/dw_mmc-exynos.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index f013e7e..36b9620 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -30,6 +30,7 @@
 #define SDMMC_CLKSEL_TIMING(x, y, z)   (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
SDMMC_CLKSEL_CCLK_DRIVE(y) |\
SDMMC_CLKSEL_CCLK_DIVIDER(z))
+#define SDMMC_CLKSEL_WAKEUP_INTBIT(11)
 
 #define SDMMC_CMD_USE_HOLD_REG BIT(29)
 
@@ -102,6 +103,27 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
return 0;
 }
 
+/**
+ * dw_mci_exynos_resume_noirq - Exynos-specific resume code
+ *
+ * We have seen cases (at least on the exynos5420) where turning off the INT
+ * power rail during suspend will leave the WAKEUP_INT bit in the CLKSEL
+ * register asserted.  This bit is 1 to indicate that it fired and we can
+ * clear it by writing a 1 back.  Clear it to prevent interrupts from going off
+ * constantly.
+ */
+
+static int dw_mci_exynos_resume_noirq(struct dw_mci *host)
+{
+   u32 clksel;
+
+   clksel = mci_readl(host, CLKSEL);
+   if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
+   mci_writel(host, CLKSEL, clksel);
+
+   return 0;
+}
+
 static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
 {
/*
@@ -165,6 +187,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
.caps   = exynos_dwmmc_caps,
.init   = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
+   .resume_noirq   = dw_mci_exynos_resume_noirq,
.prepare_command= dw_mci_exynos_prepare_command,
.set_ios= dw_mci_exynos_set_ios,
.parse_dt   = dw_mci_exynos_parse_dt,
-- 
1.8.3

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[PATCH v3 5/5] mmc: dw_mmc: Set timeout to max upon resume

2013-07-10 Thread Doug Anderson 
The TMOUT register is initted to 0x at probe time but isn't
initted after suspend/resume.  Add an init of this value.

No problems were observed without this (it will also get initted in
__dw_mci_start_request if there is data to send), but it makes the
register dump before and after suspend clean.

Signed-off-by: Doug Anderson 
Acked-by: Seungwon Jeon 
---
Changes in v3: None
Changes in v2: None

 drivers/mmc/host/dw_mmc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index be095b7..d2c5db3 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2482,6 +2482,9 @@ int dw_mci_resume(struct dw_mci *host)
/* Restore the old value at FIFOTH register */
mci_writel(host, FIFOTH, host->fifoth_val);
 
+   /* Put in max timeout */
+   mci_writel(host, TMOUT, 0x);
+
mci_writel(host, RINTSTS, 0x);
mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
   SDMMC_INT_TXDR | SDMMC_INT_RXDR |
-- 
1.8.3

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[PATCH v3 2/5] mmc: dw_mmc: Add suspend_noirq/resume_noirq callbacks for dw_mmc-pltfm

2013-07-10 Thread Doug Anderson 
On some devices (like exynos5420) the dw_mmc controller may be in a
strange state after we wake up from sleep.  Add callbacks to allow for
dealing with these quirks.  We use the "_noirq" versions of the
callbacks since in the case of exynos5420 the strange state caused
interrupts to fire so we need to deal with it while interrupts are
still off.

At the moment this support is only added to dw_mmc-pltfm which calls
straight to the callback, since nobody but exynos needs it.  We can
add some levels of indirection (a call into the generic dw_mmc code)
when someone finds a need.

Signed-off-by: Doug Anderson 
Reviewed-by: James Hogan 
---
Changes in v3:
- Add freeze/thaw and poweroff/restore noirq entries.

Changes in v2:
- Use suspend_noirq as per James Hogan.

 drivers/mmc/host/dw_mmc-pltfm.c | 41 ++---
 drivers/mmc/host/dw_mmc.h   |  4 
 2 files changed, 42 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index 41c27b7..742ef76 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -105,12 +105,47 @@ static int dw_mci_pltfm_resume(struct device *dev)
 
return 0;
 }
+
+static int dw_mci_pltfm_suspend_noirq(struct device *dev)
+{
+   struct dw_mci *host = dev_get_drvdata(dev);
+   const struct dw_mci_drv_data *drv_data = host->drv_data;
+
+   if (drv_data && drv_data->suspend_noirq)
+   return drv_data->suspend_noirq(host);
+
+   return 0;
+}
+
+static int dw_mci_pltfm_resume_noirq(struct device *dev)
+{
+   struct dw_mci *host = dev_get_drvdata(dev);
+   const struct dw_mci_drv_data *drv_data = host->drv_data;
+
+   if (drv_data && drv_data->resume_noirq)
+   return drv_data->resume_noirq(host);
+
+   return 0;
+}
+
+
 #else
-#define dw_mci_pltfm_suspend   NULL
-#define dw_mci_pltfm_resumeNULL
+#define dw_mci_pltfm_suspend   NULL
+#define dw_mci_pltfm_resumeNULL
+#define dw_mci_pltfm_suspend_noirq NULL
+#define dw_mci_pltfm_resume_noirq  NULL
 #endif /* CONFIG_PM_SLEEP */
 
-SIMPLE_DEV_PM_OPS(dw_mci_pltfm_pmops, dw_mci_pltfm_suspend, 
dw_mci_pltfm_resume);
+const struct dev_pm_ops dw_mci_pltfm_pmops = {
+   SET_SYSTEM_SLEEP_PM_OPS(dw_mci_pltfm_suspend, dw_mci_pltfm_resume)
+   .suspend_noirq = dw_mci_pltfm_suspend_noirq,
+   .resume_noirq = dw_mci_pltfm_resume_noirq,
+   .freeze_noirq = dw_mci_pltfm_suspend_noirq,
+   .thaw_noirq = dw_mci_pltfm_resume_noirq,
+   .poweroff_noirq = dw_mci_pltfm_suspend_noirq,
+   .restore_noirq = dw_mci_pltfm_resume_noirq,
+};
+
 EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
 
 static const struct of_device_id dw_mci_pltfm_match[] = {
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 0b74189..5d0398f 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -190,6 +190,8 @@ extern int dw_mci_resume(struct dw_mci *host);
  * @prepare_command: handle CMD register extensions.
  * @set_ios: handle bus specific extensions.
  * @parse_dt: parse implementation specific device tree properties.
+ * @suspend_noirq: called late in the suspend process
+ * @resume_noirq: called early in the resume process
  *
  * Provide controller implementation specific extensions. The usage of this
  * data structure is fully optional and usage of each member in this structure
@@ -202,5 +204,7 @@ struct dw_mci_drv_data {
void(*prepare_command)(struct dw_mci *host, u32 *cmdr);
void(*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
int (*parse_dt)(struct dw_mci *host);
+   int (*suspend_noirq)(struct dw_mci *host);
+   int (*resume_noirq)(struct dw_mci *host);
 };
 #endif /* _DW_MMC_H_ */
-- 
1.8.3

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[PATCH v3 1/5] mmc: dw_mmc: Invalidate cache of current_speed after suspend/resume

2013-07-10 Thread Doug Anderson 
The dw_mmc driver keeps a cache of the current slot->clock in order to
avoid doing a whole lot of work every time set_ios() is called.
However, after suspend/resume the register values are bogus so we need
to ensure that the cached value is invalidated.

In many cases we got by without this since the core mmc code fiddles
with the clock a lot.  If we've got a card present we're probably
running it at something like 50MHz and the core will temporarily
switch us to 400kHz after resume.  One case that didn't work (for me)
is the case of having no card in the slot.  The slot is initted to
400kHz at boot time.  After suspend/resume the slot thinks it's still
at 400kHz (due to the cache) so doesn't adjust timing.  When it tries
to send the command at probe time it just times out and gets left in a
bad state.

Invalidating the current_speed also means that we don't need to call:
  dw_mci_setup_bus(slot, true);
...to force an update of the clock in the case when the slot was left
powered.

Signed-off-by: Doug Anderson 
---
Changes in v3: None
Changes in v2:
- Fix typo (some -> come)
- Use ~0 instead of 0x; add comment about value

 drivers/mmc/host/dw_mmc.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index bc3a1bc..7a5ce6a 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2488,13 +2488,19 @@ int dw_mci_resume(struct dw_mci *host)
   DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
 
+   /*
+* Invalidate the 'current_speed' value since CLKDIV has come up in
+* default state and our cache is incorrect; set to something we know
+* slot->clock won't be.
+*/
+   host->current_speed = ~0;
+
for (i = 0; i < host->num_slots; i++) {
struct dw_mci_slot *slot = host->slot[i];
if (!slot)
continue;
if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
-   dw_mci_setup_bus(slot, true);
}
 
ret = mmc_resume_host(host->slot[i]->mmc);
-- 
1.8.3

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Re: [PATCH v2 2/5] mmc: dw_mmc: Add suspend_noirq/resume_noirq callbacks for dw_mmc-pltfm

2013-07-10 Thread Doug Anderson 
James,

On Wed, Jul 10, 2013 at 1:37 AM, James Hogan  wrote:
>> -SIMPLE_DEV_PM_OPS(dw_mci_pltfm_pmops, dw_mci_pltfm_suspend, 
>> dw_mci_pltfm_resume);
>> +const struct dev_pm_ops dw_mci_pltfm_pmops = {
>> + SET_SYSTEM_SLEEP_PM_OPS(dw_mci_pltfm_suspend, dw_mci_pltfm_resume)
>> + .suspend_noirq = dw_mci_pltfm_suspend_noirq,
>> + .resume_noirq = dw_mci_pltfm_resume_noirq,
>> +};
>
> Does Exynos support hibernation? I see that SET_SYSTEM_SLEEP_PM_OPS sets
> freeze, thaw, poweroff, and restore callbacks too. You may not need the
> hibernation specific _noirq callbacks though in which case it's probably
> fine as it is.

Thank you for your review and good suggestions.  You're right that I
should add the other "noirq" variants in here.  Even if hibernation
isn't supported now that's the right thing to do.  I will fix that and
send v3 with your "Reviewed-by".


-Doug
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Re: [PATCH v2 3/5] mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT

2013-07-10 Thread Doug Anderson 
Seungwon,

On Wed, Jul 10, 2013 at 7:54 AM, Seungwon Jeon  wrote:
> On Wed, July 10, 2013, Doug Anderson wrote:
>> If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
>> looping around forever.  This has been seen to happen on exynos5420
>> silicon despite the fact that we haven't enabled any wakeup events.
>>
>> Signed-off-by: Doug Anderson 
>> ---
>> Changes in v2:
>> - Use suspend_noirq as per James Hogan.
>>
>>  drivers/mmc/host/dw_mmc-exynos.c | 23 +++
>>  1 file changed, 23 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> b/drivers/mmc/host/dw_mmc-exynos.c
>> index f013e7e..36b9620 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -30,6 +30,7 @@
>>  #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
>>   SDMMC_CLKSEL_CCLK_DRIVE(y) |\
>>   SDMMC_CLKSEL_CCLK_DIVIDER(z))
>> +#define SDMMC_CLKSEL_WAKEUP_INT  BIT(11)
>>
>>  #define SDMMC_CMD_USE_HOLD_REG   BIT(29)
>>
>> @@ -102,6 +103,27 @@ static int dw_mci_exynos_setup_clock(struct dw_mci 
>> *host)
>>   return 0;
>>  }
>>
>> +/**
>> + * dw_mci_exynos_resume_noirq - Exynos-specific resume code
>> + *
>> + * We have seen cases (at least on the exynos5420) where turning off the INT
>> + * power rail during suspend will leave the WAKEUP_INT bit in the CLKSEL
>> + * register asserted.  This bit is 1 to indicate that it fired and we can
>> + * clear it by writing a 1 back.  Clear it to prevent interrupts from going 
>> off
>> + * constantly.
>> + */
> As I know this bit is auto-cleared.
> Did you find the cause of this problem?
> How about your GPIO setting in sleep?
> Currently, we don't know why the problem is happened.
> At least, we should make it clear.

Yes, the documentation that I have says that this bit is "auto
cleared" as well but doesn't indicate under what conditions it is auto
cleared.  From testing how this bit reacts I have found that writing a
1 to it clears the bit--in other words it behaves like bits in
RINTSTS.  That's a terrible design for a bit in a register with shared
config but appears to be how it works.

Note: in a sense it will be "auto cleared" because doing a
read-modify-write of any other bits in this register will clear the
interrupt.

I have asked for official confirmation.

We have found that on exynos5420 bits 8-10 of CLKSEL are marked as
RESERVED.  Those bits are documented to enable the WAKEUP_INT on
exynos5250.  My best guess is that these bits are not used on
exynos5420 and the WAKEUP_INT line is left floating, which means it
can fire randomly.  I have also asked for official confirmation about
this.


I will likely merge this change locally in our kernel tree while
waiting for a response.  If you would like to wait before Acking
that's very reasonable.  Do you have any other problems with this
change assuming my understanding above is correct?

-Doug
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RE: [PATCH v2 3/5] mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT

2013-07-10 Thread Seungwon Jeon 
On Wed, July 10, 2013, Doug Anderson wrote:
> If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
> looping around forever.  This has been seen to happen on exynos5420
> silicon despite the fact that we haven't enabled any wakeup events.
> 
> Signed-off-by: Doug Anderson 
> ---
> Changes in v2:
> - Use suspend_noirq as per James Hogan.
> 
>  drivers/mmc/host/dw_mmc-exynos.c | 23 +++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
> b/drivers/mmc/host/dw_mmc-exynos.c
> index f013e7e..36b9620 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -30,6 +30,7 @@
>  #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
>   SDMMC_CLKSEL_CCLK_DRIVE(y) |\
>   SDMMC_CLKSEL_CCLK_DIVIDER(z))
> +#define SDMMC_CLKSEL_WAKEUP_INT  BIT(11)
> 
>  #define SDMMC_CMD_USE_HOLD_REG   BIT(29)
> 
> @@ -102,6 +103,27 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
>   return 0;
>  }
> 
> +/**
> + * dw_mci_exynos_resume_noirq - Exynos-specific resume code
> + *
> + * We have seen cases (at least on the exynos5420) where turning off the INT
> + * power rail during suspend will leave the WAKEUP_INT bit in the CLKSEL
> + * register asserted.  This bit is 1 to indicate that it fired and we can
> + * clear it by writing a 1 back.  Clear it to prevent interrupts from going 
> off
> + * constantly.
> + */
As I know this bit is auto-cleared.
Did you find the cause of this problem?
How about your GPIO setting in sleep?
Currently, we don't know why the problem is happened.
At least, we should make it clear.

Thanks,
Seungwon Jeon

> +
> +static int dw_mci_exynos_resume_noirq(struct dw_mci *host)
> +{
> + u32 clksel;
> +
> + clksel = mci_readl(host, CLKSEL);
> + if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
> + mci_writel(host, CLKSEL, clksel);
> +
> + return 0;
> +}
> +
>  static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
>  {
>   /*
> @@ -165,6 +187,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
>   .caps   = exynos_dwmmc_caps,
>   .init   = dw_mci_exynos_priv_init,
>   .setup_clock= dw_mci_exynos_setup_clock,
> + .resume_noirq   = dw_mci_exynos_resume_noirq,
>   .prepare_command= dw_mci_exynos_prepare_command,
>   .set_ios= dw_mci_exynos_set_ios,
>   .parse_dt   = dw_mci_exynos_parse_dt,
> --
> 1.8.3
> 
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RE: [PATCH v2 5/5] mmc: dw_mmc: Set timeout to max upon resume

2013-07-10 Thread Seungwon Jeon 
On Wed, July 10, 2013, Doug Anderson wrote:
> The TMOUT register is initted to 0x at probe time but isn't
> initted after suspend/resume.  Add an init of this value.
> 
> No problems were observed without this (it will also get initted in
> __dw_mci_start_request if there is data to send), but it makes the
> register dump before and after suspend clean.
> 
> Signed-off-by: Doug Anderson 

Acked-by: Seungwon Jeon 

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RE: [PATCH] mmc: dw_mmc: Handle DW_MCI_QUIRK_IDMAC_DTO properly

2013-07-10 Thread Seungwon Jeon 
On Wed, July 10, 2013, Doug Anderson wrote:
> In (1fb5f68 mmc: dw_mmc: Don't loop when handling an interrupt), the
> code for handling DW_MCI_QUIRK_IDMAC_DTO became dead code.  Move it to
> where it ought to live.
> 
> Found by code inspection and compile-tested only--I don't know of any
> boards that need DW_MCI_QUIRK_IDMAC_DTO.
> 
> Signed-off-by: Doug Anderson 

Acked-by: Seungwon Jeon 

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[PATCH] mmc: sdhci-moxart: Add MOXA ART SDHCI driver

2013-07-10 Thread Jonas Jensen 
Add SDHCI driver for MOXA ART SoCs.

Signed-off-by: Jonas Jensen 
---

Notes:
Applies to next-20130703

I know this is a large chunk and there are many pitfalls with
the controller. I give you my word it does work / seem to be stable,
with or without DMA. Any feedback is appreciated.

Tested by creating multiple directories/files and moving the card
back and forth to different reader.

IRQF_DISABLED is now pointless, remove it from request_irq?

 drivers/mmc/host/Kconfig|   9 +
 drivers/mmc/host/Makefile   |   1 +
 drivers/mmc/host/sdhci-moxart.c | 786 
 drivers/mmc/host/sdhci-moxart.h | 155 
 4 files changed, 951 insertions(+)
 create mode 100644 drivers/mmc/host/sdhci-moxart.c
 create mode 100644 drivers/mmc/host/sdhci-moxart.h

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 1be2289..fb401c4 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -260,6 +260,15 @@ config MMC_SDHCI_BCM2835
 
  If unsure, say N.
 
+config MMC_SDHCI_MOXART
+   tristate "MOXART SD Host Controller Interface support"
+   depends on ARCH_MOXART && MMC
+   help
+ This selects the MOXART SD Host Controller Interface.
+ MOXA provides one multi-functional card reader which can
+ be found on some embedded hardware such as UC-7112-LX.
+ If you have a controller with this interface, say Y here.
+
 config MMC_OMAP
tristate "TI OMAP Multimedia Card Interface support"
depends on ARCH_OMAP
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 67718c1..274199a 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)   += sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)+= sdhci-of-hlwd.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)+= sdhci-bcm2835.o
+obj-$(CONFIG_MMC_SDHCI_MOXART) += sdhci-moxart.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
CFLAGS-cb710-mmc+= -DDEBUG
diff --git a/drivers/mmc/host/sdhci-moxart.c b/drivers/mmc/host/sdhci-moxart.c
new file mode 100644
index 000..f5aaea6
--- /dev/null
+++ b/drivers/mmc/host/sdhci-moxart.c
@@ -0,0 +1,786 @@
+/*
+ * MOXA ART MMC host driver.
+ *
+ * Copyright (C) 2013 Jonas Jensen
+ *
+ * Jonas Jensen 
+ *
+ * Based on code from
+ * Moxa Technology Co., Ltd. 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "sdhci-moxart.h"
+
+#define DMA_FIFO_LEN_FORCE 0
+#define APB_DMA_SD_REQ_NO  5
+#define MIN_POWER (MMC_VDD_360 - MSD_SD_POWER_MASK)
+
+static inline void moxart_init_sg(struct moxart_host *host,
+ struct mmc_data *data)
+{
+   host->cur_sg = data->sg;
+   host->num_sg = data->sg_len;
+   host->remain = host->cur_sg->length;
+
+   if (host->remain > host->size)
+   host->remain = host->size;
+
+   data->error = MMC_ERR_NONE;
+}
+
+static inline int moxart_next_sg(struct moxart_host *host)
+{
+   int remain;
+   struct mmc_data *data = host->mrq->cmd->data;
+
+   host->cur_sg++;
+   host->num_sg--;
+
+   if (host->num_sg > 0) {
+   host->remain = host->cur_sg->length;
+   remain = host->size - data->bytes_xfered;
+   if (remain > 0 && remain < host->remain)
+   host->remain = remain;
+   }
+
+   return host->num_sg;
+}
+
+static void moxart_send_command(struct moxart_host *host,
+   struct mmc_command *cmd)
+{
+   unsigned int status, cmdctrl;
+   int retry = 0;
+
+   dev_dbg(mmc_dev(host->mmc), "%s: cmd->opcode=%d\n",
+   __func__, cmd->opcode);
+
+   cmd->error = MMC_ERR_TIMEOUT;
+
+   writel(MSD_RSP_TIMEOUT | MSD_RSP_CRC_OK |
+  MSD_RSP_CRC_FAIL | MSD_CMD_SENT, &host->reg->clear);
+   writel(cmd->arg, &host->reg->argument);
+
+   cmdctrl = cmd->opcode & MSD_CMD_IDX_MASK;
+   if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND ||
+   cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS ||
+   cmdctrl == SD_APP_SEND_NUM_WR_BLKS)
+   cmdctrl |= MSD_APP_CMD;
+
+   if (cmd->flags & MMC_RSP_136)
+   cmdctrl |= (MSD_LONG_RSP | MSD_NEED_RSP);
+   else
+   cmdctrl |= MSD_NEED_RSP;
+
+   writel(cmdctrl | MSD_CMD_EN, &host->reg->command);
+
+   while (retry++ < MSD_RETRY_COUNT) {
+   udelay(10)

Re: [PATCH v2 2/5] mmc: dw_mmc: Add suspend_noirq/resume_noirq callbacks for dw_mmc-pltfm

2013-07-10 Thread James Hogan 
Hi Doug,

On 10/07/13 00:19, Doug Anderson wrote:
> On some devices (like exynos5420) the dw_mmc controller may be in a
> strange state after we wake up from sleep.  Add callbacks to allow for
> dealing with these quirks.  We use the "_noirq" versions of the
> callbacks since in the case of exynos5420 the strange state caused
> interrupts to fire so we need to deal with it while interrupts are
> still off.
> 
> At the moment this support is only added to dw_mmc-pltfm which calls
> straight to the callback, since nobody but exynos needs it.  We can
> add some levels of indirection (a call into the generic dw_mmc code)
> when someone finds a need.
> 
> Signed-off-by: Doug Anderson 

Reviewed-by: James Hogan 



>  
> -SIMPLE_DEV_PM_OPS(dw_mci_pltfm_pmops, dw_mci_pltfm_suspend, 
> dw_mci_pltfm_resume);
> +const struct dev_pm_ops dw_mci_pltfm_pmops = {
> + SET_SYSTEM_SLEEP_PM_OPS(dw_mci_pltfm_suspend, dw_mci_pltfm_resume)
> + .suspend_noirq = dw_mci_pltfm_suspend_noirq,
> + .resume_noirq = dw_mci_pltfm_resume_noirq,
> +};

Does Exynos support hibernation? I see that SET_SYSTEM_SLEEP_PM_OPS sets
freeze, thaw, poweroff, and restore callbacks too. You may not need the
hibernation specific _noirq callbacks though in which case it's probably
fine as it is.

Cheers
James

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[PATCH 1/4 V2] powerpc/85xx: Add support for 85xx cpu type detection

2013-07-10 Thread Haijun Zhang 
Add this file to help detect cpu type in runtime.
These macros will be more favorable for driver
to apply errata and workaround to specified cpu type.

Signed-off-by: Haijun Zhang 
Signed-off-by: Zhao Chenhui 
---
changes v2:
- Remove inline function
- Ignore E bit of SOC
- Add Macro to get current soc version

 arch/powerpc/include/asm/mpc85xx.h | 53 ++
 1 file changed, 53 insertions(+)
 create mode 100644 arch/powerpc/include/asm/mpc85xx.h

diff --git a/arch/powerpc/include/asm/mpc85xx.h 
b/arch/powerpc/include/asm/mpc85xx.h
new file mode 100644
index 000..20af5e8
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc85xx.h
@@ -0,0 +1,53 @@
+/*
+ * MPC85xx cpu type detection
+ *
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_MPC85XX_H
+#define __ASM_PPC_MPC85XX_H
+
+#define SVR_REV(svr)   ((svr) & 0xFF)  /* SOC design resision */
+#define SVR_MAJ(svr)   (((svr) >>  4) & 0xF)   /* Major revision field*/
+#define SVR_MIN(svr)   (((svr) >>  0) & 0xF)   /* Minor revision field*/
+
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC Version fields */
+
+/* Get current SOC Version */
+#define GET_SVR()  (mfspr(SPRN_SVR))
+
+#define IS_SVR_REV(svr, maj, min) \
+   ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+
+#define SVR_8533   0x803400
+#define SVR_8535   0x803701
+#define SVR_8536   0x803700
+#define SVR_8540   0x803000
+#define SVR_8541   0x807200
+#define SVR_8543   0x803200
+#define SVR_8544   0x803401
+#define SVR_8545   0x803102
+#define SVR_8547   0x803101
+#define SVR_8548   0x803100
+#define SVR_8555   0x807100
+#define SVR_8560   0x807000
+#define SVR_8567   0x807501
+#define SVR_8568   0x807500
+#define SVR_8569   0x808000
+#define SVR_8572   0x80E000
+#define SVR_P1010  0x80f900
+#define SVR_P2041  0x821001
+#define SVR_P3041  0x821103
+#define SVR_P5010  0x822100
+#define SVR_P5020  0x822000
+#define SVR_P5040  0x820400
+#define SVR_T4240  0x824800
+#define SVR_B4860  0x868800
+
+#endif
-- 
1.8.0


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