RE: [PATCH] drm/pm/swsmu: add ras eeprom i2c function for smu13 v13_0_0

[Zhang, Hawking]

[AMD Official Use Only - General]

Fix typo.

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Zhang, 
Hawking
Sent: Wednesday, July 20, 2022 11:26
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhou1, Tao 
; Clements, John ; Quan, Evan 
; Li, Candice 
Subject: RE: [PATCH] drm/pm/swsmu: add ras eeprom i2c function for smu13 v13_0_0

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Chai, Thomas  
Sent: Wednesday, July 20, 2022 10:49
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Clements, John ; Li, 
Candice ; Chai, Thomas ; Quan, Evan 
; Deucher, Alexander 
Subject: [PATCH] drm/pm/swsmu: add ras eeprom i2c function for smu13 v13_0_0

Add ras eeprom i2c function for smu13 v13_0_0.

Signed-off-by: YiPeng Chai 
Acked-by: Evan Quan 
Acked-by: Alex Deucher 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 157 ++
 1 file changed, 157 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index ce2fa04e3926..2b83191e8006 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -196,6 +196,7 @@ static struct cmn2asic_mapping 
smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(DRIVER_SMU_CONFIG),
TAB_MAP(ACTIVITY_MONITOR_COEFF),
[SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
+   TAB_MAP(I2C_COMMANDS),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] 
= { @@ -1606,9 +1607,165 @@ static bool 
smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
return true;
 }
 
+static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
+  struct i2c_msg *msg, int num_msgs) {
+   struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
+   struct amdgpu_device *adev = smu_i2c->adev;
+   struct smu_context *smu = adev->powerplay.pp_handle;
+   struct smu_table_context *smu_table = &smu->smu_table;
+   struct smu_table *table = &smu_table->driver_table;
+   SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
+   int i, j, r, c;
+   u16 dir;
+
+   if (!adev->pm.dpm_enabled)
+   return -EBUSY;
+
+   req = kzalloc(sizeof(*req), GFP_KERNEL);
+   if (!req)
+   return -ENOMEM;
+
+   req->I2CcontrollerPort = smu_i2c->port;
+   req->I2CSpeed = I2C_SPEED_FAST_400K;
+   req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
+   dir = msg[0].flags & I2C_M_RD;
+
+   for (c = i = 0; i < num_msgs; i++) {
+   for (j = 0; j < msg[i].len; j++, c++) {
+   SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
+
+   if (!(msg[i].flags & I2C_M_RD)) {
+   /* write */
+   cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
+   cmd->ReadWriteData = msg[i].buf[j];
+   }
+
+   if ((dir ^ msg[i].flags) & I2C_M_RD) {
+   /* The direction changes.
+*/
+   dir = msg[i].flags & I2C_M_RD;
+   cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
+   }
+
+   req->NumCmds++;
+
+   /*
+* Insert STOP if we are at the last byte of either last
+* message for the transaction or the client explicitly
+* requires a STOP at this particular message.
+*/
+   if ((j == msg[i].len - 1) &&
+   ((i == num_msgs - 1) || (msg[i].flags & 
I2C_M_STOP))) {
+   cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
+   cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
+   }
+   }
+   }
+   mutex_lock(&adev->pm.mutex);
+   r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
+   mutex_unlock(&adev->pm.mutex);
+   if (r)
+   goto fail;
+
+   for (c = i = 0; i < num_msgs; i++) {
+   if (!(msg[i].flags & I2C_M_RD)) {
+   c += msg[i].len;
+   continue;
+   }
+   for (j = 0; j < msg[i].len; j++, c++) {
+   SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
+
+   msg[i].buf[j] = cmd->ReadWriteData;
+   }
+   }
+   r = num_msgs;
+fail:
+   kfree(req);
+   return r;
+}
+
+static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap) {
+   return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; }
+
+static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
+

RE: [PATCH] drm/pm/swsmu: add ras eeprom i2c function for smu13 v13_0_0

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawing Zhang 

Regards,
Hawking
-Original Message-
From: Chai, Thomas  
Sent: Wednesday, July 20, 2022 10:49
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Clements, John ; Li, 
Candice ; Chai, Thomas ; Quan, Evan 
; Deucher, Alexander 
Subject: [PATCH] drm/pm/swsmu: add ras eeprom i2c function for smu13 v13_0_0

Add ras eeprom i2c function for smu13 v13_0_0.

Signed-off-by: YiPeng Chai 
Acked-by: Evan Quan 
Acked-by: Alex Deucher 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 157 ++
 1 file changed, 157 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index ce2fa04e3926..2b83191e8006 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -196,6 +196,7 @@ static struct cmn2asic_mapping 
smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(DRIVER_SMU_CONFIG),
TAB_MAP(ACTIVITY_MONITOR_COEFF),
[SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
+   TAB_MAP(I2C_COMMANDS),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] 
= { @@ -1606,9 +1607,165 @@ static bool 
smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
return true;
 }
 
+static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
+  struct i2c_msg *msg, int num_msgs) {
+   struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
+   struct amdgpu_device *adev = smu_i2c->adev;
+   struct smu_context *smu = adev->powerplay.pp_handle;
+   struct smu_table_context *smu_table = &smu->smu_table;
+   struct smu_table *table = &smu_table->driver_table;
+   SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
+   int i, j, r, c;
+   u16 dir;
+
+   if (!adev->pm.dpm_enabled)
+   return -EBUSY;
+
+   req = kzalloc(sizeof(*req), GFP_KERNEL);
+   if (!req)
+   return -ENOMEM;
+
+   req->I2CcontrollerPort = smu_i2c->port;
+   req->I2CSpeed = I2C_SPEED_FAST_400K;
+   req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
+   dir = msg[0].flags & I2C_M_RD;
+
+   for (c = i = 0; i < num_msgs; i++) {
+   for (j = 0; j < msg[i].len; j++, c++) {
+   SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
+
+   if (!(msg[i].flags & I2C_M_RD)) {
+   /* write */
+   cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
+   cmd->ReadWriteData = msg[i].buf[j];
+   }
+
+   if ((dir ^ msg[i].flags) & I2C_M_RD) {
+   /* The direction changes.
+*/
+   dir = msg[i].flags & I2C_M_RD;
+   cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
+   }
+
+   req->NumCmds++;
+
+   /*
+* Insert STOP if we are at the last byte of either last
+* message for the transaction or the client explicitly
+* requires a STOP at this particular message.
+*/
+   if ((j == msg[i].len - 1) &&
+   ((i == num_msgs - 1) || (msg[i].flags & 
I2C_M_STOP))) {
+   cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
+   cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
+   }
+   }
+   }
+   mutex_lock(&adev->pm.mutex);
+   r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
+   mutex_unlock(&adev->pm.mutex);
+   if (r)
+   goto fail;
+
+   for (c = i = 0; i < num_msgs; i++) {
+   if (!(msg[i].flags & I2C_M_RD)) {
+   c += msg[i].len;
+   continue;
+   }
+   for (j = 0; j < msg[i].len; j++, c++) {
+   SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
+
+   msg[i].buf[j] = cmd->ReadWriteData;
+   }
+   }
+   r = num_msgs;
+fail:
+   kfree(req);
+   return r;
+}
+
+static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap) {
+   return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; }
+
+static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
+   .master_xfer = smu_v13_0_0_i2c_xfer,
+   .functionality = smu_v13_0_0_i2c_func, };
+
+static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
+   .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
+   .max_read_len  = MAX_SW_I2C_COMMANDS,
+   .max_write_len = MAX_SW_I2C_COMMANDS,
+   .max_comb_1st_msg_len = 2,
+   .max_comb_

[PATCH] drm/amdgpu: use native mode for dp aux transfer

[Zhenneng Li]

When using amdgpu for e8860, the monitor sometimes haven't any signal,
and the kernel reports some errors:
[   17.317302][ 2] [ T1045] [drm:amdgpu_atombios_dp_link_train [amdgpu]] 
*ERROR* channel eq failed: 5 tries
[   17.326963][ 2] [ T1045] [drm:amdgpu_atombios_dp_link_train [amdgpu]] 
*ERROR* channel eq failed
But if I use radeon for e8860, everything are always normal, the reason is
that radeon use native mode and amdgpu use atombios mode
when init dp aux, so when I use native mode for amdgpu, everything
are always normal.

Signed-off-by: Zhenneng Li 
Change-Id: Ia9a2be3ab03e56b1c8337fdbf713461196fbc58f
---
 drivers/gpu/drm/amd/amdgpu/Makefile  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c |   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_dp_auxch.c | 273 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h |   2 +
 drivers/gpu/drm/amd/amdgpu/atombios_dp.c |   5 +-
 7 files changed, 290 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_dp_auxch.c

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3e0e2eb7e235..2913cf46f848 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,7 +58,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
-   amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o
+   amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o 
amdgpu_dp_auxch.o
 
 amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 30ce6bb6fa77..15e0288b1997 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -238,6 +238,8 @@ extern int amdgpu_num_kcq;
 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
 extern int amdgpu_vcnfw_log;
 
+extern int amdgpu_auxch;
+
 #define AMDGPU_VM_MAX_NUM_CTX  4096
 #define AMDGPU_SG_THRESHOLD(256*1024*1024)
 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 9ba4817a9148..68c8d79e2937 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -49,7 +49,10 @@ static struct amdgpu_i2c_bus_rec 
amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_G
 
memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
 
-   i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
+   if (amdgpu_auxch)
+   i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 
4;
+   else
+   i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dp_auxch.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dp_auxch.c
new file mode 100644
index ..22078f1ca936
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dp_auxch.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2015 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ */
+
+#include "amdgpu.h"
+
+#defineAUX_SW_RX_OVERFLOW  (1 << 8)
+#defineAUX_SW_RX_HPD_DISCON(1 << 9)
+#defineAUX_SW_RX_PARTIAL_BYTE  (1 << 10)
+#defineAUX_SW_NON_AUX_MODE (1 << 11)
+#defineAUX_SW_RX_SYNC_IN

[PATCH] drm/pm/swsmu: add ras eeprom i2c function for smu13 v13_0_0

[YiPeng Chai]

Add ras eeprom i2c function for smu13 v13_0_0.

Signed-off-by: YiPeng Chai 
Acked-by: Evan Quan 
Acked-by: Alex Deucher 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 157 ++
 1 file changed, 157 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index ce2fa04e3926..2b83191e8006 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -196,6 +196,7 @@ static struct cmn2asic_mapping 
smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(DRIVER_SMU_CONFIG),
TAB_MAP(ACTIVITY_MONITOR_COEFF),
[SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
+   TAB_MAP(I2C_COMMANDS),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] 
= {
@@ -1606,9 +1607,165 @@ static bool smu_v13_0_0_is_mode1_reset_supported(struct 
smu_context *smu)
return true;
 }
 
+static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
+  struct i2c_msg *msg, int num_msgs)
+{
+   struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
+   struct amdgpu_device *adev = smu_i2c->adev;
+   struct smu_context *smu = adev->powerplay.pp_handle;
+   struct smu_table_context *smu_table = &smu->smu_table;
+   struct smu_table *table = &smu_table->driver_table;
+   SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
+   int i, j, r, c;
+   u16 dir;
+
+   if (!adev->pm.dpm_enabled)
+   return -EBUSY;
+
+   req = kzalloc(sizeof(*req), GFP_KERNEL);
+   if (!req)
+   return -ENOMEM;
+
+   req->I2CcontrollerPort = smu_i2c->port;
+   req->I2CSpeed = I2C_SPEED_FAST_400K;
+   req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
+   dir = msg[0].flags & I2C_M_RD;
+
+   for (c = i = 0; i < num_msgs; i++) {
+   for (j = 0; j < msg[i].len; j++, c++) {
+   SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
+
+   if (!(msg[i].flags & I2C_M_RD)) {
+   /* write */
+   cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
+   cmd->ReadWriteData = msg[i].buf[j];
+   }
+
+   if ((dir ^ msg[i].flags) & I2C_M_RD) {
+   /* The direction changes.
+*/
+   dir = msg[i].flags & I2C_M_RD;
+   cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
+   }
+
+   req->NumCmds++;
+
+   /*
+* Insert STOP if we are at the last byte of either last
+* message for the transaction or the client explicitly
+* requires a STOP at this particular message.
+*/
+   if ((j == msg[i].len - 1) &&
+   ((i == num_msgs - 1) || (msg[i].flags & 
I2C_M_STOP))) {
+   cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
+   cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
+   }
+   }
+   }
+   mutex_lock(&adev->pm.mutex);
+   r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
+   mutex_unlock(&adev->pm.mutex);
+   if (r)
+   goto fail;
+
+   for (c = i = 0; i < num_msgs; i++) {
+   if (!(msg[i].flags & I2C_M_RD)) {
+   c += msg[i].len;
+   continue;
+   }
+   for (j = 0; j < msg[i].len; j++, c++) {
+   SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
+
+   msg[i].buf[j] = cmd->ReadWriteData;
+   }
+   }
+   r = num_msgs;
+fail:
+   kfree(req);
+   return r;
+}
+
+static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
+{
+   return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
+   .master_xfer = smu_v13_0_0_i2c_xfer,
+   .functionality = smu_v13_0_0_i2c_func,
+};
+
+static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
+   .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
+   .max_read_len  = MAX_SW_I2C_COMMANDS,
+   .max_write_len = MAX_SW_I2C_COMMANDS,
+   .max_comb_1st_msg_len = 2,
+   .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
+};
+
+static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   int res, i;
+
+   for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
+   struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
+   struct i2c_adapter *control = &smu_i2c->adapter;
+
+   smu_i2c->ade

Re: [PATCH 1/2] drm/amdgpu: add the IP discovery IP versions for HW INFO data

[Marek Olšák]

Reviewed-by: Marek Olšák 

for the series.

Marek

On Tue, Jul 19, 2022 at 3:53 PM Alex Deucher  wrote:

> Ping on this series.
>
> Alex
>
> On Fri, Jul 8, 2022 at 6:56 PM Alex Deucher 
> wrote:
> >
> > Use the former pad element to store the IP versions from the
> > IP discovery table.  This allows userspace to get the IP
> > version from the kernel to better align with hardware IP
> > versions.
> >
> > Proposed mesa patch:
> >
> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075
> >
> > Signed-off-by: Alex Deucher 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 24 
> >  include/uapi/drm/amdgpu_drm.h   |  3 ++-
> >  2 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index 4b44a4bc2fb3..7e03f3719d11 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -473,6 +473,30 @@ static int amdgpu_hw_ip_info(struct amdgpu_device
> *adev,
> >
> > result->hw_ip_version_major = adev->ip_blocks[i].version->major;
> > result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
> > +
> > +   if (adev->asic_type >= CHIP_VEGA10) {
> > +   switch (type) {
> > +   case AMD_IP_BLOCK_TYPE_GFX:
> > +   result->ip_discovery_version =
> adev->ip_versions[GC_HWIP][0];
> > +   break;
> > +   case AMD_IP_BLOCK_TYPE_SDMA:
> > +   result->ip_discovery_version =
> adev->ip_versions[SDMA0_HWIP][0];
> > +   break;
> > +   case AMD_IP_BLOCK_TYPE_UVD:
> > +   case AMD_IP_BLOCK_TYPE_VCN:
> > +   case AMD_IP_BLOCK_TYPE_JPEG:
> > +   result->ip_discovery_version =
> adev->ip_versions[UVD_HWIP][0];
> > +   break;
> > +   case AMD_IP_BLOCK_TYPE_VCE:
> > +   result->ip_discovery_version =
> adev->ip_versions[VCE_HWIP][0];
> > +   break;
> > +   default:
> > +   result->ip_discovery_version = 0;
> > +   break;
> > +   }
> > +   } else {
> > +   result->ip_discovery_version = 0;
> > +   }
> > result->capabilities_flags = 0;
> > result->available_rings = (1 << num_rings) - 1;
> > result->ib_start_alignment = ib_start_alignment;
> > diff --git a/include/uapi/drm/amdgpu_drm.h
> b/include/uapi/drm/amdgpu_drm.h
> > index 18d3246d636e..3a2674b4a2d9 100644
> > --- a/include/uapi/drm/amdgpu_drm.h
> > +++ b/include/uapi/drm/amdgpu_drm.h
> > @@ -1093,7 +1093,8 @@ struct drm_amdgpu_info_hw_ip {
> > __u32  ib_size_alignment;
> > /** Bitmask of available rings. Bit 0 means ring 0, etc. */
> > __u32  available_rings;
> > -   __u32  _pad;
> > +   /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
> > +   __u32  ip_discovery_version;
> >  };
> >
> >  struct drm_amdgpu_info_num_handles {
> > --
> > 2.35.3
> >
>

RE: [PATCH 1/2] drm/amdgpu: modify mcbp implement for gfx9

[Zhu, Jiadong]

[AMD Official Use Only - General]

Hi Christian,

There is an imbed project based on xen. One of the guest vm with high priority 
jobs needs to send preemption against the other vm.
There are some works in other component including umd and qemu, etc. For kmd, 
we just modify the mcbp related functions to pass the unit test.

Thanks,
Jiadong

-Original Message-
From: Koenig, Christian 
Sent: Tuesday, July 19, 2022 9:59 PM
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Liu, Aaron 
Subject: Re: [PATCH 1/2] drm/amdgpu: modify mcbp implement for gfx9

Well what's the background for this?

So far MCBP isn't a validated feature, we just added some debugfs interface for 
testing it.

Regards,
Christian.

Am 19.07.22 um 04:09 schrieb jiadong@amd.com:
> From: "Jiadong.Zhu" 
>
> 1. Use unmap_queue package to trigger preemption on gfx9
> Add trailing fence to track the preemption done.
> 2. Modify emit_ce_meta emit_de_meta functions
> for the resumed ibs.
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 156 ---
>   drivers/gpu/drm/amd/amdgpu/soc15d.h  |   2 +
>   3 files changed, 138 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 82c178a9033a..ca626f0ad7b1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -59,6 +59,7 @@ enum amdgpu_ring_priority_level {
>   #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
>   #define AMDGPU_FENCE_FLAG_INT   (1 << 1)
>   #define AMDGPU_FENCE_FLAG_TC_WB_ONLY(1 << 2)
> +#define AMDGPU_FENCE_FLAG_EXEC  (1 << 3)
>
>   #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring,
> sched)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 5332899642dc..e2c614441691 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -751,7 +751,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device 
> *adev);
>   static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
>   struct amdgpu_cu_info *cu_info);
>   static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device
> *adev); -static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
> *ring);
> +static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool
> +resume);
>   static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
>   static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
> void *ras_error_status);
> @@ -824,9 +824,10 @@ static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring 
> *kiq_ring,
>   
> PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
>
>   if (action == PREEMPT_QUEUES_NO_UNMAP) {
> - amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
> - amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
> - amdgpu_ring_write(kiq_ring, seq);
> + amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & 
> ring->buf_mask));
> + amdgpu_ring_write(kiq_ring, 0);
> + amdgpu_ring_write(kiq_ring, 0);
> +
>   } else {
>   amdgpu_ring_write(kiq_ring, 0);
>   amdgpu_ring_write(kiq_ring, 0);
> @@ -5446,11 +5447,15 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct
> amdgpu_ring *ring,
>
>   control |= ib->length_dw | (vmid << 24);
>
> - if (amdgpu_sriov_vf(ring->adev) && (ib->flags & 
> AMDGPU_IB_FLAG_PREEMPT)) {
> + if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
> +AMDGPU_IB_FLAG_PREEMPT)) {
>   control |= INDIRECT_BUFFER_PRE_ENB(1);
>
> + if (flags & AMDGPU_IB_PREEMPTED)
> + control |= INDIRECT_BUFFER_PRE_RESUME(1);
> +
>   if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
> - gfx_v9_0_ring_emit_de_meta(ring);
> + gfx_v9_0_ring_emit_de_meta(ring,
> +  (!amdgpu_sriov_vf(ring->adev) && flags & 
> AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   }
>
>   amdgpu_ring_write(ring, header);
> @@ -5505,6 +5510,7 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring 
> *ring, u64 addr,
>   bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
>   bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
>   bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
> + bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
>
>   /* RELEASE_MEM - flush caches, send int */
>   amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); @@
> -5515,6 +5521,7 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring 
> *ring, u64 addr,
>  EOP_TC_WB_ACTION_EN |
>  EOP_TC_MD_ACTION_EN)) 

[PATCH] drm/amd/display: reduce stack size in dcn32 dml

[Alex Deucher]

Move additional dummy structures off the stack and into
the dummy vars structure.

Fixes the following:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In 
function 
'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1659:1:
 error: the frame size of 2144 bytes is larger than 2048 bytes 
[-Werror=frame-larger-than=]
 1659 | }
  | ^
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In 
function 'dml32_ModeSupportAndSystemConfigurationFull':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
 error: the frame size of 2464 bytes is larger than 2048 bytes 
[-Werror=frame-larger-than=]
 3799 | } // ModeSupportAndSystemConfigurationFull
  | ^

Signed-off-by: Alex Deucher 
Cc: Stephen Rothwell 
---
 .../dc/dml/dcn32/display_mode_vba_32.c| 214 --
 .../drm/amd/display/dc/dml/display_mode_vba.h |   3 +
 2 files changed, 100 insertions(+), 117 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 349e36ae9333..441311cb9a86 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -67,6 +67,18 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
int iteration;
double MaxTotalRDBandwidth;
unsigned int NextPrefetchMode;
+   double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
+   bool DestinationLineTimesForPrefetchLessThan2 = false;
+   bool VRatioPrefetchMoreThanMax = false;
+   double dummy_unit_vector[DC__NUM_DPP__MAX];
+   double TWait;
+   double dummy_single[2];
+   bool dummy_boolean[1];
+   enum clock_change_support dummy_dramchange_support;
+   enum dm_fclock_change_support dummy_fclkchange_support;
+   bool dummy_USRRetrainingSupport;
+   double TotalWRBandwidth = 0;
+   double WRBandwidth = 0;
 
 #ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: --- START ---\n", __func__);
@@ -702,11 +714,6 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
NextPrefetchMode = 
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb];
 
do {
-   double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
-   bool DestinationLineTimesForPrefetchLessThan2 = false;
-   bool VRatioPrefetchMoreThanMax = false;
-   double dummy_unit_vector[DC__NUM_DPP__MAX];
-
MaxTotalRDBandwidth = 0;
 #ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, 
mode_lib->vba.VStartupLines);
@@ -715,41 +722,39 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
/* NOTE PerfetchMode variable is invalid in DAL as per 
the input received.
 * Hence the direction is to use PrefetchModePerState.
 */
-   double TWait = dml32_CalculateTWait(
-   
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
-   
mode_lib->vba.UsesMALLForPStateChange[k],
-   
mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
-   mode_lib->vba.DRRDisplay[k],
-   mode_lib->vba.DRAMClockChangeLatency,
-   mode_lib->vba.FCLKChangeLatency, 
v->UrgentLatency,
-   mode_lib->vba.SREnterPlusExitTime);
-
-   DmlPipe myPipe;
-
-   myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
-   myPipe.Dispclk = mode_lib->vba.DISPCLK;
-   myPipe.PixelClock = mode_lib->vba.PixelClock[k];
-   myPipe.DCFClkDeepSleep = v->DCFCLKDeepSleep;
-   myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
-   myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
-   myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
-   myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
-   myPipe.BlockHeight256BytesY = 
v->BlockHeight256BytesY[k];
-   myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
-   myPipe.BlockHeight256BytesC = 
v->BlockHeight256BytesC[k];
-   myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
-   myPipe.NumberOfCursors = 
mode_lib->vba.NumberOfCursors[k];
-   myPipe.VBlank = mode_lib->vba.VTotal[k] - 
mode_lib

Re: [PATCH v1 4/6] dma-buf: Acquire wait-wound context on attachment

[Dmitry Osipenko]

On 7/15/22 09:59, Dmitry Osipenko wrote:
> On 7/15/22 09:50, Christian König wrote:
>> Am 15.07.22 um 02:52 schrieb Dmitry Osipenko:
>>> Intel i915 GPU driver uses wait-wound mutex to lock multiple GEMs on the
>>> attachment to the i915 dma-buf. In order to let all drivers utilize
>>> shared
>>> wait-wound context during attachment in a general way, make dma-buf
>>> core to
>>> acquire the ww context internally for the attachment operation and update
>>> i915 driver to use the importer's ww context instead of the internal one.
>>>
>>>  From now on all dma-buf exporters shall use the importer's ww context
>>> for
>>> the attachment operation.
>>>
>>> Signed-off-by: Dmitry Osipenko 
>>> ---
>>>   drivers/dma-buf/dma-buf.c |  8 +-
>>>   drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c    |  2 +-
>>>   .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  2 +-
>>>   drivers/gpu/drm/i915/gem/i915_gem_object.h    |  6 ++---
>>>   drivers/gpu/drm/i915/i915_gem_evict.c |  2 +-
>>>   drivers/gpu/drm/i915/i915_gem_ww.c    | 26 +++
>>>   drivers/gpu/drm/i915/i915_gem_ww.h    | 15 +--
>>>   7 files changed, 47 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
>>> index 0ee588276534..37545ecb845a 100644
>>> --- a/drivers/dma-buf/dma-buf.c
>>> +++ b/drivers/dma-buf/dma-buf.c
>>> @@ -807,6 +807,8 @@ static struct sg_table * __map_dma_buf(struct
>>> dma_buf_attachment *attach,
>>>    * Optionally this calls &dma_buf_ops.attach to allow
>>> device-specific attach
>>>    * functionality.
>>>    *
>>> + * Exporters shall use ww_ctx acquired by this function.
>>> + *
>>>    * Returns:
>>>    *
>>>    * A pointer to newly created &dma_buf_attachment on success, or a
>>> negative
>>> @@ -822,6 +824,7 @@ dma_buf_dynamic_attach_unlocked(struct dma_buf
>>> *dmabuf, struct device *dev,
>>>   void *importer_priv)
>>>   {
>>>   struct dma_buf_attachment *attach;
>>> +    struct ww_acquire_ctx ww_ctx;
>>>   int ret;
>>>     if (WARN_ON(!dmabuf || !dev))
>>> @@ -841,7 +844,8 @@ dma_buf_dynamic_attach_unlocked(struct dma_buf
>>> *dmabuf, struct device *dev,
>>>   attach->importer_ops = importer_ops;
>>>   attach->importer_priv = importer_priv;
>>>   -    dma_resv_lock(dmabuf->resv, NULL);
>>> +    ww_acquire_init(&ww_ctx, &reservation_ww_class);
>>> +    dma_resv_lock(dmabuf->resv, &ww_ctx);
>>
>> That won't work like this. The core property of a WW context is that you
>> need to unwind all the locks and re-quire them with the contended one
>> first.
>>
>> When you statically lock the imported one here you can't do that any more.
> 
> You're right. I felt that something is missing here, but couldn't
> notice. I'll think more about this and enable
> CONFIG_DEBUG_WW_MUTEX_SLOWPATH. Thank you!
> 

Christian, do you think we could make an excuse for the attach()
callback and make the exporter responsible for taking the resv lock? It
will be inconsistent with the rest of the callbacks, where importer
takes the lock, but it will be the simplest and least invasive solution.
It's very messy to do a cross-driver ww locking, I don't think it's the
right approach.

-- 
Best regards,
Dmitry

Re: [PATCH 1/2] drm/amdgpu: add the IP discovery IP versions for HW INFO data

[Alex Deucher]

Ping on this series.

Alex

On Fri, Jul 8, 2022 at 6:56 PM Alex Deucher  wrote:
>
> Use the former pad element to store the IP versions from the
> IP discovery table.  This allows userspace to get the IP
> version from the kernel to better align with hardware IP
> versions.
>
> Proposed mesa patch:
> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 24 
>  include/uapi/drm/amdgpu_drm.h   |  3 ++-
>  2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 4b44a4bc2fb3..7e03f3719d11 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -473,6 +473,30 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
>
> result->hw_ip_version_major = adev->ip_blocks[i].version->major;
> result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
> +
> +   if (adev->asic_type >= CHIP_VEGA10) {
> +   switch (type) {
> +   case AMD_IP_BLOCK_TYPE_GFX:
> +   result->ip_discovery_version = 
> adev->ip_versions[GC_HWIP][0];
> +   break;
> +   case AMD_IP_BLOCK_TYPE_SDMA:
> +   result->ip_discovery_version = 
> adev->ip_versions[SDMA0_HWIP][0];
> +   break;
> +   case AMD_IP_BLOCK_TYPE_UVD:
> +   case AMD_IP_BLOCK_TYPE_VCN:
> +   case AMD_IP_BLOCK_TYPE_JPEG:
> +   result->ip_discovery_version = 
> adev->ip_versions[UVD_HWIP][0];
> +   break;
> +   case AMD_IP_BLOCK_TYPE_VCE:
> +   result->ip_discovery_version = 
> adev->ip_versions[VCE_HWIP][0];
> +   break;
> +   default:
> +   result->ip_discovery_version = 0;
> +   break;
> +   }
> +   } else {
> +   result->ip_discovery_version = 0;
> +   }
> result->capabilities_flags = 0;
> result->available_rings = (1 << num_rings) - 1;
> result->ib_start_alignment = ib_start_alignment;
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 18d3246d636e..3a2674b4a2d9 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -1093,7 +1093,8 @@ struct drm_amdgpu_info_hw_ip {
> __u32  ib_size_alignment;
> /** Bitmask of available rings. Bit 0 means ring 0, etc. */
> __u32  available_rings;
> -   __u32  _pad;
> +   /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
> +   __u32  ip_discovery_version;
>  };
>
>  struct drm_amdgpu_info_num_handles {
> --
> 2.35.3
>

Re: [PATCH] drm/amdgpu: Fix comment typo

[Alex Deucher]

Applied.  Thanks!

On Tue, Jul 19, 2022 at 8:34 AM Christian König
 wrote:
>
> Am 16.07.22 um 06:28 schrieb Jason Wang:
> > The double `to' is duplicated in the comment, remove one.
> >
> > Signed-off-by: Jason Wang 
>
> Reviewed-by: Christian König 
>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index e3d139708160..b45cd7cbbea8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -80,7 +80,7 @@
> >* - 3.24.0 - Add high priority compute support for gfx9
> >* - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
> >* - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
> > - * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
> > + * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
> >* - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
> >* - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
> >* - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
>

Re: [PATCH] drm/radeon: Fix comment typo

[Alex Deucher]

Applied.  Thanks!

On Tue, Jul 19, 2022 at 8:33 AM Christian König
 wrote:
>
> Am 16.07.22 um 05:57 schrieb Jason Wang:
> > The double `have' is duplicated in line 696, remove one.
> >
> > Signed-off-by: Jason Wang 
>
> Reviewed-by: Christian König 
>
> > ---
> >   drivers/gpu/drm/radeon/radeon_gem.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
> > b/drivers/gpu/drm/radeon/radeon_gem.c
> > index 84843b3b3aef..261fcbae88d7 100644
> > --- a/drivers/gpu/drm/radeon/radeon_gem.c
> > +++ b/drivers/gpu/drm/radeon/radeon_gem.c
> > @@ -693,7 +693,7 @@ int radeon_gem_va_ioctl(struct drm_device *dev, void 
> > *data,
> >   }
> >
> >   /* !! DONT REMOVE !!
> > -  * We don't support vm_id yet, to be sure we don't have have broken
> > +  * We don't support vm_id yet, to be sure we don't have broken
> >* userspace, reject anyone trying to use non 0 value thus moving
> >* forward we can use those fields without breaking existant userspace
> >*/
>

Re: [PATCH] drm/amdgpu: Remove one duplicated ef removal

[Alex Deucher]

On Tue, Jul 19, 2022 at 4:32 AM Mike Lothian  wrote:
>
> With this patch applied on Linus's tree 5.18-rc7 I get the following warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1367:20: warning:
> unused variable 'pd' [-Wunused-variable]
>struct amdgpu_bo *pd = vm->root.bo;
>  ^
> 1 warning generated.
>
> It does fix the nullpointer though :D

I fixed that up when I pulled the patch in.

Alex

>
>
> On Fri, 8 Jul 2022 at 02:55, xinhui pan  wrote:
> >
> > That has been done in BO release notify.
> >
> > Signed-off-by: xinhui pan 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 -
> >  1 file changed, 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> > index 0f9811d02f61..49536fa8d269 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> > @@ -1583,11 +1583,6 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct 
> > amdgpu_device *adev,
> > if (!process_info)
> > return;
> >
> > -   /* Release eviction fence from PD */
> > -   amdgpu_bo_reserve(pd, false);
> > -   amdgpu_bo_fence(pd, NULL, false);
> > -   amdgpu_bo_unreserve(pd);
> > -
> > /* Update process info */
> > mutex_lock(&process_info->lock);
> > process_info->n_vms--;
> > --
> > 2.34.1
> >

Re: [PATCH 1/2] drm/amd/display: Disable dmcu fw loading for dcn314

[Harry Wentland]

On 2022-07-19 14:26, roman...@amd.com wrote:
> From: Roman Li 
> 
> [Why]
> DCN 3.1.4 uses dmub not dmcu. Attempt to identify
> dmcu firmware for dcn314 results in dm init error:
> "Unsupported ASIC type"
> 
> [How]
> Add dcn314 to the list of asics that don't require dmcu
> 
> Signed-off-by: Roman Li 

Reviewed-by: Harry Wentland 

Might be easier going forward if we simply return 0 in the
outside case statement instead of explicitly calling out
IPs that don't support DMCU. The default (any new ASIC) won't
support DMCU.

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index dae998e014b0..9fff5aa86567 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1893,6 +1893,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
>   case IP_VERSION(3, 0, 1):
>   case IP_VERSION(3, 1, 2):
>   case IP_VERSION(3, 1, 3):
> + case IP_VERSION(3, 1, 4):
>   case IP_VERSION(3, 1, 5):
>   case IP_VERSION(3, 1, 6):
>   case IP_VERSION(3, 2, 0):

[PATCH] drm/amdgpu: fix check in fbdev init

[Alex Deucher]

The new vkms virtual display code is atomic so there is
no need to call drm_helper_disable_unused_functions()
when it is enabled.  Doing so can result in a segfault.
When the driver switched from the old virtual display code
to the new atomic virtual display code, it was missed that
we enable virtual display unconditionally under SR-IOV
so the checks here missed that case.  Add the missing
check for SR-IOV.

There is no equivalent of this patch for Linus' tree
because the relevant code no longer exists.  This patch
is only relevant to kernels 5.15 and 5.16.

Fixes: 84ec374bd580 ("drm/amdgpu: create amdgpu_vkms (v4)")
Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org # 5.15.x
Cc: hgof...@amazon.com
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index cd0acbea75da..d58ab9deb028 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -341,7 +341,8 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev)
}
 
/* disable all the possible outputs/crtcs before entering KMS mode */
-   if (!amdgpu_device_has_dc_support(adev) && !amdgpu_virtual_display)
+   if (!amdgpu_device_has_dc_support(adev) && !amdgpu_virtual_display &&
+   !amdgpu_sriov_vf(adev))
drm_helper_disable_unused_functions(adev_to_drm(adev));
 
drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
-- 
2.35.3

[PATCH 4/4] drm/amdgpu: clarify DC checks

[Alex Deucher]

There are several places where we don't want to check
if a particular asic could support DC, but rather, if
DC is enabled.  Set a flag if DC is enabled and check
for that rather than if a device supports DC or not.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 32 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  4 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  2 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  1 +
 .../gpu/drm/amd/pm/powerplay/amd_powerplay.c  |  2 +-
 8 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f111694cea2f..889db62d2ee8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1059,6 +1059,8 @@ struct amdgpu_device {
uint32_tscpm_status;
 
struct work_struct  reset_work;
+
+   booldc_enabled;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 130060834b4e..fbec4191c5b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -846,7 +846,7 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;
 
if (atif->notifications.brightness_change) {
-   if (amdgpu_device_has_dc_support(adev)) {
+   if (adev->dc_enabled) {
 #if defined(CONFIG_DRM_AMD_DC)
struct amdgpu_display_manager *dm = &adev->dm;
if (dm->backlight_dev[0])
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index f3b3c688e4e7..fe85eb9ebd09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1755,7 +1755,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
amdgpu_ta_if_debugfs_init(adev);
 
 #if defined(CONFIG_DRM_AMD_DC)
-   if (amdgpu_device_has_dc_support(adev))
+   if (adev->dc_enabled)
dtn_debugfs_init(adev);
 #endif
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f7ffd60e1dd6..ee25a227bbb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4153,25 +4153,27 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
fbcon)
 
amdgpu_ras_resume(adev);
 
-   /*
-* Most of the connector probing functions try to acquire runtime pm
-* refs to ensure that the GPU is powered on when connector polling is
-* performed. Since we're calling this from a runtime PM callback,
-* trying to acquire rpm refs will cause us to deadlock.
-*
-* Since we're guaranteed to be holding the rpm lock, it's safe to
-* temporarily disable the rpm helpers so this doesn't deadlock us.
-*/
+   if (adev->mode_info.num_crtc) {
+   /*
+* Most of the connector probing functions try to acquire 
runtime pm
+* refs to ensure that the GPU is powered on when connector 
polling is
+* performed. Since we're calling this from a runtime PM 
callback,
+* trying to acquire rpm refs will cause us to deadlock.
+*
+* Since we're guaranteed to be holding the rpm lock, it's safe 
to
+* temporarily disable the rpm helpers so this doesn't deadlock 
us.
+*/
 #ifdef CONFIG_PM
-   dev->dev->power.disable_depth++;
+   dev->dev->power.disable_depth++;
 #endif
-   if (!amdgpu_device_has_dc_support(adev))
-   drm_helper_hpd_irq_event(dev);
-   else
-   drm_kms_helper_hotplug_event(dev);
+   if (!adev->dc_enabled)
+   drm_helper_hpd_irq_event(dev);
+   else
+   drm_kms_helper_hotplug_event(dev);
 #ifdef CONFIG_PM
-   dev->dev->power.disable_depth--;
+   dev->dev->power.disable_depth--;
 #endif
+   }
adev->in_suspend = false;
 
if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 220554e7c548..ec2bebcec968 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -549,7 +549,7 @@ uint32_t amdgpu_display_supported_domains(struct 
amdgpu_device *adev,
 */
if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
amdgpu_bo_suppor

[PATCH 3/4] drm/amdgpu: move non-DC vblank handling out of irq code

[Alex Deucher]

Move it into the DCE code for each generation. This avoids
confusion with the different display paths.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 35 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 58 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c| 12 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  | 13 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  | 13 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   | 14 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   | 14 +
 8 files changed, 103 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index b0fa5d065d50..220554e7c548 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -44,6 +44,41 @@
 #include 
 #include 
 
+/**
+ * amdgpu_display_hotplug_work_func - work handler for display hotplug event
+ *
+ * @work: work struct pointer
+ *
+ * This is the hotplug event work handler (all ASICs).
+ * The work gets scheduled from the IRQ handler if there
+ * was a hotplug interrupt.  It walks through the connector table
+ * and calls hotplug handler for each connector. After this, it sends
+ * a DRM hotplug event to alert userspace.
+ *
+ * This design approach is required in order to defer hotplug event handling
+ * from the IRQ handler to a work handler because hotplug handler has to use
+ * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
+ * sleep).
+ */
+void amdgpu_display_hotplug_work_func(struct work_struct *work)
+{
+   struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+ hotplug_work);
+   struct drm_device *dev = adev_to_drm(adev);
+   struct drm_mode_config *mode_config = &dev->mode_config;
+   struct drm_connector *connector;
+   struct drm_connector_list_iter iter;
+
+   mutex_lock(&mode_config->mutex);
+   drm_connector_list_iter_begin(dev, &iter);
+   drm_for_each_connector_iter(connector, &iter)
+   amdgpu_connector_hotplug(connector);
+   drm_connector_list_iter_end(&iter);
+   mutex_unlock(&mode_config->mutex);
+   /* Just fire off a uevent and let userspace tell us what to do */
+   drm_helper_hpd_irq_event(dev);
+}
+
 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
   struct amdgpu_framebuffer *rfb,
   const struct drm_mode_fb_cmd2 
*mode_cmd,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
index 560352f7c317..9d19940f73c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
@@ -35,6 +35,7 @@
 #define amdgpu_display_add_encoder(adev, e, s, c) 
(adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) 
(adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), 
(h), (r))
 
+void amdgpu_display_hotplug_work_func(struct work_struct *work);
 void amdgpu_display_update_priority(struct amdgpu_device *adev);
 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
  uint64_t bo_flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 89011bae7588..a6aef488a822 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -100,41 +100,6 @@ const char *soc15_ih_clientid_name[] = {
"MP1"
 };
 
-/**
- * amdgpu_hotplug_work_func - work handler for display hotplug event
- *
- * @work: work struct pointer
- *
- * This is the hotplug event work handler (all ASICs).
- * The work gets scheduled from the IRQ handler if there
- * was a hotplug interrupt.  It walks through the connector table
- * and calls hotplug handler for each connector. After this, it sends
- * a DRM hotplug event to alert userspace.
- *
- * This design approach is required in order to defer hotplug event handling
- * from the IRQ handler to a work handler because hotplug handler has to use
- * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
- * sleep).
- */
-static void amdgpu_hotplug_work_func(struct work_struct *work)
-{
-   struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
- hotplug_work);
-   struct drm_device *dev = adev_to_drm(adev);
-   struct drm_mode_config *mode_config = &dev->mode_config;
-   struct drm_connector *connector;
-   struct drm_connector_list_iter iter;
-
-   mutex_lock(&mode_config->mutex);
-   drm_connector_list_iter_begin(dev, &iter);
-   drm_for_each_connector_iter(connector, &iter

[PATCH 1/4] drm/amdgpu: use proper DC check in amdgpu_display_supported_domains()

[Alex Deucher]

amdgpu_device_asic_has_dc_support() just checks the asic itself.
amdgpu_device_has_dc_support() is a runtime check which not
only checks the asic, but also other things in the driver
like whether virtual display is enabled.  We want the latter
here.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index c20922a5af9f..b0fa5d065d50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -514,7 +514,7 @@ uint32_t amdgpu_display_supported_domains(struct 
amdgpu_device *adev,
 */
if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
amdgpu_bo_support_uswc(bo_flags) &&
-   amdgpu_device_asic_has_dc_support(adev->asic_type) &&
+   amdgpu_device_has_dc_support(adev) &&
adev->mode_info.gpu_vm_support)
domain |= AMDGPU_GEM_DOMAIN_GTT;
 #endif
-- 
2.35.3

[PATCH 2/4] drm/amdgpu: rework SR-IOV virtual display handling

[Alex Deucher]

virtual display is enabled unconditionally in SR-IOV, but
without specifying the virtual_display module, the number
of crtcs defaults to 0.  Set a single display by default
for SR-IOV if the virtual_display parameter is not set.
Only enable virtual display by default on SR-IOV on asics
which actually have display hardware.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 13 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 18 +++---
 drivers/gpu/drm/amd/amdgpu/vi.c   |  6 --
 4 files changed, 32 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1734d967c35e..f111694cea2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1116,6 +1116,8 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device 
*adev,
 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
 
+void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
+
 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 struct amdgpu_reset_context *reset_context);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 041bd906449d..f7ffd60e1dd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1915,6 +1915,16 @@ static void amdgpu_device_enable_virtual_display(struct 
amdgpu_device *adev)
}
 }
 
+void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
+{
+   if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
+   adev->mode_info.num_crtc = 1;
+   adev->enable_virtual_display = true;
+   DRM_INFO("virtual_display:%d, num_crtc:%d\n",
+adev->enable_virtual_display, 
adev->mode_info.num_crtc);
+   }
+}
+
 /**
  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
  *
@@ -3317,8 +3327,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type 
asic_type)
  */
 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
 {
-   if (amdgpu_sriov_vf(adev) ||
-   adev->enable_virtual_display ||
+   if (adev->enable_virtual_display ||
(adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
return false;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 22144ba6c7ec..ced70bf3e14a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1698,9 +1698,15 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct 
amdgpu_device *adev)
return 0;
 }
 
+static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
+{
+   amdgpu_device_set_sriov_virtual_display(adev);
+   amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
+}
+
 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
 {
-   if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
+   if (adev->enable_virtual_display) {
amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
return 0;
}
@@ -1727,7 +1733,10 @@ static int amdgpu_discovery_set_display_ip_blocks(struct 
amdgpu_device *adev)
case IP_VERSION(3, 1, 6):
case IP_VERSION(3, 2, 0):
case IP_VERSION(3, 2, 1):
-   amdgpu_device_ip_block_add(adev, &dm_ip_block);
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_discovery_set_sriov_display(adev);
+   else
+   amdgpu_device_ip_block_add(adev, &dm_ip_block);
break;
default:
dev_err(adev->dev,
@@ -1740,7 +1749,10 @@ static int amdgpu_discovery_set_display_ip_blocks(struct 
amdgpu_device *adev)
case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 0, 1):
case IP_VERSION(12, 1, 0):
-   amdgpu_device_ip_block_add(adev, &dm_ip_block);
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_discovery_set_sriov_display(adev);
+   else
+   amdgpu_device_ip_block_add(adev, &dm_ip_block);
break;
default:
dev_err(adev->dev,
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index f6ffd7c96ff9..12ef782eb478 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -2111,6 +2111,8 @@ void vi_set_virt_ops(struct amdgpu_device *adev)
 
 int vi_set_ip_blocks(struct amdgpu_device *adev)

Re: [PATCH 2/2] drm/amdgpu: add dm ip block for dcn 3.1.4

[Alex Deucher]

Series is:
Reviewed-by: Alex Deucher 

On Tue, Jul 19, 2022 at 2:26 PM  wrote:
>
> From: Roman Li 
>
> Adding dm ip block to enable display on dcn 3.1.4.
>
> Signed-off-by: Roman Li 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 0ba56e2ebf09..242d1847c4aa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1716,6 +1716,7 @@ static int 
> amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(3, 0, 1):
> case IP_VERSION(3, 1, 2):
> case IP_VERSION(3, 1, 3):
> +   case IP_VERSION(3, 1, 4):
> case IP_VERSION(3, 1, 5):
> case IP_VERSION(3, 1, 6):
> case IP_VERSION(3, 2, 0):
> --
> 2.17.1
>

[PATCH 1/2] drm/amd/display: Disable dmcu fw loading for dcn314

[Roman.Li]

From: Roman Li 

[Why]
DCN 3.1.4 uses dmub not dmcu. Attempt to identify
dmcu firmware for dcn314 results in dm init error:
"Unsupported ASIC type"

[How]
Add dcn314 to the list of asics that don't require dmcu

Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index dae998e014b0..9fff5aa86567 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1893,6 +1893,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
+   case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
case IP_VERSION(3, 2, 0):
-- 
2.17.1

[PATCH 2/2] drm/amdgpu: add dm ip block for dcn 3.1.4

[Roman.Li]

From: Roman Li 

Adding dm ip block to enable display on dcn 3.1.4.

Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 0ba56e2ebf09..242d1847c4aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1716,6 +1716,7 @@ static int amdgpu_discovery_set_display_ip_blocks(struct 
amdgpu_device *adev)
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
+   case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
case IP_VERSION(3, 2, 0):
-- 
2.17.1

Re: Command "clinfo" causes BUG: kernel NULL pointer dereference, address: 0000000000000008 on driver amdgpu

[Mikhail Gavrilov]

On Tue, Jul 19, 2022 at 4:26 PM Mikhail Gavrilov
 wrote:
> In the kernel log there is no error so it is most likely a user space issue , 
> but I am not
> sure about it.

But I am confused by the message in the kernel log:
[ 1962.000909] amdgpu: HIQ MQD's queue_doorbell_id0 is not 0, Queue
preemption time out
[ 1962.000912] amdgpu: Failed to evict process queues
[ 1962.000918] amdgpu: Failed to quiesce KFD
[ 1966.010395] amdgpu: HIQ MQD's queue_doorbell_id0 is not 0, Queue
preemption time out
[ 1966.010406] amdgpu: Resetting wave fronts (cpsch) on dev b40e7982


-- 
Best Regards,
Mike Gavrilov.

Re: [PATCH] drm/amd/pm: enable gfx ulv and gpo on smu_v13_0_7

[Wang, Yang(Kevin)]

[AMD Official Use Only - General]

Reviewed-by: Yang Wang 

Best Regards,
Kevin

From: amd-gfx  on behalf of Kenneth Feng 

Sent: Tuesday, July 19, 2022 9:17 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Feng, Kenneth 
Subject: [PATCH] drm/amd/pm: enable gfx ulv and gpo on smu_v13_0_7

enable gfx ulv and gpo on smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 6f0548714566..16eea2de8a2d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -251,6 +251,7 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
*smu,
 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
+   *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
 }

 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
@@ -271,6 +272,9 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
*smu,
 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);

+   if (adev->pm.pp_feature & PP_ULV_MASK)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+
 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
--
2.25.1

[PATCH 3/3] drm/amd/kfd: Add sphinx documentation for amdkfd

[David.Francis]

From: David Francis 

Add a new series of documentation entries in the AMDGPU
section describing AMDKFD, the compute driver for AMD
GPUs

Signed-off-by: David Francis 
Reviewed-by: Felix Kuehling 
---
 Documentation/gpu/amdgpu/index.rst  |  1 +
 Documentation/gpu/amdgpu/kfd/index.rst  | 14 +
 Documentation/gpu/amdgpu/kfd/interrupts.rst | 19 
 Documentation/gpu/amdgpu/kfd/memory.rst | 33 +
 Documentation/gpu/amdgpu/kfd/queues.rst | 21 +
 Documentation/gpu/amdgpu/kfd/topology.rst   | 13 
 6 files changed, 101 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/kfd/index.rst
 create mode 100644 Documentation/gpu/amdgpu/kfd/interrupts.rst
 create mode 100644 Documentation/gpu/amdgpu/kfd/memory.rst
 create mode 100644 Documentation/gpu/amdgpu/kfd/queues.rst
 create mode 100644 Documentation/gpu/amdgpu/kfd/topology.rst

diff --git a/Documentation/gpu/amdgpu/index.rst 
b/Documentation/gpu/amdgpu/index.rst
index a24e1cfa7407..e1152c40d78b 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -10,6 +10,7 @@ Next (GCN) architecture.
module-parameters
driver-core
display/index
+   kfd/index
xgmi
ras
thermal
diff --git a/Documentation/gpu/amdgpu/kfd/index.rst 
b/Documentation/gpu/amdgpu/kfd/index.rst
new file mode 100644
index ..c9bfc52c547a
--- /dev/null
+++ b/Documentation/gpu/amdgpu/kfd/index.rst
@@ -0,0 +1,14 @@
+===
+drm/amd/amdkfd - Kernel Fusion Driver (KFD)
+===
+
+KFD is the non-graphics component of AMDGPU. It allows users to run
+their own programs (called compute shaders) on
+AMD GPUs, including discrete GPUs, integrated GPUs, and APUs.
+
+.. toctree::
+
+   topology.rst
+   memory.rst
+   queues.rst
+   interrupts.rst
\ No newline at end of file
diff --git a/Documentation/gpu/amdgpu/kfd/interrupts.rst 
b/Documentation/gpu/amdgpu/kfd/interrupts.rst
new file mode 100644
index ..f59b985ca3f1
--- /dev/null
+++ b/Documentation/gpu/amdgpu/kfd/interrupts.rst
@@ -0,0 +1,19 @@
+==
+Interrupts and Signals
+==
+
+Signals
+---
+
+Signals are locations in memory used for communication between CPUs
+and GPUs. Uses of signals include indicating that a kernel has completed
+and indicating that more scratch memory is rqeuired.
+
+CPUs and GPUs can poll signals to await their signalling. Processes can also
+set up an event, which will trigger a CPU interrupt when a signal arrives.
+
+Interrupts
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+   :doc: KFD_Interrupts
\ No newline at end of file
diff --git a/Documentation/gpu/amdgpu/kfd/memory.rst 
b/Documentation/gpu/amdgpu/kfd/memory.rst
new file mode 100644
index ..2d6b3724d3fb
--- /dev/null
+++ b/Documentation/gpu/amdgpu/kfd/memory.rst
@@ -0,0 +1,33 @@
+=
+Memory Allocation and Mapping
+=
+
+AMD GPUs contain their own page tables used by the GPU's processors; memory 
must
+be mapped on these page tables before the GPU can access it. The GPUs also
+contain VRAM memory of their own, which can be allocated. By mapping memory on
+both the CPU and GPU, processes can load data onto or off of the GPU.
+
+Interface
+=
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+   :doc: Memory_Types
+
+Implementation
+==
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+   :doc: Memory_Implementation
+
+Memory Features
+===
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+   :doc: Memory_Features
+
+
+ioctls
+==
+
+.. kernel-doc:: include/uapi/linux/kfd_ioctl.h
+   :identifiers: kfd_ioctl_alloc_memory_of_gpu_args 
kfd_ioctl_map_memory_to_gpu_args kfd_ioctl_svm_args 
kfd_ioctl_set_xnack_mode_args
\ No newline at end of file
diff --git a/Documentation/gpu/amdgpu/kfd/queues.rst 
b/Documentation/gpu/amdgpu/kfd/queues.rst
new file mode 100644
index ..dbd18029e0c8
--- /dev/null
+++ b/Documentation/gpu/amdgpu/kfd/queues.rst
@@ -0,0 +1,21 @@
+===
+Usermode Queues
+===
+
+Queues (HSA queues and DMA queues) are the means by which users may submit
+programs to be run on the GPU. Once a queue is set up, users can submit 
commands
+to the hardware through it with no driver involvement. This is different from
+the way that graphics shaders are loaded, which involves an ioctl each time.
+
+Interface
+=
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdkfd/kfd_queue.c
+   :doc: Queue_Interface
+
+Implementation
+==
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdkfd/kfd_queue.c
+   :doc: Queue_Implementation
+
diff --git a/Documentation/gpu/amdgpu/kfd/topology.rst 
b/Documentation/gpu/amdgpu/kfd/topology.rst
new file mode 100644
index ..309f2d01fed9
--- /dev/null
+++ b/Documentation/gpu/amdgpu/kf

[PATCH 1/3] drm/amd/kfd: Update documentation to match kernel standards

[David.Francis]

From: David Francis 

The kernel documentation system requires things to be just so
in order to incorporate documentation into the sphinx system.

There were some comments in amdkfd which didn't meet that
standard. Tweak them so they do.

Signed-off-by: David Francis 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 27 +---
 drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c   |  4 +--
 include/uapi/linux/kfd_ioctl.h   | 33 +++-
 3 files changed, 43 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 8aebe408c544..075e4c80dd04 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -37,11 +37,14 @@
 #include 
 #include 
 
-/*
+/**
+ * DOC: Memory_Features
+ *
  * The primary memory I/O features being added for revisions of gfxip
  * beyond 7.0 (Kaveri) are:
  *
  * Access to ATC/IOMMU mapped memory w/ associated extension of VA to 48b
+ * --
  *
  * “Flat” shader memory access – These are new shader vector memory
  * operations that do not reference a T#/V# so a “pointer” is what is
@@ -55,6 +58,7 @@
  *
  *
  * System Unified Address - SUA
+ * 
  *
  * The standard usage for GPU virtual addresses are that they are mapped by
  * a set of page tables we call GPUVM and these page tables are managed by
@@ -72,13 +76,16 @@
  * There are three fundamental address modes of operation for a given VMID
  * (process) on the GPU:
  *
- * HSA64 – 64b pointers and the default address space is ATC
- * HSA32 – 32b pointers and the default address space is ATC
- * GPUVM – 64b pointers and the default address space is GPUVM (driver
- * model mode)
+ * HSA64 – 64b pointers and the default address space is ATC
+ *
+ * HSA32 – 32b pointers and the default address space is ATC
+ *
+ * GPUVM – 64b pointers and the default address space is GPUVM (driver
+ * model mode)
  *
  *
  * HSA64 - ATC/IOMMU 64b
+ * -
  *
  * A 64b pointer in the AMD64/IA64 CPU architecture is not fully utilized
  * by the CPU so an AMD CPU can only access the high area
@@ -99,6 +106,7 @@
  *
  *
  * 64b to 49b Address conversion
+ * -
  *
  * Note that there are still significant portions of unused regions (holes)
  * in the 64b address space even for the GPU.  There are several places in
@@ -147,6 +155,7 @@
  *
  *
  * “Spare” aperture (APE1)
+ * ---
  *
  * We use the GPUVM aperture to differentiate ATC vs. GPUVM, but we also use
  * apertures to set the Mtype field for S_LOAD/FLAT_* ops which is input to the
@@ -160,6 +169,7 @@
  *
  *
  * General Aperture definitions and rules
+ * --
  *
  * An aperture register definition consists of a Base, Limit, Mtype, and
  * usually an ATC bit indicating which translation tables that aperture uses.
@@ -187,6 +197,7 @@
  *
  *
  * HSA32 - ATC/IOMMU 32b
+ * -
  *
  * For HSA32 mode, the pointers are interpreted as 32 bits and use a single GPR
  * instead of two for the S_LOAD and FLAT_* ops. The entire GPUVM space of 40b
@@ -196,6 +207,7 @@
  *
  *
  * GPUVM 64b mode (driver model)
+ * -
  *
  * This mode is related to HSA64 in that the difference really is that
  * the default aperture is GPUVM (ATC==0) and not ATC space.
@@ -204,6 +216,7 @@
  *
  *
  * Device Unified Address - DUA
+ * 
  *
  * Device unified address (DUA) is the name of the feature that maps the
  * Shared(LDS) memory and Private(Scratch) memory into the overall address
@@ -220,6 +233,7 @@
  *
  *
  * HSA64 Apertures for FLAT_* vector ops
+ * -
  *
  * For HSA64 SUA mode, the Shared and Private apertures are always placed
  * in the hole w/ a limited selection of possible locations. The requests
@@ -231,6 +245,7 @@
  *
  *
  * HSA32 Apertures for FLAT_* vector ops
+ * -
  *
  * In HSA32 mode, the Private and Shared apertures can be placed anywhere
  * in the 32b space except at 0 (Private or Shared Base at zero disables
@@ -239,6 +254,7 @@
  *
  *
  * GPUVM Apertures for FLAT_* vector ops
+ * -
  *
  * In GPUVM mode, the Shared/Private apertures are specified identically
  * to HSA64 mode where they are always in the hole at a limited selection
@@ -246,6 +262,7 @@
  *
  *
  * Aperture Definitions for SUA and DUA
+ * 
  *
  * The interpretation of the aperture register definitions for a given
  * VMID is a function of the “SUA Mode” which is one of HSA64, HSA32, or
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index a9466d154395..d532635a 1006

[PATCH 2/3] drm/amd/kfd: Add documentation comments to KFD

[David.Francis]

From: David Francis 

Add six long comments outlining the basic features of the
driver, to aid new developers.

Signed-off-by: David Francis 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  | 74 +++
 drivers/gpu/drm/amd/amdkfd/kfd_device.c   | 25 
 drivers/gpu/drm/amd/amdkfd/kfd_queue.c| 57 +
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 33 ++
 4 files changed, 189 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 6abfe10229a2..ea25a47b62dc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1031,6 +1031,80 @@ static int kfd_ioctl_get_available_memory(struct file 
*filep,
return 0;
 }
 
+/**
+ * DOC: Memory_Types
+ *
+ * There are many different types of memory that KFD can manage, each with
+ * slightly different interfaces
+ *
+ * VRAM and GTT
+ * 
+ *
+ * VRAM and GTT can be allocated with the AMDKFD_IOC_ALLOC_MEMORY_OF_GPU ioctl.
+ * This ioctl returns a handle used to refer to the memory in future kfd 
ioctls,
+ * as well as a mmap_offset used for mapping the allocation on the CPU. VRAM
+ * memory is located on the GPU, while GTT memory is located in host memory.
+ * Once memory is allocated, it must be mapped with the
+ * AMD_KFD_IOC_MAP_MEMORY_TO_GPU ioctl before the GPU can access it.
+ *
+ * Doorbell and MMIO
+ * -
+ *
+ * Each process is assigned two pages of doorbell memory used to signal that
+ * usermode queues have awaiting packets. AMDKFD_IOC_ALLOC_MEMORY_OF_GPU
+ * associates these pages with a virtual address. They must still be mapped if
+ * the GPU is to access them.
+ *
+ * There is one page of MMIO memory per GPU that is accessible to userspace by
+ * the same means.
+ *
+ * userptr
+ * ---
+ *
+ * userptr memory is user-allocated system memory, alloacted with malloc or
+ * similar. As with doorbell and MMIO memory, AMDKFD_IOC_ALLOC_MEMORY_OF_GPU
+ * does not allocate the memory; instead it registers existing memory for
+ * mapping.
+ *
+ * SVM
+ * ---
+ *
+ * SVM is a different memory-allocation API available on GFX9+. Like userptr
+ * memory, SVM maps existing user-managed memory onto the GPU.
+ *
+ * XNACK is an SVM feature that is disabled by default as it has a performance
+ * cost. When XNACK is enabled, SVM memory can perform recoverable page faults,
+ * allowing KFD to allocate memory without reserving physical address space,
+ * performing the physical allocation only on page fault. With XNACK, SVM
+ * uses the Heterogenous Memory Manager (HMM) to migrate pages back and forth
+ * between the device and the host in reponse to memory pressure and page 
faults.
+ *
+ * Scratch
+ * ---
+ *
+ * Scratch memory is VRAM memory on a GPU reserved for holding intermediate
+ * values during a shader's execution. A user (usually ROCr) can allocate
+ * scratch memory by allocating VRAM memory and then using the
+ * AMDKFD_IOC_SET_SCRATCH_BACKING_VA ioctl.
+ */
+
+/**
+ * DOC: Memory_Implementation
+ *
+ * The GPU page tables need to be kept in sync with the CPU page tables; if a
+ * page is moved, swapped, or evicted by linux's normal memory manager, a 
callback
+ * is made into kfd, which must pause hardware access to the memory while the
+ * operation is in progress.
+ *
+ * Compute shaders can cause thrashing if the total memory in use exceeds the
+ * GPU or system's memory limits. Because user command submission is via
+ * usermode queues, with no driver involvement, all memory must be physically
+ * resident at all times (this is different from the graphics approach, which
+ * can swap memory on and off the GPU as needed). KFD prevents overcommitment
+ * of memory by keeping an account of how much memory processes have allocated,
+ * and refusing to allocate beyond a threshold.
+ */
+
 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
struct kfd_process *p, void *data)
 {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f5853835f03a..76d1842c9333 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -37,6 +37,31 @@
 
 #define MQD_SIZE_ALIGNED 768
 
+/**
+ * DOC: Discovery
+ *
+ * There are two phases of initialization and topology discovery in KFD. The
+ * first, module_init occurs when the module is built into the kernel (on boot
+ * or modprobe). The second, device_init, occurs when linux discovers a PCI
+ * device that is an AMD GPU (on boot or hotplug).
+ *
+ * module_init begins when the amdgpu driver is initialized (amdgpu_drv.c),
+ * which calls kfd_init() in kfd_module.c. At this time, the chardev is created
+ * so that ioctls can be submitted, and the topology is queried, creating the
+ * sysfs layout. Some AMD APUs make their topology information
+ * available through a BIOS structu

drm/amd/kfd: AMDKFD Sphinx documentation

[David.Francis]

Make existing documentation comments available through the
sphinx docs, and add new high-level documentation for 
AMDKFD features

Re: [PATCH 1/2] drm/amdgpu: modify mcbp implement for gfx9

[Christian König]

Well what's the background for this?

So far MCBP isn't a validated feature, we just added some debugfs 
interface for testing it.


Regards,
Christian.

Am 19.07.22 um 04:09 schrieb jiadong@amd.com:

From: "Jiadong.Zhu" 

1. Use unmap_queue package to trigger preemption on gfx9
Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
for the resumed ibs.
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 156 ---
  drivers/gpu/drm/amd/amdgpu/soc15d.h  |   2 +
  3 files changed, 138 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 82c178a9033a..ca626f0ad7b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -59,6 +59,7 @@ enum amdgpu_ring_priority_level {
  #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
  #define AMDGPU_FENCE_FLAG_INT   (1 << 1)
  #define AMDGPU_FENCE_FLAG_TC_WB_ONLY(1 << 2)
+#define AMDGPU_FENCE_FLAG_EXEC  (1 << 3)
  
  #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
  
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

index 5332899642dc..e2c614441691 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -751,7 +751,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device 
*adev);
  static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
struct amdgpu_cu_info *cu_info);
  static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
-static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
  static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
  static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
  void *ras_error_status);
@@ -824,9 +824,10 @@ static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring 
*kiq_ring,

PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
  
  	if (action == PREEMPT_QUEUES_NO_UNMAP) {

-   amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
-   amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
-   amdgpu_ring_write(kiq_ring, seq);
+   amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & 
ring->buf_mask));
+   amdgpu_ring_write(kiq_ring, 0);
+   amdgpu_ring_write(kiq_ring, 0);
+
} else {
amdgpu_ring_write(kiq_ring, 0);
amdgpu_ring_write(kiq_ring, 0);
@@ -5446,11 +5447,15 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct 
amdgpu_ring *ring,
  
  	control |= ib->length_dw | (vmid << 24);
  
-	if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {

+   if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & 
AMDGPU_IB_FLAG_PREEMPT)) {
control |= INDIRECT_BUFFER_PRE_ENB(1);
  
+		if (flags & AMDGPU_IB_PREEMPTED)

+   control |= INDIRECT_BUFFER_PRE_RESUME(1);
+
if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
-   gfx_v9_0_ring_emit_de_meta(ring);
+   gfx_v9_0_ring_emit_de_meta(ring,
+(!amdgpu_sriov_vf(ring->adev) && flags & 
AMDGPU_IB_PREEMPTED) ? true : false);
}
  
  	amdgpu_ring_write(ring, header);

@@ -5505,6 +5510,7 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr,
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
+   bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
  
  	/* RELEASE_MEM - flush caches, send int */

amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
@@ -5515,6 +5521,7 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr,
   EOP_TC_WB_ACTION_EN |
   EOP_TC_MD_ACTION_EN)) |
 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+(exec ? EOP_EXEC : 0x0) |
 EVENT_INDEX(5)));
amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel 
? 2 : 0));
  
@@ -5620,33 +5627,132 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)

amdgpu_ring_write(ring, 0);
  }
  
-static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)

+static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
  {
+   struct amdgpu_device *adev = ring->adev;
struct v9_ce_ib_state ce_payload = {0};
-   uint64_t csa_addr;
+   uint64_t offset, ce_

Re: [PATCH] drm/amd/pm: enable gfx ulv and gpo on smu_v13_0_7

[Alex Deucher]

On Tue, Jul 19, 2022 at 9:17 AM Kenneth Feng  wrote:
>
> enable gfx ulv and gpo on smu_v13_0_7
>
> Signed-off-by: Kenneth Feng 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index 6f0548714566..16eea2de8a2d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -251,6 +251,7 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
> *smu,
> if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
> *(uint64_t *)feature_mask |= 
> FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
> *(uint64_t *)feature_mask |= 
> FEATURE_MASK(FEATURE_GFX_IMU_BIT);
> +   *(uint64_t *)feature_mask |= 
> FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
> }
>
> if (adev->pm.pp_feature & PP_GFXOFF_MASK)
> @@ -271,6 +272,9 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
> *smu,
> if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
> *(uint64_t *)feature_mask |= 
> FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
>
> +   if (adev->pm.pp_feature & PP_ULV_MASK)
> +   *(uint64_t *)feature_mask |= 
> FEATURE_MASK(FEATURE_GFX_ULV_BIT);
> +
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
> --
> 2.25.1
>

[PATCH] drm/amd/pm: enable gfx ulv and gpo on smu_v13_0_7

[Kenneth Feng]

enable gfx ulv and gpo on smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 6f0548714566..16eea2de8a2d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -251,6 +251,7 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
*smu,
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
+   *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
}
 
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
@@ -271,6 +272,9 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
*smu,
if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 
+   if (adev->pm.pp_feature & PP_ULV_MASK)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
-- 
2.25.1

Re: [PATCH 10/12] drm/amd/display: Remove parameters from dml30_CalculateWriteBackDISPCLK

[Alex Deucher]

On Tue, Jul 19, 2022 at 6:49 AM Maíra Canal  wrote:
>
> On 7/18/22 16:02, Alex Deucher wrote:
> > On Thu, Jul 14, 2022 at 12:46 PM Maíra Canal  wrote:
> >>
> >> The parameters WritebackPixelFormat and WritebackVRatio are removed as
> >> they are not used on the function dml30_CalculateWriteBackDISPCLK.
> >
> > Maybe this is done for consistency with other dml code for other DCN blocks?
> >
> > Alex
>
> This is reasonable. Anyway, the functions
> dml30_CalculateWriteBackDISPCLK and dml31_CalculateWriteBackDISPCLK are
> identical. May I send a v2 from PATCH 11/12 with the original function
> signature?

Sounds good.  Thanks!

Alex

>
> Best Regards,
> - Maíra Canal
>
> >
> >>
> >> Signed-off-by: Maíra Canal 
> >> ---
> >>  drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c| 2 --
> >>  .../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c  | 6 --
> >>  .../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h  | 2 --
> >>  3 files changed, 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c 
> >> b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
> >> index a8db1306750e..746bb93ade6c 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
> >> @@ -322,10 +322,8 @@ void dcn30_fpu_populate_dml_writeback_from_context(
> >>  * parameters per pipe
> >>  */
> >> writeback_dispclk = 
> >> dml30_CalculateWriteBackDISPCLK(
> >> -   dout_wb.wb_pixel_format,
> >> 
> >> pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
> >> dout_wb.wb_hratio,
> >> -   dout_wb.wb_vratio,
> >> dout_wb.wb_htaps_luma,
> >> dout_wb.wb_vtaps_luma,
> >> dout_wb.wb_src_width,
> >> diff --git 
> >> a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c 
> >> b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
> >> index 876b321b30ca..37049daaab4c 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
> >> @@ -1938,10 +1938,8 @@ static void 
> >> DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
> >> if (v->WritebackEnable[k]) {
> >> v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK,
> >> dml30_CalculateWriteBackDISPCLK(
> >> -   v->WritebackPixelFormat[k],
> >> v->PixelClock[k],
> >> v->WritebackHRatio[k],
> >> -   v->WritebackVRatio[k],
> >> v->WritebackHTaps[k],
> >> v->WritebackVTaps[k],
> >> v->WritebackSourceWidth[k],
> >> @@ -3284,10 +3282,8 @@ static double CalculateTWait(
> >>  }
> >>
> >>  double dml30_CalculateWriteBackDISPCLK(
> >> -   enum source_format_class WritebackPixelFormat,
> >> double PixelClock,
> >> double WritebackHRatio,
> >> -   double WritebackVRatio,
> >> unsigned int WritebackHTaps,
> >> unsigned int WritebackVTaps,
> >> long   WritebackSourceWidth,
> >> @@ -3794,10 +3790,8 @@ void 
> >> dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> >> if (v->WritebackEnable[k] == true) {
> >> v->WritebackRequiredDISPCLK = 
> >> dml_max(v->WritebackRequiredDISPCLK,
> >> dml30_CalculateWriteBackDISPCLK(
> >> -   
> >> v->WritebackPixelFormat[k],
> >> v->PixelClock[k],
> >> 
> >> v->WritebackHRatio[k],
> >> -   
> >> v->WritebackVRatio[k],
> >> 
> >> v->WritebackHTaps[k],
> >> 
> >> v->WritebackVTaps[k],
> >> 
> >> v->WritebackSourceWidth[k],
> >> diff --git 
> >> a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h 
> >> b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h
> >> index daaf0883b84d..12c070434eee 100644
> >> --- a/drivers/gpu/drm/a

[PATCH] drm/amdgpu: Fix comment typo

[Jason Wang]

The double `to' is duplicated in the comment, remove one.

Signed-off-by: Jason Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e3d139708160..b45cd7cbbea8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -80,7 +80,7 @@
  * - 3.24.0 - Add high priority compute support for gfx9
  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
- * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
+ * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
  * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
-- 
2.35.1

Re: [PATCH v9 06/14] mm/gup: migrate device coherent pages when pinning instead of failing

[David Hildenbrand]

On 18.07.22 22:32, Andrew Morton wrote:
> On Mon, 18 Jul 2022 12:56:29 +0200 David Hildenbrand  wrote:
> 
>>> /*
>>>  * Try to move out any movable page before pinning the range.
>>>  */
>>> @@ -1919,7 +1948,8 @@ static long check_and_migrate_movable_pages(unsigned 
>>> long nr_pages,
>>> folio_nr_pages(folio));
>>> }
>>>  
>>> -   if (!list_empty(&movable_page_list) || isolation_error_count)
>>> +   if (!list_empty(&movable_page_list) || isolation_error_count
>>> +   || coherent_pages)
>>
>> The common style is to
>>
>> a) add the || to the end of the previous line
>> b) indent such the we have a nice-to-read alignment
>>
>> if (!list_empty(&movable_page_list) || isolation_error_count ||
>> coherent_pages)
>>
> 
> I missed that.  This series is now in mm-stable so any fix will need to
> be a standalone followup patch, please.
> 
>> Apart from that lgtm.
>>
>> Reviewed-by: David Hildenbrand 
> 
> And your reviewed-by's will be lost.  Stupid git.

I know, I already raised my concerns regarding the new workflow, so I
won't repeat that. I can understand (too some degree) that we don't want
code to change just before the new merge window opens.

But I do wonder if we really don't even want to do subject+description
updates. Sure, the commit IDs will change. Who cares?

Anyhow, it is what it is.

-- 
Thanks,

David / dhildenb

Re: [PATCH v1 0/6] Move all drivers to a common dma-buf locking convention

[Tomasz Figa]

On Fri, Jul 15, 2022 at 9:53 AM Dmitry Osipenko
 wrote:
>
> Hello,
>
> This series moves all drivers to a dynamic dma-buf locking specification.
> From now on all dma-buf importers are made responsible for holding
> dma-buf's reservation lock around all operations performed over dma-bufs.
> This common locking convention allows us to utilize reservation lock more
> broadly around kernel without fearing of potential dead locks.
>
> This patchset passes all i915 selftests. It was also tested using VirtIO,
> Panfrost, Lima and Tegra drivers. I tested cases of display+GPU,
> display+V4L and GPU+V4L dma-buf sharing, which covers majority of kernel
> drivers since rest of the drivers share same or similar code paths.
>
> This is a continuation of [1] where Christian König asked to factor out
> the dma-buf locking changes into separate series.
>
> [1] 
> https://lore.kernel.org/dri-devel/20220526235040.678984-1-dmitry.osipe...@collabora.com/
>
> Dmitry Osipenko (6):
>   dma-buf: Add _unlocked postfix to function names
>   drm/gem: Take reservation lock for vmap/vunmap operations
>   dma-buf: Move all dma-bufs to dynamic locking specification
>   dma-buf: Acquire wait-wound context on attachment
>   media: videobuf2: Stop using internal dma-buf lock
>   dma-buf: Remove internal lock
>
>  drivers/dma-buf/dma-buf.c | 198 +++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c   |   4 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |   4 +-
>  drivers/gpu/drm/armada/armada_gem.c   |  14 +-
>  drivers/gpu/drm/drm_client.c  |   4 +-
>  drivers/gpu/drm/drm_gem.c |  28 +++
>  drivers/gpu/drm/drm_gem_cma_helper.c  |   6 +-
>  drivers/gpu/drm/drm_gem_framebuffer_helper.c  |   6 +-
>  drivers/gpu/drm/drm_gem_shmem_helper.c|   6 +-
>  drivers/gpu/drm/drm_prime.c   |  12 +-
>  drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c   |   6 +-
>  drivers/gpu/drm/exynos/exynos_drm_gem.c   |   2 +-
>  drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c|  20 +-
>  .../gpu/drm/i915/gem/i915_gem_execbuffer.c|   2 +-
>  drivers/gpu/drm/i915/gem/i915_gem_object.h|   6 +-
>  .../drm/i915/gem/selftests/i915_gem_dmabuf.c  |  20 +-
>  drivers/gpu/drm/i915/i915_gem_evict.c |   2 +-
>  drivers/gpu/drm/i915/i915_gem_ww.c|  26 ++-
>  drivers/gpu/drm/i915/i915_gem_ww.h|  15 +-
>  drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c |   8 +-
>  drivers/gpu/drm/qxl/qxl_object.c  |  17 +-
>  drivers/gpu/drm/qxl/qxl_prime.c   |   4 +-
>  drivers/gpu/drm/tegra/gem.c   |  27 +--
>  drivers/infiniband/core/umem_dmabuf.c |  11 +-
>  .../common/videobuf2/videobuf2-dma-contig.c   |  26 +--
>  .../media/common/videobuf2/videobuf2-dma-sg.c |  23 +-
>  .../common/videobuf2/videobuf2-vmalloc.c  |  17 +-

For the videobuf2 changes:

Acked-by: Tomasz Figa 

Best regards,
Tomasz

[PATCH] drm/amdgpu: remove useless condition in amdgpu_job_stop_all_jobs_on_sched()

[Andrey Strachuk]

Local variable 'rq' is initialized by an address
of field of drm_sched_job, so it does not make
sense to compare 'rq' with NULL.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Signed-off-by: Andrey Strachuk 
Fixes: 7c6e68c777f1 ("drm/amdgpu: Avoid HW GPU reset for RAS.")
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 67f66f2f1809..600401f2a98f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -285,10 +285,6 @@ void amdgpu_job_stop_all_jobs_on_sched(struct 
drm_gpu_scheduler *sched)
/* Signal all jobs not yet scheduled */
for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; 
i--) {
struct drm_sched_rq *rq = &sched->sched_rq[i];
-
-   if (!rq)
-   continue;
-
spin_lock(&rq->lock);
list_for_each_entry(s_entity, &rq->entities, list) {
while ((s_job = 
to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue {
-- 
2.25.1

[PATCH] drm/radeon: Fix comment typo

[Jason Wang]

The double `have' is duplicated in line 696, remove one.

Signed-off-by: Jason Wang 
---
 drivers/gpu/drm/radeon/radeon_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index 84843b3b3aef..261fcbae88d7 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -693,7 +693,7 @@ int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
}
 
/* !! DONT REMOVE !!
-* We don't support vm_id yet, to be sure we don't have have broken
+* We don't support vm_id yet, to be sure we don't have broken
 * userspace, reject anyone trying to use non 0 value thus moving
 * forward we can use those fields without breaking existant userspace
 */
-- 
2.35.1

Re: [PATCH] drm/amdgpu: Fix comment typo

[Christian König]

Am 16.07.22 um 06:28 schrieb Jason Wang:

The double `to' is duplicated in the comment, remove one.

Signed-off-by: Jason Wang 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e3d139708160..b45cd7cbbea8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -80,7 +80,7 @@
   * - 3.24.0 - Add high priority compute support for gfx9
   * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
   * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
- * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
+ * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
   * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
   * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
   * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.

Re: [PATCH] drm/radeon: Fix comment typo

[Christian König]

Am 16.07.22 um 05:57 schrieb Jason Wang:

The double `have' is duplicated in line 696, remove one.

Signed-off-by: Jason Wang 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/radeon/radeon_gem.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index 84843b3b3aef..261fcbae88d7 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -693,7 +693,7 @@ int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
}
  
  	/* !! DONT REMOVE !!

-* We don't support vm_id yet, to be sure we don't have have broken
+* We don't support vm_id yet, to be sure we don't have broken
 * userspace, reject anyone trying to use non 0 value thus moving
 * forward we can use those fields without breaking existant userspace
 */

Re: Command "clinfo" causes BUG: kernel NULL pointer dereference, address: 0000000000000008 on driver amdgpu

[Mikhail Gavrilov]

On Tue, Jul 19, 2022 at 1:40 PM Mike Lothian  wrote:
>
> I was told that this patch replaces the patch you mentioned
> https://patchwork.freedesktop.org/series/106078/ and it the one
> that'll hopefully land in Linus's tree
>

Great, I confirm that both patches solve the issue.
As I understand the second patch [1] is more right and it should be
land merged 5.19 soon, right?

And since we are talking about clinfo, there is a question.
No one has encountered the problem that on configurations with two
GPUs, it hangs in a cycle since it completely occupies one processor
core. In my case, one GPU is in the RENOIR processor, and the other is
a discrete AMD Radeon 6800M. In the BIOS there is no ability to turn
off the integrated GPU in the processor, so there is no way to check
this configuration with each GPU separately. In the kernel log there
is no error so it is most likely a user space issue , but I am not
sure about it.

clinfo backtrace is here [2]

[1] https://patchwork.freedesktop.org/series/106078/
[2] https://pastebin.com/wv5iGibi

-- 
Best Regards,
Mike Gavrilov.

Re: [PATCH 10/12] drm/amd/display: Remove parameters from dml30_CalculateWriteBackDISPCLK

[Maíra Canal]

On 7/18/22 16:02, Alex Deucher wrote:
> On Thu, Jul 14, 2022 at 12:46 PM Maíra Canal  wrote:
>>
>> The parameters WritebackPixelFormat and WritebackVRatio are removed as
>> they are not used on the function dml30_CalculateWriteBackDISPCLK.
> 
> Maybe this is done for consistency with other dml code for other DCN blocks?
> 
> Alex

This is reasonable. Anyway, the functions
dml30_CalculateWriteBackDISPCLK and dml31_CalculateWriteBackDISPCLK are
identical. May I send a v2 from PATCH 11/12 with the original function
signature?

Best Regards,
- Maíra Canal

> 
>>
>> Signed-off-by: Maíra Canal 
>> ---
>>  drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c| 2 --
>>  .../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c  | 6 --
>>  .../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h  | 2 --
>>  3 files changed, 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c 
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
>> index a8db1306750e..746bb93ade6c 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
>> @@ -322,10 +322,8 @@ void dcn30_fpu_populate_dml_writeback_from_context(
>>  * parameters per pipe
>>  */
>> writeback_dispclk = 
>> dml30_CalculateWriteBackDISPCLK(
>> -   dout_wb.wb_pixel_format,
>> 
>> pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
>> dout_wb.wb_hratio,
>> -   dout_wb.wb_vratio,
>> dout_wb.wb_htaps_luma,
>> dout_wb.wb_vtaps_luma,
>> dout_wb.wb_src_width,
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c 
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
>> index 876b321b30ca..37049daaab4c 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
>> @@ -1938,10 +1938,8 @@ static void 
>> DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
>> if (v->WritebackEnable[k]) {
>> v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK,
>> dml30_CalculateWriteBackDISPCLK(
>> -   v->WritebackPixelFormat[k],
>> v->PixelClock[k],
>> v->WritebackHRatio[k],
>> -   v->WritebackVRatio[k],
>> v->WritebackHTaps[k],
>> v->WritebackVTaps[k],
>> v->WritebackSourceWidth[k],
>> @@ -3284,10 +3282,8 @@ static double CalculateTWait(
>>  }
>>
>>  double dml30_CalculateWriteBackDISPCLK(
>> -   enum source_format_class WritebackPixelFormat,
>> double PixelClock,
>> double WritebackHRatio,
>> -   double WritebackVRatio,
>> unsigned int WritebackHTaps,
>> unsigned int WritebackVTaps,
>> long   WritebackSourceWidth,
>> @@ -3794,10 +3790,8 @@ void 
>> dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>> if (v->WritebackEnable[k] == true) {
>> v->WritebackRequiredDISPCLK = 
>> dml_max(v->WritebackRequiredDISPCLK,
>> dml30_CalculateWriteBackDISPCLK(
>> -   
>> v->WritebackPixelFormat[k],
>> v->PixelClock[k],
>> 
>> v->WritebackHRatio[k],
>> -   
>> v->WritebackVRatio[k],
>> v->WritebackHTaps[k],
>> v->WritebackVTaps[k],
>> 
>> v->WritebackSourceWidth[k],
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h 
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h
>> index daaf0883b84d..12c070434eee 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h
>> @@ -29,10 +29,8 @@
>>  void dml30_recalculate(struct display_mode_lib *mode_lib);
>>  void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib 
>> *mode_

[PATCH v3 3/3] drm/i915: Use luminance range calculated during edid parsing

[Jouni Högander]

Instead of using fixed 0 - 512 range use luminance range calculated
as a part of edid parsing. As a backup fall back to static 0 - 512.

v3: Clean-ups suggested by Jani Nikula
v2: Use values calculated during edid parsing

Cc: Lyude Paul 
Cc: Mika Kahola 
Cc: Jani Nikula 
Cc: Manasi Navare 
Signed-off-by: Jouni Högander 
---
 .../gpu/drm/i915/display/intel_dp_aux_backlight.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index c92d5bb2326a..83af95bce98d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -278,6 +278,8 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector 
*connector, enum pipe pi
 {
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_panel *panel = &connector->panel;
+   struct drm_luminance_range_info *luminance_range =
+   &connector->base.display_info.luminance_range;
int ret;
 
if (panel->backlight.edp.intel.sdr_uses_aux) {
@@ -293,8 +295,17 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector 
*connector, enum pipe pi
}
}
 
-   panel->backlight.max = 512;
-   panel->backlight.min = 0;
+   if (luminance_range->max_luminance) {
+   panel->backlight.max = luminance_range->max_luminance;
+   panel->backlight.min = luminance_range->min_luminance;
+   } else {
+   panel->backlight.max = 512;
+   panel->backlight.min = 0;
+   }
+
+   drm_dbg_kms(&i915->drm, "Using backlight range %d..%d\n", 
panel->backlight.min,
+   panel->backlight.max);
+
panel->backlight.level = intel_dp_aux_hdr_get_backlight(connector, 
pipe);
panel->backlight.enabled = panel->backlight.level != 0;
 
-- 
2.25.1

[PATCH v3 2/3] drm/amdgpu_dm: Rely on split out luminance calculation function

[Jouni Högander]

Luminance range calculation was split out into drm_edid.c and is now
part of edid parsing. Rely on values calculated during edid parsing and
use these for caps->aux_max_input_signal and caps->aux_min_input_signal.

v2: Use values calculated during edid parsing

Cc: Roman Li 
Cc: Rodrigo Siqueira 
Cc: Harry Wentland 
Cc: Lyude Paul 
Cc: Mika Kahola 
Cc: Jani Nikula 
Cc: Manasi Navare 
Signed-off-by: Jouni Högander 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 +++
 1 file changed, 4 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3e83fed540e8..eb7abdeb8653 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2903,15 +2903,12 @@ static struct drm_mode_config_helper_funcs 
amdgpu_dm_mode_config_helperfuncs = {
 
 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
 {
-   u32 max_avg, min_cll, max, min, q, r;
struct amdgpu_dm_backlight_caps *caps;
struct amdgpu_display_manager *dm;
struct drm_connector *conn_base;
struct amdgpu_device *adev;
struct dc_link *link = NULL;
-   static const u8 pre_computed_values[] = {
-   50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
-   71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
+   struct drm_luminance_range_info *luminance_range;
int i;
 
if (!aconnector || !aconnector->dc_link)
@@ -2933,8 +2930,6 @@ static void update_connector_ext_caps(struct 
amdgpu_dm_connector *aconnector)
caps = &dm->backlight_caps[i];
caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
caps->aux_support = false;
-   max_avg = conn_base->hdr_sink_metadata.hdmi_type1.max_fall;
-   min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
 
if (caps->ext_caps->bits.oled == 1 /*||
caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
@@ -2946,31 +2941,9 @@ static void update_connector_ext_caps(struct 
amdgpu_dm_connector *aconnector)
else if (amdgpu_backlight == 1)
caps->aux_support = true;
 
-   /* From the specification (CTA-861-G), for calculating the maximum
-* luminance we need to use:
-*  Luminance = 50*2**(CV/32)
-* Where CV is a one-byte value.
-* For calculating this expression we may need float point precision;
-* to avoid this complexity level, we take advantage that CV is divided
-* by a constant. From the Euclids division algorithm, we know that CV
-* can be written as: CV = 32*q + r. Next, we replace CV in the
-* Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
-* need to pre-compute the value of r/32. For pre-computing the values
-* We just used the following Ruby line:
-*  (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
-* The results of the above expressions can be verified at
-* pre_computed_values.
-*/
-   q = max_avg >> 5;
-   r = max_avg % 32;
-   max = (1 << q) * pre_computed_values[r];
-
-   // min luminance: maxLum * (CV/255)^2 / 100
-   q = DIV_ROUND_CLOSEST(min_cll, 255);
-   min = max * DIV_ROUND_CLOSEST((q * q), 100);
-
-   caps->aux_max_input_signal = max;
-   caps->aux_min_input_signal = min;
+   luminance_range = &conn_base->display_info.luminance_range;
+   caps->aux_min_input_signal = luminance_range->min_luminance;
+   caps->aux_max_input_signal = luminance_range->max_luminance;
 }
 
 void amdgpu_dm_update_connector_after_detect(
-- 
2.25.1

[PATCH v3 1/3] drm: New function to get luminance range based on static hdr metadata

[Jouni Högander]

Split luminance min/max calculation using static hdr metadata from
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:update_connector_ext_caps
into drm/drm_edid.c and use it during edid parsing. Calculated range is
stored into connector->display_info->luminance_range.

Add new data structure (drm_luminance_range_inf) to store luminance range
calculated using data from EDID's static hdr metadata block. Add this new
struct as a part of drm_display_info struct.

v3: Squashed adding drm_luminance_range_info patch here
v2: Calculate range during edid parsing

Cc: Roman Li 
Cc: Rodrigo Siqueira 
Cc: Harry Wentland 
Cc: Lyude Paul 
Cc: Mika Kahola 
Cc: Jani Nikula 
Cc: Manasi Navare 
Signed-off-by: Jouni Högander 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c  | 52 -
 include/drm/drm_connector.h | 21 +++
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index bbc25e3b7220..90a5e26eafa8 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5165,6 +5165,51 @@ static void fixup_detailed_cea_mode_clock(struct 
drm_display_mode *mode)
mode->clock = clock;
 }
 
+static void drm_calculate_luminance_range(struct drm_connector *connector)
+{
+   struct hdr_static_metadata *hdr_metadata = 
&connector->hdr_sink_metadata.hdmi_type1;
+   struct drm_luminance_range_info *luminance_range =
+   &connector->display_info.luminance_range;
+   static const u8 pre_computed_values[] = {
+   50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
+   71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
+   };
+   u32 max_avg, min_cll, max, min, q, r;
+
+   if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
+   return;
+
+   max_avg = hdr_metadata->max_fall;
+   min_cll = hdr_metadata->min_cll;
+
+   /*
+* From the specification (CTA-861-G), for calculating the maximum
+* luminance we need to use:
+*  Luminance = 50*2**(CV/32)
+* Where CV is a one-byte value.
+* For calculating this expression we may need float point precision;
+* to avoid this complexity level, we take advantage that CV is divided
+* by a constant. From the Euclids division algorithm, we know that CV
+* can be written as: CV = 32*q + r. Next, we replace CV in the
+* Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
+* need to pre-compute the value of r/32. For pre-computing the values
+* We just used the following Ruby line:
+*  (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
+* The results of the above expressions can be verified at
+* pre_computed_values.
+*/
+   q = max_avg >> 5;
+   r = max_avg % 32;
+   max = (1 << q) * pre_computed_values[r];
+
+   /* min luminance: maxLum * (CV/255)^2 / 100 */
+   q = DIV_ROUND_CLOSEST(min_cll, 255);
+   min = max * DIV_ROUND_CLOSEST((q * q), 100);
+
+   luminance_range->min_luminance = min;
+   luminance_range->max_luminance = max;
+}
+
 static uint8_t eotf_supported(const u8 *edid_ext)
 {
return edid_ext[2] &
@@ -5196,8 +5241,12 @@ drm_parse_hdr_metadata_block(struct drm_connector 
*connector, const u8 *db)
connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
if (len >= 5)
connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
-   if (len >= 6)
+   if (len >= 6) {
connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
+
+   /* Calculate only when all values are available */
+   drm_calculate_luminance_range(connector);
+   }
 }
 
 static void
@@ -6101,6 +6150,7 @@ static void drm_reset_display_info(struct drm_connector 
*connector)
 
info->non_desktop = 0;
memset(&info->monitor_range, 0, sizeof(info->monitor_range));
+   memset(&info->luminance_range, 0, sizeof(info->luminance_range));
 
info->mso_stream_count = 0;
info->mso_pixel_overlap = 0;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 2c6fa746efac..248206bbd975 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -323,6 +323,22 @@ struct drm_monitor_range_info {
u8 max_vfreq;
 };
 
+/**
+ * struct drm_luminance_range_info - Panel's luminance range for
+ * &drm_display_info. Calculated using data in EDID
+ *
+ * This struct is used to store a luminance range supported by panel
+ * as calculated using data from EDID's static hdr metadata.
+ *
+ * @min_luminance: This is the min supported luminance value
+ *
+ * @max_luminance: This is the max supported luminance value
+ */
+struct drm_luminance_range_info {
+   u32 min_luminance;
+   u32 max_luminance;
+};
+
 /**
  * enum drm_privacy_screen_status - privacy screen

[PATCH v3 0/3] HDR aux backlight range calculation

[Jouni Högander]

This patch set splits out static hdr metadata backlight range parsing
from gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c into gpu/drm/drm-edid.c
as a new function. This new function is then used during edid parsing
when HDR static metadata block parsing.

Calculated values are stored in a new struct drm_luminance_range
introduced into display_info. Amdgpu_dm.c and intel_dp_aux_backlight.c
are using this new data.

v3: Some clean-ups suggested by Jani Nikula
v2: Calculate the range during edid parsing and store into display_info

Cc: Roman Li 
Cc: Maarten Lankhorst 
Cc: Rodrigo Siqueira 
Cc: Harry Wentland 
Cc: Lyude Paul 
Cc: Mika Kahola 
Cc: Jani Nikula 
Cc: Manasi Navare 

Jouni Högander (3):
  drm: New function to get luminance range based on static hdr metadata
  drm/amdgpu_dm: Rely on split out luminance calculation function
  drm/i915: Use luminance range calculated during edid parsing

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 ++---
 drivers/gpu/drm/drm_edid.c| 52 ++-
 .../drm/i915/display/intel_dp_aux_backlight.c | 15 +-
 include/drm/drm_connector.h   | 21 
 4 files changed, 89 insertions(+), 34 deletions(-)

-- 
2.25.1

[PATCH 4/4] drm/amd/pm: revise the driver reloading fix for SMU 13.0.0 and 13.0.7

[Evan Quan]

The current approach breaks S3/S4 as asic reset is needed for them.
And putting SMU out of service(via SMU_MSG_PrepareMp1ForUnload) will make
that(asic reset) failed. Considering with current designs, there is
actually also asic reset involved on driver reloading. That can make
asic back to a clean state. So, the SMU_MSG_PrepareMp1ForUnload operation
will be not so necessary. Thus we will just drop the SMU_MSG_PrepareMp1ForUnload
operation. We may revise the whole driver reloading sequences when there
is a better design.

Fixes: 826126d8f805 ("drm/amd/pm: fix driver reload SMC firmware fail issue for 
smu13")

Signed-off-by: Evan Quan 
Reviewed-by: Hawking Zhang 
Acked-by: Alex Deucher 
Change-Id: I4e93f08f930ebeb1ed134307e62b4c53a9885066
--
v1->v2:
  - limit the impacts to legacy ASICs(Hawking)
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index fd79b213fab4..6d9b3c6af164 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1415,13 +1415,6 @@ static int smu_disable_dpms(struct smu_context *smu)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 7):
-   if (!(adev->in_runpm || amdgpu_in_reset(adev))) {
-   ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
-   if (ret) {
-   dev_err(adev->dev, "Fail set mp1 state to 
UNLOAD!\n");
-   return ret;
-   }
-   }
return 0;
default:
break;
-- 
2.29.0

[PATCH 2/4] drm/amd/pm: update SMU13.0.0 driver_if header

[Evan Quan]

To fit the latest 78.49.0 PMFW. Also, bump the version
to 0x2B.

Signed-off-by: Evan Quan 
Reviewed-by: Hawking Zhang 
Acked-by: Alex Deucher 
Change-Id: Icbf79cca25dbfd2850425e9e4afbb77cf1ff28db
---
 .../drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h| 4 ++--
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
index 5becfc1bb2ec..2b672d102c96 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
@@ -973,8 +973,8 @@ typedef struct {
   uint16_tVmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT];   //In mV(Q2) 
End-of-life Vset to be used at hot.
   uint16_tVmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT];  //In mV(Q2) 
End-of-life Vset to be used at cold.
   uint16_tVmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT];  //In mV(Q2) 
Worst-case aging margin
-  uint16_tVmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT];   //In mV(Q2) 
Platform offset apply to T0 Hot
-  uint16_tVmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT];  //In mV(Q2) 
Platform offset apply to T0 Cold
+  uint16_tSpare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT];   //In 
mV(Q2) Platform offset apply to T0 Hot
+  uint16_tSpare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT];  //In 
mV(Q2) Platform offset apply to T0 Cold
 
   //This is a fixed/minimum VMIN aging degradation offset which is applied at 
T0. This reflects the minimum amount of aging already accounted for.
   uint16_tVcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT];
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 038a8956de5b..50daf1353e78 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -30,7 +30,7 @@
 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
-#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2A
+#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2B
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2A
 
 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
-- 
2.29.0

[PATCH 3/4] drm/amd/pm: correct smu 13.0.0/7 mp1 state setup

[Evan Quan]

Only PP_MP1_STATE_UNLOAD is supported for now. For other mp1 state, we
should just ignore it. Otherwise, there will be errors coming out.

Signed-off-by: Evan Quan 
Reviewed-by: Hawking Zhang 
Acked-by: Alex Deucher 
Change-Id: I15427d6daf14d5c82a6e7f9d32fdea60a80fd0ec
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 19 ++-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 19 ++-
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index fe7528c83843..1e0109c10e06 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1608,6 +1608,23 @@ static bool smu_v13_0_0_is_mode1_reset_supported(struct 
smu_context *smu)
return true;
 }
 
+static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
+enum pp_mp1_state mp1_state)
+{
+   int ret;
+
+   switch (mp1_state) {
+   case PP_MP1_STATE_UNLOAD:
+   ret = smu_cmn_set_mp1_state(smu, mp1_state);
+   break;
+   default:
+   /* Ignore others */
+   ret = 0;
+   }
+
+   return ret;
+}
+
 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -1672,7 +1689,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = 
{
.baco_exit = smu_v13_0_baco_exit,
.mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
.mode1_reset = smu_v13_0_mode1_reset,
-   .set_mp1_state = smu_cmn_set_mp1_state,
+   .set_mp1_state = smu_v13_0_0_set_mp1_state,
 };
 
 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 3358be877b56..ea99c38d4e55 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1554,6 +1554,23 @@ static int smu_v13_0_7_set_power_profile_mode(struct 
smu_context *smu, long *inp
return ret;
 }
 
+static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
+enum pp_mp1_state mp1_state)
+{
+   int ret;
+
+   switch (mp1_state) {
+   case PP_MP1_STATE_UNLOAD:
+   ret = smu_cmn_set_mp1_state(smu, mp1_state);
+   break;
+   default:
+   /* Ignore others */
+   ret = 0;
+   }
+
+   return ret;
+}
+
 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -1611,7 +1628,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.baco_set_state = smu_v13_0_baco_set_state,
.baco_enter = smu_v13_0_baco_enter,
.baco_exit = smu_v13_0_baco_exit,
-   .set_mp1_state = smu_cmn_set_mp1_state,
+   .set_mp1_state = smu_v13_0_7_set_mp1_state,
 };
 
 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
-- 
2.29.0

[PATCH 1/4] drm/amd/pm: enable GPO feature support for SMU13.0.0

[Evan Quan]

The feature is ready with latest firmwares.

Signed-off-by: Evan Quan 
Reviewed-by: Hawking Zhang 
Acked-by: Alex Deucher 
Change-Id: I581a7aae2618134a9d196cd383cdabf3516efec0
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index ce2fa04e3926..fe7528c83843 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -310,6 +310,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context 
*smu,
 
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
 
+   *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
+
return 0;
 }
 
-- 
2.29.0

Re: Command "clinfo" causes BUG: kernel NULL pointer dereference, address: 0000000000000008 on driver amdgpu

[Mike Lothian]

I was told that this patch replaces the patch you mentioned
https://patchwork.freedesktop.org/series/106078/ and it the one
that'll hopefully land in Linus's tree

On Tue, 19 Jul 2022 at 03:33, Chen, Guchun  wrote:
>
> Patch https://patchwork.freedesktop.org/series/106024/ should fix this.
>
> Regards,
> Guchun
>
> -Original Message-
> From: amd-gfx  On Behalf Of Mikhail 
> Gavrilov
> Sent: Tuesday, July 19, 2022 7:50 AM
> To: amd-gfx list ; Linux List Kernel Mailing 
> ; Christian König 
> 
> Subject: Command "clinfo" causes BUG: kernel NULL pointer dereference, 
> address: 0008 on driver amdgpu
>
> Hi guys I continue testing 5.19 rc7 and found the bug.
> Command "clinfo" causes BUG: kernel NULL pointer dereference, address:
> 0008 on driver amdgpu.
>
> Here is trace:
> [ 1320.203332] BUG: kernel NULL pointer dereference, address: 
> 0008 [ 1320.203338] #PF: supervisor read access in kernel mode [ 
> 1320.203340] #PF: error_code(0x) - not-present page [ 1320.203341] PGD 0 
> P4D 0 [ 1320.203344] Oops:  [#1] PREEMPT SMP NOPTI [ 1320.203346] CPU: 5 
> PID: 1226 Comm: kworker/5:2 Tainted: G W L
>  --- 5.19.0-0.rc7.53.fc37.x86_64+debug #1 [ 1320.203348] Hardware 
> name: System manufacturer System Product Name/ROG STRIX X570-I GAMING, BIOS 
> 4403 04/27/2022 [ 1320.203350] Workqueue: events delayed_fput [ 1320.203354] 
> RIP: 0010:dma_resv_add_fence+0x5a/0x2d0
> [ 1320.203358] Code: 85 c0 0f 84 43 02 00 00 8d 50 01 09 c2 0f 88 47
> 02 00 00 8b 15 73 10 99 01 49 8d 45 70 48 89 44 24 10 85 d2 0f 85 05
> 02 00 00 <49> 8b 44 24 08 48 3d 80 93 53 97 0f 84 06 01 00 00 48 3d 20
> 93 53
> [ 1320.203360] RSP: 0018:af4cc1adfc68 EFLAGS: 00010246 [ 1320.203362] 
> RAX: 976660408208 RBX: 975f545f2000 RCX:  [ 
> 1320.203363] RDX:  RSI:  RDI: 
> 976660408198 [ 1320.203364] RBP: 976806f6e800 R08:  
> R09:  [ 1320.203366] R10:  R11: 
> 0001 R12:  [ 1320.203367] R13: 976660408198 
> R14: 975f545f2000 R15: 976660408198 [ 1320.203368] FS: 
> () GS:976de120()
> knlGS:
> [ 1320.203370] CS: 0010 DS:  ES:  CR0: 80050033 [ 
> 1320.203371] CR2: 0008 CR3: 0007fb31c000 CR4: 
> 00350ee0 [ 1320.203372] Call Trace:
> [ 1320.203374] 
> [ 1320.203378] amdgpu_amdkfd_gpuvm_destroy_cb+0x5d/0x1e0 [amdgpu] [ 
> 1320.203516] amdgpu_vm_fini+0x2f/0x4e0 [amdgpu] [ 1320.203625] ? 
> mutex_destroy+0x21/0x50 [ 1320.203629] 
> amdgpu_driver_postclose_kms+0x1da/0x2b0 [amdgpu] [ 1320.203734] 
> drm_file_free.part.0+0x20d/0x260 [ 1320.203738] drm_release+0x6a/0x120 [ 
> 1320.203741] __fput+0xab/0x270 [ 1320.203743] delayed_fput+0x1f/0x30 [ 
> 1320.203745] process_one_work+0x2a0/0x600 [ 1320.203749] 
> worker_thread+0x4f/0x3a0 [ 1320.203751] ? process_one_work+0x600/0x600 [ 
> 1320.203753] kthread+0xf5/0x120 [ 1320.203755] ? 
> kthread_complete_and_exit+0x20/0x20
> [ 1320.203758] ret_from_fork+0x22/0x30
> [ 1320.203764] 
>
> Full kernel log is here:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpastebin.com%2FEeKh2LEr&data=05%7C01%7Cguchun.chen%40amd.com%7C06749e19d65b418748dc08da6918435f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637937850184140997%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=x1%2FR7m9Vy2XwkXKXsmEOeaAyv44ZKNsU4caZJOOSIvY%3D&reserved=0
>
> And one hour later after a lot of messages "BUG: workqueue lockup" GPU 
> completely hung.
>
> I will be glad to test patches that fix this bug.
>
> --
> Best Regards,
> Mike Gavrilov.

Re: [PATCH] drm/amdgpu: Remove one duplicated ef removal

[Mike Lothian]

With this patch applied on Linus's tree 5.18-rc7 I get the following warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1367:20: warning:
unused variable 'pd' [-Wunused-variable]
   struct amdgpu_bo *pd = vm->root.bo;
 ^
1 warning generated.

It does fix the nullpointer though :D


On Fri, 8 Jul 2022 at 02:55, xinhui pan  wrote:
>
> That has been done in BO release notify.
>
> Signed-off-by: xinhui pan 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 -
>  1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 0f9811d02f61..49536fa8d269 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1583,11 +1583,6 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct 
> amdgpu_device *adev,
> if (!process_info)
> return;
>
> -   /* Release eviction fence from PD */
> -   amdgpu_bo_reserve(pd, false);
> -   amdgpu_bo_fence(pd, NULL, false);
> -   amdgpu_bo_unreserve(pd);
> -
> /* Update process info */
> mutex_lock(&process_info->lock);
> process_info->n_vms--;
> --
> 2.34.1
>