Fwd: [drm-tip:drm-tip 4/8] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1565:27: error: 'drm_primary_helper_destroy' undeclared here (not in a function); did you mean 'drm_plane_h
Forwarding this to amd-gfx Weitergeleitete Nachricht Betreff: [drm-tip:drm-tip 4/8] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1565:27: error: 'drm_primary_helper_destroy' undeclared here (not in a function); did you mean 'drm_plane_helper_destroy'? Datum: Thu, 28 Jul 2022 14:10:58 +0800 Von: kernel test robot An: Thomas Zimmermann Kopie (CC): intel-...@lists.freedesktop.org, kbuild-...@lists.01.org, dri-de...@lists.freedesktop.org Hi Thomas, First bad commit (maybe != root cause): tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip head: df865a97749db8fbb9ec3491f34bf40771ce1f7b commit: 9c7f5cf088789957dcfb460cca1ab0fb578f2376 [4/8] Merge remote-tracking branch 'drm-misc/drm-misc-next' into drm-tip config: alpha-randconfig-r003-20220728 (https://download.01.org/0day-ci/archive/20220728/202207281420.mnf0xrnj-...@intel.com/config) compiler: alpha-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip git fetch --no-tags drm-tip drm-tip git checkout 9c7f5cf088789957dcfb460cca1ab0fb578f2376 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=alpha SHELL=/bin/bash drivers/gpu/drm/ If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot All errors (new ones prefixed by >>): drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:83:31: warning: no previous prototype for 'amd_get_format_info' [-Wmissing-prototypes] 83 | const struct drm_format_info *amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:88:6: warning: no previous prototype for 'fill_blending_from_plane_state' [-Wmissing-prototypes] 88 | void fill_blending_from_plane_state(const struct drm_plane_state *plane_state, | ^~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:152:6: warning: no previous prototype for 'modifier_has_dcc' [-Wmissing-prototypes] 152 | bool modifier_has_dcc(uint64_t modifier) | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:157:10: warning: no previous prototype for 'modifier_gfx9_swizzle_mode' [-Wmissing-prototypes] 157 | unsigned modifier_gfx9_swizzle_mode(uint64_t modifier) | ^~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:752:5: warning: no previous prototype for 'fill_plane_buffer_attributes' [-Wmissing-prototypes] 752 | int fill_plane_buffer_attributes(struct amdgpu_device *adev, | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:992:5: warning: no previous prototype for 'dm_plane_helper_check_state' [-Wmissing-prototypes] 992 | int dm_plane_helper_check_state(struct drm_plane_state *state, | ^~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1046:5: warning: no previous prototype for 'fill_dc_scaling_info' [-Wmissing-prototypes] 1046 | int fill_dc_scaling_info(struct amdgpu_device *adev, | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1222:6: warning: no previous prototype for 'handle_cursor_update' [-Wmissing-prototypes] 1222 | void handle_cursor_update(struct drm_plane *plane, | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1565:27: error: 'drm_primary_helper_destroy' undeclared here (not in a function); did you mean 'drm_plane_helper_destroy'? 1565 | .destroy= drm_primary_helper_destroy, | ^~ | drm_plane_helper_destroy drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1576:5: warning: no previous prototype for 'amdgpu_dm_plane_init' [-Wmissing-prototypes] 1576 | int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, | ^~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:32, from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_trace.h:41, from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:36: drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:137:22: warning: 'SYNAPTICS_DEVICE_ID' defined but not used [-Wunused-const-variable=] 137 | static const uint8_t SYNAPTI
RE: [PATCH v2] drm/amd/amdgpu: add memory training support for PSP_V13
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chengming Gui
Sent: Thursday, July 28, 2022 13:29
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking
Cc: Gui, Jack
Subject: [PATCH v2] drm/amd/amdgpu: add memory training support for PSP_V13
Add PSP_V13 memory training support funcs.
v2: replace DRM_{DEBUG/ERROR} with dev_{dbg/err}. (Hawking)
Signed-off-by: Chengming Gui
Reviewed-by: Hawking Zhang
Change-Id: Ic59f31c95897cc983e1d73335d4b44e159373369
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 159 +
1 file changed, 159 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 30386d34d0d6..c9821f89eeed 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -20,6 +20,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
+#include
+#include
#include "amdgpu.h"
#include "amdgpu_psp.h"
#include "amdgpu_ucode.h"
@@ -58,6 +60,9 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 #define
C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
+/* memory training timeout define */
+#define MEM_TRAIN_SEND_MSG_TIMEOUT_US 300
+
static int psp_v13_0_init_microcode(struct psp_context *psp) {
struct amdgpu_device *adev = psp->adev; @@ -419,6 +424,159 @@ static
void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); }
+static int psp_v13_0_memory_training_send_msg(struct psp_context *psp,
+int msg) {
+ int ret;
+ int i;
+ uint32_t data_32;
+ int max_wait;
+ struct amdgpu_device *adev = psp->adev;
+
+ data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
+
+ max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
+ for (i = 0; i < max_wait; i++) {
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
regMP0_SMN_C2PMSG_35),
+ 0x8000, 0x8000, false);
+ if (ret == 0)
+ break;
+ }
+ if (i < max_wait)
+ ret = 0;
+ else
+ ret = -ETIME;
+
+ dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
+ (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
+ (ret == 0) ? "succeed" : "failed",
+ i, adev->usec_timeout/1000);
+ return ret;
+}
+
+
+static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t
+ops) {
+ struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
+ uint32_t *pcache = (uint32_t *)ctx->sys_cache;
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t p2c_header[4];
+ uint32_t sz;
+ void *buf;
+ int ret, idx;
+
+ if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
+ dev_dbg(adev->dev, "Memory training is not supported.\n");
+ return 0;
+ } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
+ dev_err(adev->dev, "Memory training initialization failure.\n");
+ return -EINVAL;
+ }
+
+ if (psp_v13_0_is_sos_alive(psp)) {
+ dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
+ return 0;
+ }
+
+ amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header,
sizeof(p2c_header), false);
+ dev_dbg(adev->dev,"sys_cache[%08x,%08x,%08x,%08x]
p2c_header[%08x,%08x,%08x,%08x]\n",
+ pcache[0], pcache[1], pcache[2], pcache[3],
+ p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
+
+ if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
+ dev_dbg(adev->dev, "Short training depends on restore.\n");
+ ops |= PSP_MEM_TRAIN_RESTORE;
+ }
+
+ if ((ops & PSP_MEM_TRAIN_RESTORE) &&
+ pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
+ dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on
save.\n");
+ ops |= PSP_MEM_TRAIN_SAVE;
+ }
+
+ if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
+ !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
+ pcache[3] == p2c_header[3])) {
+ dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need
save training data to sys_cache.\n");
+ ops |= PSP_MEM_TRAIN_SAVE;
+ }
+
+ if ((ops & PSP_MEM_TRAIN_SAVE) &&
+ p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
+ dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on
long training.\n");
+ ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
+ }
+
+ if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
+ ops &= ~PSP_MEM_TRAIN_SEND_
Re: [PATCH] drm/amdkfd: use time_is_before_jiffies(a + b) to replace "jiffies - a > b"
在 2022年07月28日 00:04, Felix Kuehling 写道:
This patch introduces a build warning for me:
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o
In file included from /home/fkuehlin/compute/kernel/include/linux/spinlock.h:54,
from /home/fkuehlin/compute/kernel/include/linux/mmzone.h:8,
from /home/fkuehlin/compute/kernel/include/linux/gfp.h:6,
from /home/fkuehlin/compute/kernel/include/linux/slab.h:15,
from
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.c:44:
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.c:
In function ?interrupt_wq?:
/home/fkuehlin/compute/kernel/include/linux/typecheck.h:12:18: warning:
comparison of distinct pointer types lacks a cast
12 | (void)(&__dummy == &__dummy2); \
| ^~
/home/fkuehlin/compute/kernel/include/linux/jiffies.h:106:3: note: in expansion
of macro ?typecheck?
106 | typecheck(unsigned long, b) && \
| ^
/home/fkuehlin/compute/kernel/include/linux/jiffies.h:154:35: note: in
expansion of macro ?time_after?
154 | #define time_is_before_jiffies(a) time_after(jiffies, a)
| ^~
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.c:159:7:
note: in expansion of macro ?time_is_before_jiffies?
159 | if (time_is_before_jiffies(start_jiffies + HZ)) {
| ^~
I think you need to change the the definition of start_jiffies to be
unsigned long. Do you want to submit a v2 of your patch?
Yes, I will submit v2 patch later.
That said, I think the existing code was fine, though the type-mismatch
highlighted by your patch is a bit iffy.
And if the timer wrap changes in the future you won't have to alter your driver
code. So I think it's better.
Regards,
Felix
Am 2022-07-26 um 22:59 schrieb Yu Zhe:
time_is_before_jiffies deals with timer wrapping correctly.
Signed-off-by: Yu Zhe
---
drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index a9466d154395..6397926e059c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
@@ -156,7 +156,7 @@ static void interrupt_wq(struct work_struct *work)
while (dequeue_ih_ring_entry(dev, ih_ring_entry)) {
dev->device_info.event_interrupt_class->interrupt_wq(dev,
ih_ring_entry);
-if (jiffies - start_jiffies > HZ) {
+if (time_is_before_jiffies(start_jiffies + HZ)) {
/* If we spent more than a second processing signals,
* reschedule the worker to avoid soft-lockup warnings
*/
[PATCH v2] drm/amdkfd: use time_is_before_jiffies(a + b) to replace "jiffies - a > b"
time_is_before_jiffies deals with timer wrapping correctly.
Signed-off-by: Yu Zhe
---
drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index a9466d154395..34772fe74296 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
@@ -146,7 +146,7 @@ static void interrupt_wq(struct work_struct *work)
struct kfd_dev *dev = container_of(work, struct kfd_dev,
interrupt_work);
uint32_t ih_ring_entry[KFD_MAX_RING_ENTRY_SIZE];
- long start_jiffies = jiffies;
+ unsigned long start_jiffies = jiffies;
if (dev->device_info.ih_ring_entry_size > sizeof(ih_ring_entry)) {
dev_err_once(dev->adev->dev, "Ring entry too small\n");
@@ -156,7 +156,7 @@ static void interrupt_wq(struct work_struct *work)
while (dequeue_ih_ring_entry(dev, ih_ring_entry)) {
dev->device_info.event_interrupt_class->interrupt_wq(dev,
ih_ring_entry);
- if (jiffies - start_jiffies > HZ) {
+ if (time_is_before_jiffies(start_jiffies + HZ)) {
/* If we spent more than a second processing signals,
* reschedule the worker to avoid soft-lockup warnings
*/
--
2.11.0
Re: [PATCH] dma-buf: Fix one use-after-free of fence
Did this ever land? I don't see it in drm-misc.
Alex
On Thu, Jul 7, 2022 at 4:05 AM Christian König wrote:
>
> Am 07.07.22 um 10:02 schrieb xinhui pan:
> > Need get the new fence when we replace the old one.
> >
> > Fixes: 047a1b877ed48 ("dma-buf & drm/amdgpu: remove dma_resv workaround")
> > Signed-off-by: xinhui pan
>
> Good catch, Reviewed-by: Christian König
>
> Going to push that in a minute.
>
> Christian.
>
> > ---
> > drivers/dma-buf/dma-resv.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
> > index 0cce6e4ec946..205acb2c744d 100644
> > --- a/drivers/dma-buf/dma-resv.c
> > +++ b/drivers/dma-buf/dma-resv.c
> > @@ -343,7 +343,7 @@ void dma_resv_replace_fences(struct dma_resv *obj,
> > uint64_t context,
> > if (old->context != context)
> > continue;
> >
> > - dma_resv_list_set(list, i, replacement, usage);
> > + dma_resv_list_set(list, i, dma_fence_get(replacement), usage);
> > dma_fence_put(old);
> > }
> > }
>
Re: [PATCH 3/3] drm/amdkfd: remove an unnecessary amdgpu_bo_ref
Am 2022-07-25 um 06:32 schrieb Lang Yu: No need to reference the BO here, dmabuf framework will handle that. OK. I guess I needed to do that manually for the userptr attachment, and copy/pasted it unnecessarily for the dmabuf attachment. Reviewed-by: Felix Kuehling Signed-off-by: Lang Yu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index c1855b72a3f0..802c762108b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -827,7 +827,6 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, *bo = gem_to_amdgpu_bo(gobj); (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE; - (*bo)->parent = amdgpu_bo_ref(mem->bo); return 0; }
RE: [PATCH 3/3] drm/amdkfd: remove an unnecessary amdgpu_bo_ref
[Public] Ping for this single patch. >-Original Message- >From: Yu, Lang >Sent: Monday, July 25, 2022 6:32 PM >To: amd-gfx@lists.freedesktop.org >Cc: Kuehling, Felix ; Koenig, Christian >; Deucher, Alexander >; Huang, Ray ; Yu, Lang > >Subject: [PATCH 3/3] drm/amdkfd: remove an unnecessary amdgpu_bo_ref > >No need to reference the BO here, dmabuf framework will handle that. > >Signed-off-by: Lang Yu >--- > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 - > 1 file changed, 1 deletion(-) > >diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >index c1855b72a3f0..802c762108b2 100644 >--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >@@ -827,7 +827,6 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, >struct kgd_mem *mem, > > *bo = gem_to_amdgpu_bo(gobj); > (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE; >- (*bo)->parent = amdgpu_bo_ref(mem->bo); > > return 0; > } >-- >2.25.1
RE: [PATCH 5/5] drm/amdgpu: enable VCN cg and JPEG cg/pg i
Ping Best Regards, Yifan -Original Message- From: amd-gfx On Behalf Of Sonny Jiang Sent: Friday, July 22, 2022 1:27 AM To: amd-gfx@lists.freedesktop.org Cc: Jiang, Sonny ; Zhu, James Subject: [PATCH 5/5] drm/amdgpu: enable VCN cg and JPEG cg/pg i Not enable VCN pg because encode issue Signed-off-by: Sonny Jiang Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 68e78983f956..52816de5e17b 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -585,8 +585,11 @@ static int soc21_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x10; break; case IP_VERSION(11, 0, 1): - adev->cg_flags = 0; - adev->pg_flags = 0; + adev->cg_flags = + AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_JPEG_MGCG; + adev->pg_flags = + AMD_PG_SUPPORT_JPEG; adev->external_rev_id = adev->rev_id + 0x1; break; default: -- 2.36.1
[PATCH] drm/amdgpu: Fix stub fence refcount underflow
Don't drop the stub fence reference after installing it as a replacement
for the eviction fence. dma_resv_replace_fences doesn't take another
reference to the fence, so it takes ownership of the reference passed
in by us.
Fixes: 548e7432dc2d ("dma-buf: add dma_resv_replace_fences v2")
CC: Christian König
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 87a3a3ae9448..a6c7dcd8c345 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -294,7 +294,6 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct
amdgpu_bo *bo,
replacement = dma_fence_get_stub();
dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
replacement, DMA_RESV_USAGE_READ);
- dma_fence_put(replacement);
return 0;
}
--
2.32.0
Re: [PATCH] drm/amd/display: Remove unused struct freesync_context
On 2022-07-27 13:50, Maíra Canal wrote:
All references to struct freesync_context were removed, so remove the
struct freesync_context itself and its entry on struct dc_stream_state.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index c3d97206ed89..f87f852d4829 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -48,11 +48,6 @@ struct dc_stream_status {
bool is_abm_supported;
};
-// TODO: References to this needs to be removed..
-struct freesync_context {
- bool dummy;
-};
-
enum hubp_dmdata_mode {
DMDATA_SW_MODE,
DMDATA_HW_MODE
@@ -184,9 +179,6 @@ struct dc_stream_state {
struct rect src; /* composition area */
struct rect dst; /* stream addressable area */
- // TODO: References to this needs to be removed..
- struct freesync_context freesync_ctx;
-
struct audio_info audio_info;
struct dc_info_packet hdr_static_metadata;
Reviewed-by: Rodrigo Siqueira
and applied to amd-staging-drm-next.
Thanks
Siqueira
Re: [PATCH 0/4] Revert reduce stack size for DML code
On 2022-07-27 18:22, Alex Deucher wrote: Series is: Reviewed-by: Alex Deucher Thanks Alex, Patshet pushed to amd-staging-drm-next. Best Regards Siqueira On Wed, Jul 27, 2022 at 6:19 PM Rodrigo Siqueira wrote: We had a stack size issue on DML, and we tried to fix it by moving some of the local variables to some of the DML struct. In this process of reducing the stack size, we sent some other patches that fixed the issue reported by Stephen, and the below set of patches become unnecessary: 987949933127 drm/amd/display: reduce stack for dml32_CalculatePrefetchSchedule 8f08cd32b767 drm/amd/display: reduce stack for dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport 5d526d124fe3 drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath f6ceebcc7825 drm/amd/display: reduce stack for dml32_CalculateSwathAndDETConfiguration For this reason, this patchset reverts all of the above patches. Cc: Aurabindo Pillai Cc: Stephen Rothwell Cc: Alex Deucher Thanks Siqueira Rodrigo Siqueira (4): Revert "drm/amd/display: reduce stack for dml32_CalculatePrefetchSchedule" Revert "drm/amd/display: reduce stack for dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport" Revert "drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath" Revert "drm/amd/display: reduce stack for dml32_CalculateSwathAndDETConfiguration" .../dc/dml/dcn32/display_mode_vba_32.c| 12 +- .../dc/dml/dcn32/display_mode_vba_util_32.c | 812 ++ .../dc/dml/dcn32/display_mode_vba_util_32.h | 5 - .../drm/amd/display/dc/dml/display_mode_vba.h | 106 --- 4 files changed, 441 insertions(+), 494 deletions(-) -- 2.35.1
Re: [PATCH 0/4] Revert reduce stack size for DML code
Series is: Reviewed-by: Alex Deucher On Wed, Jul 27, 2022 at 6:19 PM Rodrigo Siqueira wrote: > > We had a stack size issue on DML, and we tried to fix it by moving some > of the local variables to some of the DML struct. In this process of > reducing the stack size, we sent some other patches that fixed the issue > reported by Stephen, and the below set of patches become unnecessary: > > 987949933127 drm/amd/display: reduce stack for dml32_CalculatePrefetchSchedule > 8f08cd32b767 drm/amd/display: reduce stack for > dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport > 5d526d124fe3 drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath > f6ceebcc7825 drm/amd/display: reduce stack for > dml32_CalculateSwathAndDETConfiguration > > For this reason, this patchset reverts all of the above patches. > > Cc: Aurabindo Pillai > Cc: Stephen Rothwell > Cc: Alex Deucher > > Thanks > Siqueira > > Rodrigo Siqueira (4): > Revert "drm/amd/display: reduce stack for > dml32_CalculatePrefetchSchedule" > Revert "drm/amd/display: reduce stack for > dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport" > Revert "drm/amd/display: reduce stack for > dml32_CalculateVMRowAndSwath" > Revert "drm/amd/display: reduce stack for > dml32_CalculateSwathAndDETConfiguration" > > .../dc/dml/dcn32/display_mode_vba_32.c| 12 +- > .../dc/dml/dcn32/display_mode_vba_util_32.c | 812 ++ > .../dc/dml/dcn32/display_mode_vba_util_32.h | 5 - > .../drm/amd/display/dc/dml/display_mode_vba.h | 106 --- > 4 files changed, 441 insertions(+), 494 deletions(-) > > -- > 2.35.1 >
[PATCH 4/4] Revert "drm/amd/display: reduce stack for dml32_CalculateSwathAndDETConfiguration"
This reverts commit ca6730ca0f01cd918087344c0c22cf6ed840db9d.
This commit was a part of a patchset responsible for reducing the stack
size. However, after some other changes, this commit becomes
unnecessary, so we are reverting it here.
Cc: Aurabindo Pillai
Reported-by: Stephen Rothwell
Acked-by: Alex Deucher
Signed-off-by: Rodrigo Siqueira
---
.../dc/dml/dcn32/display_mode_vba_32.c| 3 -
.../dc/dml/dcn32/display_mode_vba_util_32.c | 121 +-
.../dc/dml/dcn32/display_mode_vba_util_32.h | 2 -
.../drm/amd/display/dc/dml/display_mode_vba.h | 15 ---
4 files changed, 64 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 3cfd3cc4d60c..cb2025771646 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -221,7 +221,6 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
// VBA_DELTA
// Calculate DET size, swath height
dml32_CalculateSwathAndDETConfiguration(
-
&v->dummy_vars.dml32_CalculateSwathAndDETConfiguration,
mode_lib->vba.DETSizeOverride,
mode_lib->vba.UsesMALLForPStateChange,
mode_lib->vba.ConfigReturnBufferSizeInKByte,
@@ -1948,7 +1947,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
}
dml32_CalculateSwathAndDETConfiguration(
- &v->dummy_vars.dml32_CalculateSwathAndDETConfiguration,
mode_lib->vba.DETSizeOverride,
mode_lib->vba.UsesMALLForPStateChange,
mode_lib->vba.ConfigReturnBufferSizeInKByte,
@@ -2545,7 +2543,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
}
dml32_CalculateSwathAndDETConfiguration(
-
&v->dummy_vars.dml32_CalculateSwathAndDETConfiguration,
mode_lib->vba.DETSizeOverride,
mode_lib->vba.UsesMALLForPStateChange,
mode_lib->vba.ConfigReturnBufferSizeInKByte,
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index f9adfd7371dc..05fc14a47fba 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -391,7 +391,6 @@ void dml32_CalculateBytePerPixelAndBlockSizes(
} // CalculateBytePerPixelAndBlockSizes
void dml32_CalculateSwathAndDETConfiguration(
- struct dml32_CalculateSwathAndDETConfiguration *st_vars,
unsigned int DETSizeOverride[],
enum dm_use_mall_for_pstate_change_mode
UseMALLForPStateChange[],
unsigned int ConfigReturnBufferSizeInKByte,
@@ -456,10 +455,18 @@ void dml32_CalculateSwathAndDETConfiguration(
bool ViewportSizeSupportPerSurface[],
bool *ViewportSizeSupport)
{
+ unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+ unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+ unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX];
+ unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX];
+ unsigned int RoundedUpSwathSizeBytesY;
+ unsigned int RoundedUpSwathSizeBytesC;
+ double SwathWidthdoubleDPP[DC__NUM_DPP__MAX];
+ double SwathWidthdoubleDPPChroma[DC__NUM_DPP__MAX];
unsigned int k;
-
- st_vars->TotalActiveDPP = 0;
- st_vars->NoChromaSurfaces = true;
+ unsigned int TotalActiveDPP = 0;
+ bool NoChromaSurfaces = true;
+ unsigned int DETBufferSizeInKByteForSwathCalculation;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);
@@ -494,43 +501,43 @@ void dml32_CalculateSwathAndDETConfiguration(
DPPPerSurface,
/* Output */
- st_vars->SwathWidthdoubleDPP,
- st_vars->SwathWidthdoubleDPPChroma,
+ SwathWidthdoubleDPP,
+ SwathWidthdoubleDPPChroma,
SwathWidth,
SwathWidthChroma,
- st_vars->MaximumSwathHeightY,
- st_vars->MaximumSwathHeightC,
+ MaximumSwathHeightY,
+ MaximumSwathHeightC,
swath_width_luma_ub,
swath_width_chroma_ub);
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
-
[PATCH 1/4] Revert "drm/amd/display: reduce stack for dml32_CalculatePrefetchSchedule"
This reverts commit 361e705e712d2255f5b0f6e6cc69687043d4fcc9.
This commit was a part of a patchset responsible for reducing the stack
size. However, after some other changes, this commit becomes
unnecessary, so we are reverting it here.
Cc: Aurabindo Pillai
Reported-by: Stephen Rothwell
Acked-by: Alex Deucher
Signed-off-by: Rodrigo Siqueira
---
.../dc/dml/dcn32/display_mode_vba_32.c| 5 +-
.../dc/dml/dcn32/display_mode_vba_util_32.c | 394 ++
.../dc/dml/dcn32/display_mode_vba_util_32.h | 1 -
.../drm/amd/display/dc/dml/display_mode_vba.h | 38 --
4 files changed, 211 insertions(+), 227 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 890612db08dc..04f1eefdabe8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -757,9 +757,7 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelY
= v->BytePerPixelY[k];
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelC
= v->BytePerPixelC[k];
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ProgressiveToInterlaceUnitInOPP
= mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
- v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(
-
&v->dummy_vars.dml32_CalculatePrefetchSchedule,
-
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
+ v->ErrorResult[k] =
dml32_CalculatePrefetchSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe,
v->DSCDelay[k],
mode_lib->vba.DPPCLKDelaySubtotal +
mode_lib->vba.DPPCLKDelayCNVCFormater,
mode_lib->vba.DPPCLKDelaySCL,
@@ -3266,7 +3264,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
mode_lib->vba.NoTimeForPrefetch[i][j][k] =
dml32_CalculatePrefetchSchedule(
-
&v->dummy_vars.dml32_CalculatePrefetchSchedule,
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor,
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe,
mode_lib->vba.DSCDelayPerState[i][k],
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 07f8f3b8626b..54dde0ea424a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3342,7 +3342,6 @@ double dml32_CalculateExtraLatency(
} // CalculateExtraLatency
bool dml32_CalculatePrefetchSchedule(
- struct dml32_CalculatePrefetchSchedule *st_vars,
double HostVMInefficiencyFactor,
DmlPipe *myPipe,
unsigned int DSCDelay,
@@ -3406,18 +3405,45 @@ bool dml32_CalculatePrefetchSchedule(
double *VReadyOffsetPix)
{
bool MyError = false;
-
- st_vars->TimeForFetchingMetaPTE = 0;
- st_vars->TimeForFetchingRowInVBlank = 0;
- st_vars->LinesToRequestPrefetchPixelData = 0;
- st_vars->max_vratio_pre = __DML_MAX_VRATIO_PRE__;
- st_vars->Tsw_est1 = 0;
- st_vars->Tsw_est3 = 0;
+ unsigned int DPPCycles, DISPCLKCycles;
+ double DSTTotalPixelsAfterScaler;
+ double LineTime;
+ double dst_y_prefetch_equ;
+ double prefetch_bw_oto;
+ double Tvm_oto;
+ double Tr0_oto;
+ double Tvm_oto_lines;
+ double Tr0_oto_lines;
+ double dst_y_prefetch_oto;
+ double TimeForFetchingMetaPTE = 0;
+ double TimeForFetchingRowInVBlank = 0;
+ double LinesToRequestPrefetchPixelData = 0;
+ unsigned int HostVMDynamicLevelsTrips;
+ double trip_to_mem;
+ double Tvm_trips;
+ double Tr0_trips;
+ double Tvm_trips_rounded;
+ double Tr0_trips_rounded;
+ double Lsw_oto;
+ double Tpre_r
[PATCH 3/4] Revert "drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath"
This reverts commit a0a68cda2ef8446b55d1b0baa8c352812639b196.
This commit was a part of a patchset responsible for reducing the stack
size. However, after some other changes, this commit becomes
unnecessary, so we are reverting it here.
Cc: Aurabindo Pillai
Reported-by: Stephen Rothwell
Acked-by: Alex Deucher
Signed-off-by: Rodrigo Siqueira
---
.../dc/dml/dcn32/display_mode_vba_32.c| 2 -
.../dc/dml/dcn32/display_mode_vba_util_32.c | 110 ++
.../dc/dml/dcn32/display_mode_vba_util_32.h | 1 -
.../drm/amd/display/dc/dml/display_mode_vba.h | 19 ---
4 files changed, 62 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 55f351d5b610..3cfd3cc4d60c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -461,7 +461,6 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
{
dml32_CalculateVMRowAndSwath(
- &v->dummy_vars.dml32_CalculateVMRowAndSwath,
mode_lib->vba.NumberOfActiveSurfaces,
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters,
v->SurfaceSizeInMALL,
@@ -2746,7 +2745,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
{
dml32_CalculateVMRowAndSwath(
-
&v->dummy_vars.dml32_CalculateVMRowAndSwath,
mode_lib->vba.NumberOfActiveSurfaces,
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters,
mode_lib->vba.SurfaceSizeInMALL,
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index c0dab2b2c446..f9adfd7371dc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -1867,7 +1867,6 @@ void dml32_CalculateSurfaceSizeInMall(
} // CalculateSurfaceSizeInMall
void dml32_CalculateVMRowAndSwath(
- struct dml32_CalculateVMRowAndSwath *st_vars,
unsigned int NumberOfActiveSurfaces,
DmlPipe myPipe[],
unsigned int SurfaceSizeInMALL[],
@@ -1933,6 +1932,21 @@ void dml32_CalculateVMRowAndSwath(
unsigned int BIGK_FRAGMENT_SIZE[])
{
unsigned int k;
+ unsigned int PTEBufferSizeInRequestsForLuma[DC__NUM_DPP__MAX];
+ unsigned int PTEBufferSizeInRequestsForChroma[DC__NUM_DPP__MAX];
+ unsigned int PDEAndMetaPTEBytesFrameY;
+ unsigned int PDEAndMetaPTEBytesFrameC;
+ unsigned int MetaRowByteY[DC__NUM_DPP__MAX];
+ unsigned int MetaRowByteC[DC__NUM_DPP__MAX];
+ unsigned int PixelPTEBytesPerRowY[DC__NUM_DPP__MAX];
+ unsigned int PixelPTEBytesPerRowC[DC__NUM_DPP__MAX];
+ unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DC__NUM_DPP__MAX];
+ unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DC__NUM_DPP__MAX];
+ unsigned int dpte_row_width_luma_ub_one_row_per_frame[DC__NUM_DPP__MAX];
+ unsigned int dpte_row_height_luma_one_row_per_frame[DC__NUM_DPP__MAX];
+ unsigned int
dpte_row_width_chroma_ub_one_row_per_frame[DC__NUM_DPP__MAX];
+ unsigned int dpte_row_height_chroma_one_row_per_frame[DC__NUM_DPP__MAX];
+ bool one_row_per_frame_fits_in_buffer[DC__NUM_DPP__MAX];
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
if (HostVMEnable == true) {
@@ -1954,15 +1968,15 @@ void dml32_CalculateVMRowAndSwath(
myPipe[k].SourcePixelFormat == dm_rgbe_alpha) {
if ((myPipe[k].SourcePixelFormat == dm_420_10 ||
myPipe[k].SourcePixelFormat == dm_420_12) &&
!IsVertical(myPipe[k].SourceRotation)) {
- st_vars->PTEBufferSizeInRequestsForLuma[k] =
+ PTEBufferSizeInRequestsForLuma[k] =
(PTEBufferSizeInRequestsLuma +
PTEBufferSizeInRequestsChroma) / 2;
- st_vars->PTEBufferSizeInRequestsForChroma[k] =
st_vars->PTEBufferSizeInRequestsForLuma[k];
+ PTEBufferSizeInRequestsForChroma[k] =
PTEBufferSizeInRequestsForLuma[k];
} else {
- st_vars->PTEBufferSizeInRequestsForLuma[k] =
PTEBufferSizeInRequestsLuma;
- st_vars->PTEBufferSiz
[PATCH 2/4] Revert "drm/amd/display: reduce stack for dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport"
This reverts commit f2dbf5a4dd1eaa8893afe7a970cd89f075316d18.
This commit was a part of a patchset responsible for reducing the stack
size. However, after some other changes, this commit becomes
unnecessary, so we are reverting it here.
Cc: Aurabindo Pillai
Reported-by: Stephen Rothwell
Acked-by: Alex Deucher
Signed-off-by: Rodrigo Siqueira
---
.../dc/dml/dcn32/display_mode_vba_32.c| 2 -
.../dc/dml/dcn32/display_mode_vba_util_32.c | 187 ++
.../dc/dml/dcn32/display_mode_vba_util_32.h | 1 -
.../drm/amd/display/dc/dml/display_mode_vba.h | 34
4 files changed, 104 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 04f1eefdabe8..55f351d5b610 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1165,7 +1165,6 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.SMNLatency
= mode_lib->vba.SMNLatency;
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
-
&v->dummy_vars.dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport,
mode_lib->vba.USRRetrainingRequiredFinal,
mode_lib->vba.UsesMALLForPStateChange,
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
@@ -3563,7 +3562,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
{
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
-
&v->dummy_vars.dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport,
mode_lib->vba.USRRetrainingRequiredFinal,
mode_lib->vba.UsesMALLForPStateChange,
mode_lib->vba.PrefetchModePerState[i][j],
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 54dde0ea424a..c0dab2b2c446 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -4185,7 +4185,6 @@ void dml32_CalculateFlipSchedule(
} // CalculateFlipSchedule
void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
- struct
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport *st_vars,
bool USRRetrainingRequiredFinal,
enum dm_use_mall_for_pstate_change_mode
UseMALLForPStateChange[],
unsigned int PrefetchMode,
@@ -4247,15 +4246,37 @@ void
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
double ActiveDRAMClockChangeLatencyMargin[])
{
unsigned int i, j, k;
-
- st_vars->SurfaceWithMinActiveFCLKChangeMargin = 0;
- st_vars->DRAMClockChangeSupportNumber = 0;
- st_vars->DRAMClockChangeMethod = 0;
- st_vars->FoundFirstSurfaceWithMinActiveFCLKChangeMargin = false;
- st_vars->MinActiveFCLKChangeMargin = 0.;
- st_vars->SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = 0.;
- st_vars->TotalPixelBW = 0.0;
- st_vars->TotalActiveWriteback = 0;
+ unsigned int SurfaceWithMinActiveFCLKChangeMargin = 0;
+ unsigned int DRAMClockChangeSupportNumber = 0;
+ unsigned int LastSurfaceWithoutMargin;
+ unsigned int DRAMClockChangeMethod = 0;
+ bool FoundFirstSurfaceWithMinActiveFCLKChangeMargin = false;
+ double MinActiveFCLKChangeMargin = 0.;
+ double SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = 0.;
+ double ActiveClockChangeLatencyHidingY;
+ double ActiveClockChangeLatencyHidingC;
+ double ActiveClockChangeLatencyHiding;
+double EffectiveDETBufferSizeY;
+ double ActiveFCLKChangeLatencyMargin[DC__NUM_DPP__MAX];
+ double USRRetrainingLatencyMargin[DC__NUM_DPP__MAX];
+ double TotalPixelBW = 0.0;
+ boolSynchronizedSurfaces[DC__NUM_DPP__MAX][DC__NUM_DPP__MAX];
+ double EffectiveLBLatencyHidingY;
+ double EffectiveLBLatencyHidingC;
+ double LinesInDETY[DC__NUM_DPP__MAX];
+ double LinesInDETC[DC__NUM_DPP__MAX];
+ unsigned intLinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
+ unsigned intLinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
+ double FullDETBufferingTimeY;
+ double FullDETBufferingTimeC;
+ double WritebackDRAMClockChangeLatencyMargin;
+ double WritebackFCLKChangeLatencyM
[PATCH 0/4] Revert reduce stack size for DML code
We had a stack size issue on DML, and we tried to fix it by moving some of the local variables to some of the DML struct. In this process of reducing the stack size, we sent some other patches that fixed the issue reported by Stephen, and the below set of patches become unnecessary: 987949933127 drm/amd/display: reduce stack for dml32_CalculatePrefetchSchedule 8f08cd32b767 drm/amd/display: reduce stack for dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport 5d526d124fe3 drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath f6ceebcc7825 drm/amd/display: reduce stack for dml32_CalculateSwathAndDETConfiguration For this reason, this patchset reverts all of the above patches. Cc: Aurabindo Pillai Cc: Stephen Rothwell Cc: Alex Deucher Thanks Siqueira Rodrigo Siqueira (4): Revert "drm/amd/display: reduce stack for dml32_CalculatePrefetchSchedule" Revert "drm/amd/display: reduce stack for dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport" Revert "drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath" Revert "drm/amd/display: reduce stack for dml32_CalculateSwathAndDETConfiguration" .../dc/dml/dcn32/display_mode_vba_32.c| 12 +- .../dc/dml/dcn32/display_mode_vba_util_32.c | 812 ++ .../dc/dml/dcn32/display_mode_vba_util_32.h | 5 - .../drm/amd/display/dc/dml/display_mode_vba.h | 106 --- 4 files changed, 441 insertions(+), 494 deletions(-) -- 2.35.1
[PATCH] drm/amd/display: Fix vblank refcount in vrr transition
manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on
which causes drm_crtc_vblank_get in vrr_transition to fail, and later
when drm_crtc_vblank_put is called the refcount on vblank will be messed
up. Therefore move the call to after manage_dm_interrupts.
Unchecked calls to drm_crtc_vblank_get seems to be common in other
drivers as well so it may make sense to let get always succeed during
modset, see
https://lists.freedesktop.org/archives/dri-devel/2022-July/365589.html
Signed-off-by: Yunxiang Li
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 ---
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 92470a0e0262..2107b2aef076 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8252,23 +8252,6 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
mutex_unlock(&dm->dc_lock);
}
- /* Count number of newly disabled CRTCs for dropping PM refs later. */
- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
- if (old_crtc_state->active && !new_crtc_state->active)
- crtc_disable_count++;
-
- dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
- dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-
- /* For freesync config update on crtc state and params for irq
*/
- update_stream_irq_parameters(dm, dm_new_crtc_state);
-
- /* Handle vrr on->off / off->on transitions */
- amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
- dm_new_crtc_state);
- }
-
/**
* Enable interrupts for CRTCs that are newly enabled or went through
* a modeset. It was intentionally deferred until after the front end
@@ -8287,7 +8270,15 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
cur_crc_src = acrtc->dm_irq_params.crc_src;
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
#endif
+ /* Count number of newly disabled CRTCs for dropping PM refs
later. */
+ if (old_crtc_state->active && !new_crtc_state->active)
+ crtc_disable_count++;
+
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
+ /* For freesync config update on crtc state and params for irq
*/
+ update_stream_irq_parameters(dm, dm_new_crtc_state);
if (new_crtc_state->active &&
(!old_crtc_state->active ||
@@ -8324,6 +8315,9 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
DRM_DEBUG_DRIVER("Failed to configure
crc source");
#endif
}
+
+ /* Handle vrr on->off / off->on transitions */
+ amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
dm_new_crtc_state);
}
for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
--
2.37.1
[Patch v2] drm/amdgpu: Avoid direct cast to amdgpu_ttm_tt
For typesafety, use container_of() instead of implicit cast from struct
ttm_tt to struct amdgpu_ttm_tt.
Cc: Christian König
Signed-off-by: Rajneesh Bhardwaj
---
Changes in v2:
* Fixed a bug that Felix pointed out in V1 by updating the macro
definition
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 34 +
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index be0efaae79a9..8a6c8db31c00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -637,6 +637,8 @@ struct amdgpu_ttm_tt {
#endif
};
+#define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt,
ttm)
+
#ifdef CONFIG_DRM_AMDGPU_USERPTR
/*
* amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
@@ -648,7 +650,7 @@ struct amdgpu_ttm_tt {
int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
{
struct ttm_tt *ttm = bo->tbo.ttm;
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
unsigned long start = gtt->userptr;
struct vm_area_struct *vma;
struct mm_struct *mm;
@@ -702,7 +704,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
struct page **pages)
*/
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
{
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
bool r = false;
if (!gtt || !gtt->userptr)
@@ -751,7 +753,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
@@ -788,7 +790,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
@@ -822,7 +824,7 @@ static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
{
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
struct ttm_tt *ttm = tbo->ttm;
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
if (amdgpu_bo_encrypted(abo))
flags |= AMDGPU_PTE_TMZ;
@@ -860,7 +862,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
struct ttm_resource *bo_mem)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void*)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
uint64_t flags;
int r;
@@ -927,7 +929,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_operation_ctx ctx = { false, false };
- struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
struct ttm_placement placement;
struct ttm_place placements;
struct ttm_resource *tmp;
@@ -998,7 +1000,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
/* if the pages have userptr pinning then clear that first */
if (gtt->userptr) {
@@ -1025,7 +1027,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device
*bdev,
static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
struct ttm_tt *ttm)
{
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
if (gtt->usertask)
put_task_struct(gtt->usertask);
@@ -1079,7 +1081,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
struct ttm_operation_ctx *ctx)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
pgoff_t i;
int ret;
@@ -1113,7 +1115,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
[PATCH] drm/amd/display: Remove unused struct freesync_context
All references to struct freesync_context were removed, so remove the
struct freesync_context itself and its entry on struct dc_stream_state.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index c3d97206ed89..f87f852d4829 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -48,11 +48,6 @@ struct dc_stream_status {
bool is_abm_supported;
};
-// TODO: References to this needs to be removed..
-struct freesync_context {
- bool dummy;
-};
-
enum hubp_dmdata_mode {
DMDATA_SW_MODE,
DMDATA_HW_MODE
@@ -184,9 +179,6 @@ struct dc_stream_state {
struct rect src; /* composition area */
struct rect dst; /* stream addressable area */
- // TODO: References to this needs to be removed..
- struct freesync_context freesync_ctx;
-
struct audio_info audio_info;
struct dc_info_packet hdr_static_metadata;
--
2.37.1
Re: [PATCH] drm/amd/display: Reduce stack size in the mode support function
On Wed, Jul 27, 2022 at 12:27 PM Rodrigo Siqueira Jordao wrote: > > > > On 2022-07-24 17:41, Stephen Rothwell wrote: > > Hi all, > > > > On Fri, 22 Jul 2022 14:12:44 -0400 Alex Deucher > > wrote: > >> > >> On Fri, Jul 22, 2022 at 1:56 PM Rodrigo Siqueira > >> wrote: > >>> > >>> When we use the allmodconfig option we see the following error: > >>> > >>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: > >>> In function 'dml32_ModeSupportAndSystemConfigurationFull': > >>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1: > >>> error: the frame size of 2464 bytes is larger than 2048 bytes > >>> [-Werror=frame-larger-than=] > >>>3799 | } // ModeSupportAndSystemConfigurationFull > >>> > >>> This commit fixes this issue by moving part of the mode support > >>> operation from ModeSupportAndSystemConfigurationFull to a dedicated > >>> function. > >>> > >>> Cc: Harry Wentland > >>> Cc: Alex Deucher > >>> Cc: Aurabindo Pillai > >>> Cc: Stephen Rothwell > >>> Signed-off-by: Rodrigo Siqueira > >> > >> Thanks for sorting this out! > >> Acked-by: Alex Deucher > > > > Tested-by: Stephen Rothwell > > > > Also, after applying the above patch, the following commits are no > > longer needed: > > > > 987949933127 drm/amd/display: reduce stack for > > dml32_CalculatePrefetchSchedule > > 8f08cd32b767 drm/amd/display: reduce stack for > > dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport > > 5d526d124fe3 drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath > > f6ceebcc7825 drm/amd/display: reduce stack for > > dml32_CalculateSwathAndDETConfiguration > > > > and could be reverted (or removed). > > Ohhh... that's nice! > > Alex, if you don't mind, I would prefer to revert the above patches to > keep things simpler. If it is ok for you, I can prepare the revert patches. Sure. Please go ahead. Acked-by: Alex Deucher Alex > > Thanks > Siqueira
Re: [PATCH] drm/amd/display: Reduce stack size in the mode support function
On 2022-07-24 17:41, Stephen Rothwell wrote: Hi all, On Fri, 22 Jul 2022 14:12:44 -0400 Alex Deucher wrote: On Fri, Jul 22, 2022 at 1:56 PM Rodrigo Siqueira wrote: When we use the allmodconfig option we see the following error: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In function 'dml32_ModeSupportAndSystemConfigurationFull': drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1: error: the frame size of 2464 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] 3799 | } // ModeSupportAndSystemConfigurationFull This commit fixes this issue by moving part of the mode support operation from ModeSupportAndSystemConfigurationFull to a dedicated function. Cc: Harry Wentland Cc: Alex Deucher Cc: Aurabindo Pillai Cc: Stephen Rothwell Signed-off-by: Rodrigo Siqueira Thanks for sorting this out! Acked-by: Alex Deucher Tested-by: Stephen Rothwell Also, after applying the above patch, the following commits are no longer needed: 987949933127 drm/amd/display: reduce stack for dml32_CalculatePrefetchSchedule 8f08cd32b767 drm/amd/display: reduce stack for dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport 5d526d124fe3 drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath f6ceebcc7825 drm/amd/display: reduce stack for dml32_CalculateSwathAndDETConfiguration and could be reverted (or removed). Ohhh... that's nice! Alex, if you don't mind, I would prefer to revert the above patches to keep things simpler. If it is ok for you, I can prepare the revert patches. Thanks Siqueira
Re: [PATCH] drm/amdkfd: use time_is_before_jiffies(a + b) to replace "jiffies - a > b"
This patch introduces a build warning for me:
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o
In file included from /home/fkuehlin/compute/kernel/include/linux/spinlock.h:54,
from /home/fkuehlin/compute/kernel/include/linux/mmzone.h:8,
from /home/fkuehlin/compute/kernel/include/linux/gfp.h:6,
from /home/fkuehlin/compute/kernel/include/linux/slab.h:15,
from
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.c:44:
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.c:
In function ?interrupt_wq?:
/home/fkuehlin/compute/kernel/include/linux/typecheck.h:12:18: warning:
comparison of distinct pointer types lacks a cast
12 | (void)(&__dummy == &__dummy2); \
| ^~
/home/fkuehlin/compute/kernel/include/linux/jiffies.h:106:3: note: in expansion
of macro ?typecheck?
106 | typecheck(unsigned long, b) && \
| ^
/home/fkuehlin/compute/kernel/include/linux/jiffies.h:154:35: note: in
expansion of macro ?time_after?
154 | #define time_is_before_jiffies(a) time_after(jiffies, a)
| ^~
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.c:159:7:
note: in expansion of macro ?time_is_before_jiffies?
159 | if (time_is_before_jiffies(start_jiffies + HZ)) {
| ^~
I think you need to change the the definition of start_jiffies to be
unsigned long. Do you want to submit a v2 of your patch?
That said, I think the existing code was fine, though the type-mismatch
highlighted by your patch is a bit iffy.
Regards,
Felix
Am 2022-07-26 um 22:59 schrieb Yu Zhe:
time_is_before_jiffies deals with timer wrapping correctly.
Signed-off-by: Yu Zhe
---
drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index a9466d154395..6397926e059c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
@@ -156,7 +156,7 @@ static void interrupt_wq(struct work_struct *work)
while (dequeue_ih_ring_entry(dev, ih_ring_entry)) {
dev->device_info.event_interrupt_class->interrupt_wq(dev,
ih_ring_entry);
- if (jiffies - start_jiffies > HZ) {
+ if (time_is_before_jiffies(start_jiffies + HZ)) {
/* If we spent more than a second processing signals,
* reschedule the worker to avoid soft-lockup warnings
*/
Re: [PATCH -next] drm/amd/display: remove unneeded semicolon
On 2022-07-26 18:28, Yang Li wrote: Eliminate the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c:2344:67-68: Unneeded semicolon Reported-by: Abaci Robot Signed-off-by: Yang Li --- drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 39428488a052..ca44df4fca74 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -2341,7 +2341,7 @@ void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc, dout_wb.wb_dst_width = wb_info->dwb_params.dest_width; dout_wb.wb_dst_height = wb_info->dwb_params.dest_height; dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; - dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;; + dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; dout_wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; dout_wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ? Reviewed-by: Rodrigo Siqueira And applied to amd-staging-drm-next. Thanks Siqueira
Re: [PATCH v2] drm/ttm: Fix dummy res NULL ptr deref bug
Hi Arunpravin, Às 02:30 de 27/07/22, Arunpravin Paneer Selvam escreveu: > Check the bo->resource value before accessing the resource > mem_type. > > v2: Fix commit description unwrapped warning > > > [ 40.191227][ T184] general protection fault, probably for non-canonical > address 0xdc02: [#1] SMP KASAN PTI > [ 40.192995][ T184] KASAN: null-ptr-deref in range > [0x0010-0x0017] > [ 40.194411][ T184] CPU: 1 PID: 184 Comm: systemd-udevd Not tainted > 5.19.0-rc4-00721-gb297c22b7070 #1 > [ 40.196063][ T184] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), > BIOS 1.16.0-debian-1.16.0-4 04/01/2014 > [ 40.199605][ T184] RIP: 0010:ttm_bo_validate+0x1b3/0x240 [ttm] > [ 40.200754][ T184] Code: e8 72 c5 ff ff 83 f8 b8 74 d4 85 c0 75 54 49 8b > 9e 58 01 00 00 48 b8 00 00 00 00 00 fc ff df 48 8d 7b 10 48 89 fa 48 c1 ea 03 > <0f> b6 04 02 84 c0 74 04 3c 03 7e 44 8b 53 10 31 c0 85 d2 0f 85 58 > [ 40.203685][ T184] RSP: 0018:c96df0c8 EFLAGS: 00010202 > [ 40.204630][ T184] RAX: dc00 RBX: RCX: > 11102f4bb71b > [ 40.205864][ T184] RDX: 0002 RSI: c96df208 RDI: > 0010 > [ 40.207102][ T184] RBP: 192dbe1a R08: c96df208 R09: > > [ 40.208394][ T184] R10: 88817a5f R11: 0001 R12: > c96df110 > [ 40.209692][ T184] R13: c96df0f0 R14: 88817a5db800 R15: > c96df208 > [ 40.210862][ T184] FS: 7f6b1d16e8c0() GS:88839d70() > knlGS: > [ 40.212250][ T184] CS: 0010 DS: ES: CR0: 80050033 > [ 40.213275][ T184] CR2: 55a1001d4ff0 CR3: 0001700f4000 CR4: > 06e0 > [ 40.214469][ T184] Call Trace: > [ 40.214974][ T184] > [ 40.215438][ T184] ? ttm_bo_bounce_temp_buffer+0x140/0x140 [ttm] > [ 40.216572][ T184] ? mutex_spin_on_owner+0x240/0x240 > [ 40.217456][ T184] ? drm_vma_offset_add+0xaa/0x100 [drm] > [ 40.218457][ T184] ttm_bo_init_reserved+0x3d6/0x540 [ttm] > [ 40.219410][ T184] ? shmem_get_inode+0x744/0x980 > [ 40.220231][ T184] ttm_bo_init_validate+0xb1/0x200 [ttm] > [ 40.221172][ T184] ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper] > [ 40.222530][ T184] ? ttm_bo_init_reserved+0x540/0x540 [ttm] > [ 40.223643][ T184] ? __do_sys_finit_module+0x11a/0x1c0 > [ 40.224654][ T184] ? __shmem_file_setup+0x102/0x280 > [ 40.234764][ T184] drm_gem_vram_create+0x305/0x480 [drm_vram_helper] > [ 40.235766][ T184] ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper] > [ 40.236846][ T184] ? __kasan_slab_free+0x108/0x180 > [ 40.237650][ T184] drm_gem_vram_fill_create_dumb+0x134/0x340 > [drm_vram_helper] > [ 40.238864][ T184] ? local_pci_probe+0xdf/0x180 > [ 40.239674][ T184] ? drmm_vram_helper_init+0x400/0x400 [drm_vram_helper] > [ 40.240826][ T184] drm_client_framebuffer_create+0x19c/0x400 [drm] > [ 40.241955][ T184] ? drm_client_buffer_delete+0x200/0x200 [drm] > [ 40.243001][ T184] ? drm_client_pick_crtcs+0x554/0xb80 [drm] > [ 40.244030][ T184] drm_fb_helper_generic_probe+0x23f/0x940 > [drm_kms_helper] > [ 40.245226][ T184] ? __cond_resched+0x1c/0xc0 > [ 40.245987][ T184] ? drm_fb_helper_memory_range_to_clip+0x180/0x180 > [drm_kms_helper] > [ 40.247316][ T184] ? mutex_unlock+0x80/0x100 > [ 40.248005][ T184] ? __mutex_unlock_slowpath+0x2c0/0x2c0 > [ 40.249083][ T184] drm_fb_helper_single_fb_probe+0x907/0xf00 > [drm_kms_helper] > [ 40.250314][ T184] ? drm_fb_helper_check_var+0x1180/0x1180 > [drm_kms_helper] > [ 40.251540][ T184] ? __cond_resched+0x1c/0xc0 > [ 40.252321][ T184] ? mutex_lock+0x9f/0x100 > [ 40.253062][ T184] __drm_fb_helper_initial_config_and_unlock+0xb9/0x2c0 > [drm_kms_helper] > [ 40.254394][ T184] drm_fbdev_client_hotplug+0x56f/0x840 [drm_kms_helper] > [ 40.255477][ T184] drm_fbdev_generic_setup+0x165/0x3c0 [drm_kms_helper] > [ 40.256607][ T184] bochs_pci_probe+0x6b7/0x900 [bochs] > [ 40.257515][ T184] ? _raw_spin_lock_irqsave+0x87/0x100 > [ 40.258312][ T184] ? bochs_hw_init+0x480/0x480 [bochs] > [ 40.259244][ T184] ? bochs_hw_init+0x480/0x480 [bochs] > [ 40.260186][ T184] local_pci_probe+0xdf/0x180 > [ 40.260928][ T184] pci_call_probe+0x15f/0x500 > [ 40.265798][ T184] ? _raw_spin_lock+0x81/0x100 > [ 40.266508][ T184] ? pci_pm_suspend_noirq+0x980/0x980 > [ 40.267322][ T184] ? pci_assign_irq+0x81/0x280 > [ 40.268096][ T184] ? pci_match_device+0x351/0x6c0 > [ 40.268883][ T184] ? kernfs_put+0x18/0x40 > [ 40.269611][ T184] pci_device_probe+0xee/0x240 > [ 40.270352][ T184] really_probe+0x435/0xa80 > [ 40.271021][ T184] __driver_probe_device+0x2ab/0x480 > [ 40.271828][ T184] driver_probe_device+0x49/0x140 > [ 40.272627][ T184] __driver_attach+0x1bd/0x4c0 > [ 40.273372][ T184] ? __device_attach_driver+0x240/0x240 > [
Re: [PATCH] drm/amdgpu: fix i2s_pdata out of bound array access
On Wed, Jul 27, 2022 at 11:16 AM Mukunda,Vijendar
wrote:
>
> On 7/27/22 8:25 PM, Alex Deucher wrote:
> > On Wed, Jul 27, 2022 at 10:42 AM Vijendar Mukunda
> > wrote:
> >>
> >> Fixed following Smatch static checker warning:
> >>
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:393 acp_hw_init()
> >> error: buffer overflow 'i2s_pdata' 3 <= 3
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:396 acp_hw_init()
> >> error: buffer overflow 'i2s_pdata' 3 <= 3
> >>
> >> Reported-by: Dan Carpenter
> >> Signed-off-by: Vijendar Mukunda
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 8
> >> 1 file changed, 8 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> >> index bcc7ee02e0fc..6d72355ac492 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> >> @@ -390,14 +390,6 @@ static int acp_hw_init(void *handle)
> >> i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
> >> i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
> >>
> >> - i2s_pdata[3].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
> >> - switch (adev->asic_type) {
> >> - case CHIP_STONEY:
> >> - i2s_pdata[3].quirks |=
> >> DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
> >> - break;
> >> - default:
> >> - break;
> >> - }
> >
> > Is this actually not used or should we just increase the allocation size?
> >
> > Alex
> it's my bad. i2s_pdata array size is 3. when we recently included code
> changes for JD platform , this piece of code was added mistakenly for
> Stoney platform switch case.
Thanks. Patch is:
Acked-by: Alex Deucher
>
> --
> Vijendar
>
> >
> >> adev->acp.acp_res[0].name = "acp2x_dma";
> >> adev->acp.acp_res[0].flags = IORESOURCE_MEM;
> >> adev->acp.acp_res[0].start = acp_base;
> >> --
> >> 2.25.1
> >>
>
Re: [PATCH] drm/amdgpu: fix i2s_pdata out of bound array access
On 7/27/22 8:25 PM, Alex Deucher wrote:
> On Wed, Jul 27, 2022 at 10:42 AM Vijendar Mukunda
> wrote:
>>
>> Fixed following Smatch static checker warning:
>>
>> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:393 acp_hw_init()
>> error: buffer overflow 'i2s_pdata' 3 <= 3
>> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:396 acp_hw_init()
>> error: buffer overflow 'i2s_pdata' 3 <= 3
>>
>> Reported-by: Dan Carpenter
>> Signed-off-by: Vijendar Mukunda
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 8
>> 1 file changed, 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> index bcc7ee02e0fc..6d72355ac492 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> @@ -390,14 +390,6 @@ static int acp_hw_init(void *handle)
>> i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
>> i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
>>
>> - i2s_pdata[3].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
>> - switch (adev->asic_type) {
>> - case CHIP_STONEY:
>> - i2s_pdata[3].quirks |=
>> DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
>> - break;
>> - default:
>> - break;
>> - }
>
> Is this actually not used or should we just increase the allocation size?
>
> Alex
it's my bad. i2s_pdata array size is 3. when we recently included code
changes for JD platform , this piece of code was added mistakenly for
Stoney platform switch case.
--
Vijendar
>
>> adev->acp.acp_res[0].name = "acp2x_dma";
>> adev->acp.acp_res[0].flags = IORESOURCE_MEM;
>> adev->acp.acp_res[0].start = acp_base;
>> --
>> 2.25.1
>>
Re: [PATCH] drm/amdgpu: fix i2s_pdata out of bound array access
On Wed, Jul 27, 2022 at 10:42 AM Vijendar Mukunda
wrote:
>
> Fixed following Smatch static checker warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:393 acp_hw_init()
> error: buffer overflow 'i2s_pdata' 3 <= 3
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:396 acp_hw_init()
> error: buffer overflow 'i2s_pdata' 3 <= 3
>
> Reported-by: Dan Carpenter
> Signed-off-by: Vijendar Mukunda
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> index bcc7ee02e0fc..6d72355ac492 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> @@ -390,14 +390,6 @@ static int acp_hw_init(void *handle)
> i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
> i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
>
> - i2s_pdata[3].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
> - switch (adev->asic_type) {
> - case CHIP_STONEY:
> - i2s_pdata[3].quirks |=
> DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
> - break;
> - default:
> - break;
> - }
Is this actually not used or should we just increase the allocation size?
Alex
> adev->acp.acp_res[0].name = "acp2x_dma";
> adev->acp.acp_res[0].flags = IORESOURCE_MEM;
> adev->acp.acp_res[0].start = acp_base;
> --
> 2.25.1
>
[PATCH] drm/amdgpu: fix i2s_pdata out of bound array access
Fixed following Smatch static checker warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:393 acp_hw_init()
error: buffer overflow 'i2s_pdata' 3 <= 3
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:396 acp_hw_init()
error: buffer overflow 'i2s_pdata' 3 <= 3
Reported-by: Dan Carpenter
Signed-off-by: Vijendar Mukunda
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index bcc7ee02e0fc..6d72355ac492 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -390,14 +390,6 @@ static int acp_hw_init(void *handle)
i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
- i2s_pdata[3].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
- switch (adev->asic_type) {
- case CHIP_STONEY:
- i2s_pdata[3].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
- break;
- default:
- break;
- }
adev->acp.acp_res[0].name = "acp2x_dma";
adev->acp.acp_res[0].flags = IORESOURCE_MEM;
adev->acp.acp_res[0].start = acp_base;
--
2.25.1
Re: [PATCH 5/5] drm/amdgpu: reduce reset time
On 2022-07-27 06:35, Zhao, Victor wrote:
[AMD Official Use Only - General]
Hi Andrey,
Problem with status.hang is that it is set at
amdgpu_device_ip_check_soft_reset, which is not implemented in nv or gfx10.
They have to be nicely implemented first.
Another option I thought is to mark status.hang or add a flag to amdgpu_gfx
when job timeout reported on gfx/comp ring. And this will require some logic to
map the relationship for ring and ip blocks. This way does not look good as
well.
I don't think we need this at the ring level, its enough to know that
the reset you are going through is because of one of rings are hanged to
apply this skip logic, it's pretty easy if we add 'bool hang' flag to
adev->reset_domain
which u can set in the beginning amdgpu_job_timedout and clear in the
end. No protection is required as all the resets from all origins are
serialized with timeout handler in a single threaded queue.
Andrey
Thanks,
Victor
-Original Message-
From: Grodzovsky, Andrey
Sent: Wednesday, July 27, 2022 12:57 AM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Deng, Emily ;
Koenig, Christian
Subject: Re: [PATCH 5/5] drm/amdgpu: reduce reset time
On 2022-07-26 05:40, Zhao, Victor wrote:
[AMD Official Use Only - General]
Hi Andrey,
Reply inline.
Thanks,
Victor
-Original Message-
From: Grodzovsky, Andrey
Sent: Tuesday, July 26, 2022 5:18 AM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Deng, Emily
; Koenig, Christian
Subject: Re: [PATCH 5/5] drm/amdgpu: reduce reset time
On 2022-07-22 03:34, Victor Zhao wrote:
In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset
Why are they failing in this case ? Skipping ring tests is not the best idea as
you loose important indicator of system's sanity. Is there any way to make them
work ?
[Victor]: I've seen gfx ring test fail every time after a gfx engine hang. I
thought it should be expected as gfx is in a bad state. Do you know the reason
we have ring tests before reset? As we are going to reset the asic anyway.
Another approach could be to make the skip mode2 only or reduce the wait time
here.
I dug down in history and according to commit 'drm/amdgpu:unmap KCQ in gfx
hw_fini(v2)' you need to write to scratch register for completion of queue
unmap operation so you defently don't want to just skip it. I agree in case
that the ring is hung this has no point but remember that GPU reset can happen
not only to a hunged ring but for other reasons (RAS, manual reset e.t.c.) in
which case you probably want to shut down gracefully here ?
I see we have adev->ip_blocks[i].status.hang flag which you maybe can use here
instead ?
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++--
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 222d3d7ea076..f872495ccc3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -477,7 +477,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
RESET_QUEUES, 0, 0);
- if (adev->gfx.kiq.ring.sched.ready)
+ if (adev->gfx.kiq.ring.sched.ready && !amdgpu_in_reset(adev))
r = amdgpu_ring_test_helper(kiq_ring);
spin_unlock(&adev->gfx.kiq.ring_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fafbad3cf08d..9ae29023e38f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5971,16 +5971,19 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device
*adev, bool enable)
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
}
- for (i = 0; i < adev->usec_timeout; i++) {
- if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
- break;
- udelay(1);
- }
-
- if (i >= adev->usec_timeout)
- DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
+ if (!amdgpu_in_reset(adev)) {
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
+ break;
+ udelay(1);
+ }
+ if (i >= adev->usec_timeout)
+ DRM_ERROR("failed to %s cp gfx\n",
+ enable ? "unhalt" : "halt");
+ }
return 0;
+
}
This change has impact beyond container case no ? We had no issue with this
code during regular reset cases so why we would
RE: [PATCH 5/5] drm/amdgpu: reduce reset time
[AMD Official Use Only - General]
Hi Andrey,
Problem with status.hang is that it is set at
amdgpu_device_ip_check_soft_reset, which is not implemented in nv or gfx10.
They have to be nicely implemented first.
Another option I thought is to mark status.hang or add a flag to amdgpu_gfx
when job timeout reported on gfx/comp ring. And this will require some logic to
map the relationship for ring and ip blocks. This way does not look good as
well.
Thanks,
Victor
-Original Message-
From: Grodzovsky, Andrey
Sent: Wednesday, July 27, 2022 12:57 AM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Deng, Emily
; Koenig, Christian
Subject: Re: [PATCH 5/5] drm/amdgpu: reduce reset time
On 2022-07-26 05:40, Zhao, Victor wrote:
> [AMD Official Use Only - General]
>
> Hi Andrey,
>
> Reply inline.
>
>
> Thanks,
> Victor
>
>
>
> -Original Message-
> From: Grodzovsky, Andrey
> Sent: Tuesday, July 26, 2022 5:18 AM
> To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Deng, Emily
> ; Koenig, Christian
> Subject: Re: [PATCH 5/5] drm/amdgpu: reduce reset time
>
>
> On 2022-07-22 03:34, Victor Zhao wrote:
>> In multi container use case, reset time is important, so skip ring
>> tests and cp halt wait during ip suspending for reset as they are
>> going to fail and cost more time on reset
>
> Why are they failing in this case ? Skipping ring tests is not the best idea
> as you loose important indicator of system's sanity. Is there any way to make
> them work ?
>
> [Victor]: I've seen gfx ring test fail every time after a gfx engine hang. I
> thought it should be expected as gfx is in a bad state. Do you know the
> reason we have ring tests before reset? As we are going to reset the asic
> anyway.
> Another approach could be to make the skip mode2 only or reduce the wait time
> here.
I dug down in history and according to commit 'drm/amdgpu:unmap KCQ in gfx
hw_fini(v2)' you need to write to scratch register for completion of queue
unmap operation so you defently don't want to just skip it. I agree in case
that the ring is hung this has no point but remember that GPU reset can happen
not only to a hunged ring but for other reasons (RAS, manual reset e.t.c.) in
which case you probably want to shut down gracefully here ?
I see we have adev->ip_blocks[i].status.hang flag which you maybe can use here
instead ?
>
>
>> Signed-off-by: Victor Zhao
>> ---
>>drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
>>drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++--
>>2 files changed, 17 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index 222d3d7ea076..f872495ccc3a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -477,7 +477,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
>> kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
>> RESET_QUEUES, 0, 0);
>>
>> -if (adev->gfx.kiq.ring.sched.ready)
>> +if (adev->gfx.kiq.ring.sched.ready && !amdgpu_in_reset(adev))
>> r = amdgpu_ring_test_helper(kiq_ring);
>> spin_unlock(&adev->gfx.kiq.ring_lock);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index fafbad3cf08d..9ae29023e38f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -5971,16 +5971,19 @@ static int gfx_v10_0_cp_gfx_enable(struct
>> amdgpu_device *adev, bool enable)
>> WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
>> }
>>
>> -for (i = 0; i < adev->usec_timeout; i++) {
>> -if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
>> -break;
>> -udelay(1);
>> -}
>> -
>> -if (i >= adev->usec_timeout)
>> -DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
>> +if (!amdgpu_in_reset(adev)) {
>> +for (i = 0; i < adev->usec_timeout; i++) {
>> +if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
>> +break;
>> +udelay(1);
>> +}
>>
>> +if (i >= adev->usec_timeout)
>> +DRM_ERROR("failed to %s cp gfx\n",
>> + enable ? "unhalt" : "halt");
>> +}
>> return 0;
>> +
>>}
>
> This change has impact beyond container case no ? We had no issue with this
> code during regular reset cases so why we would give up on this code which
> confirms CP is idle ? What is the side effect of skipping this during all GPU
> resets ?
>
> Andrey
>
> [Victor]: I see "failed to halt cp gfx" with regular reset cases as well when
> doing a gfx hang test using quark. I haven't seen a side effect with Mode1
> reset yet but maybe shorten the wait t
RE: [PATCH] drm/amd/amdgpu: add additional page fault settings for gfx11
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chengming Gui
Sent: Wednesday, July 27, 2022 16:59
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking
Cc: Gui, Jack
Subject: [PATCH] drm/amd/amdgpu: add additional page fault settings for gfx11
Add three additional page fault settings.
V2: move reg offset definition to header file. (Alex)
V3: add all shift/mask definitions of used reg. (Hawking)
Signed-off-by: Chengming Gui
Reviewed-by: Hawking Zhang
Change-Id: Ibab979853fd233a1c2017672f2534947fa1d637d
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 32 ---
.../include/asic_reg/gc/gc_11_0_0_offset.h| 3 ++
.../include/asic_reg/gc/gc_11_0_0_sh_mask.h | 25 +++
3 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
index 5eccaa2c7ca0..0e13370c2057 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
@@ -26,13 +26,10 @@
#include "gc/gc_11_0_0_offset.h"
#include "gc/gc_11_0_0_sh_mask.h"
+#include "gc/gc_11_0_0_default.h"
#include "navi10_enum.h"
#include "soc15_common.h"
-#define regGCVM_L2_CNTL3_DEFAULT 0x8017
-#define regGCVM_L2_CNTL4_DEFAULT 0x00c1
-#define regGCVM_L2_CNTL5_DEFAULT 0x3fe0
-
static const char *gfxhub_client_ids[] = {
"CB/DB",
"Reserved",
@@ -414,12 +411,39 @@ static void gfxhub_v3_0_set_fault_enable_default(struct
amdgpu_device *adev, {
u32 tmp;
+ /* NO halt CP when page fault */
+ tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
+ tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
+ WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
+
+ /**
+* Set GRBM_GFX_INDEX in broad cast mode
+* before programming GL1C_UTCL0_CNTL1 and SQG_CONFIG
+*/
+ WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, regGRBM_GFX_INDEX_DEFAULT);
+
+ /**
+* Retry respond mode: RETRY
+* Error (no retry) respond mode: SUCCESS
+*/
+ tmp = RREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1);
+ tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_MODE, 0);
+ tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_FAULT_MODE, 0x2);
+ WREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1, tmp);
+
/* These registers are not accessible to VF-SRIOV.
* The PF will program them instead.
*/
if (amdgpu_sriov_vf(adev))
return;
+ /* Disable SQ XNACK interrupt for all VMIDs */
+ tmp = RREG32_SOC15(GC, 0, regSQG_CONFIG);
+ tmp = REG_SET_FIELD(tmp, SQG_CONFIG, XNACK_INTR_MASK,
+ SQG_CONFIG__XNACK_INTR_MASK_MASK >>
+ SQG_CONFIG__XNACK_INTR_MASK__SHIFT);
+ WREG32_SOC15(GC, 0, regSQG_CONFIG, tmp);
+
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); diff
--git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
index e5b85bf1d7dc..c92c4b83253f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
@@ -4221,6 +4221,7 @@
#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX
0
#define regGB_EDC_MODE
0x1e1e
#define regGB_EDC_MODE_BASE_IDX
0
+#define regCP_DEBUG
0x1e1f
#define regCP_DEBUG_BASE_IDX
0
#define regCP_CPC_DEBUG
0x1e21
#define regCP_CPC_DEBUG_BASE_IDX
0
@@ -8306,6 +8307,8 @@
#define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX
1
#define regGL1C_STATUS
0x2d41
#define regGL1C_STATUS_BASE_IDX
1
+#define regGL1C_UTCL0_CNTL1
0x2d42
+#define regGL1C_UTCL0_CNTL1_BASE_IDX
1
#define regGL1C_UTCL0_CNTL2
0x2d43
#define regGL1C_UTCL0_CNTL2_BASE_IDX
Re: Crash on resume from S3
https://gitlab.freedesktop.org/drm/amd/-/issues/2105 On Tue, Jul 26, 2022 at 6:10 PM Andrey Grodzovsky wrote: > > The stack trace is expected part of reset procedure so that ok. The > issue you are having is a hang on one of GPU jobs during resume which > triggers a GPU reset attempt. > > You can open a ticket with this issue here > https://gitlab.freedesktop.org/drm/amd/-/issues, please attach full > dmesg log. > > Andrey > > On 2022-07-26 05:06, Tom Cook wrote: > > I have a Ryzen 7 3700U in an HP laptop. lspci describes the GPU in this > > way: > > > > 04:00.0 VGA compatible controller: Advanced Micro Devices, Inc. > > [AMD/ATI] Picasso/Raven 2 [Radeon Vega Series / Radeon Vega Mobile > > Series] (rev c1) > > > > This laptop has never successfully resumed from suspend (I have tried > > every 5.x kernel). Currently on 5.18.0, the system appears to be okay > > after resume apart from the gpu which is usually giving a blank > > screen, occasionally a scrambled output. After rebooting, I see this > > in syslog: > > > > Jul 25 11:02:18 frog kernel: [240782.968674] amdgpu :04:00.0: > > amdgpu: GPU reset begin! > > Jul 25 11:02:19 frog kernel: [240783.974891] amdgpu :04:00.0: > > [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test > > failed (-110) > > Jul 25 11:02:19 frog kernel: [240783.988650] [drm] free PSP TMR buffer > > Jul 25 11:02:19 frog kernel: [240784.019057] CPU: 4 PID: 305612 Comm: > > kworker/u32:17 Not tainted 5.18.0 #1 > > Jul 25 11:02:19 frog kernel: [240784.019063] Hardware name: HP HP ENVY > > x360 Convertible 15-ds0xxx/85DD, BIOS F.20 05/28/2020 > > Jul 25 11:02:19 frog kernel: [240784.019067] Workqueue: > > amdgpu-reset-dev drm_sched_job_timedout [gpu_sched] > > Jul 25 11:02:19 frog kernel: [240784.019079] Call Trace: > > Jul 25 11:02:19 frog kernel: [240784.019082] > > Jul 25 11:02:19 frog kernel: [240784.019085] dump_stack_lvl+0x49/0x5f > > Jul 25 11:02:19 frog kernel: [240784.019095] dump_stack+0x10/0x12 > > Jul 25 11:02:19 frog kernel: [240784.019099] > > amdgpu_do_asic_reset+0x2f/0x4e0 [amdgpu] > > Jul 25 11:02:19 frog kernel: [240784.019278] > > amdgpu_device_gpu_recover_imp+0x41e/0xb50 [amdgpu] > > Jul 25 11:02:19 frog kernel: [240784.019452] > > amdgpu_job_timedout+0x155/0x1b0 [amdgpu] > > Jul 25 11:02:19 frog kernel: [240784.019674] > > drm_sched_job_timedout+0x74/0xf0 [gpu_sched] > > Jul 25 11:02:19 frog kernel: [240784.019681] ? > > amdgpu_cgs_destroy_device+0x10/0x10 [amdgpu] > > Jul 25 11:02:19 frog kernel: [240784.019896] ? > > drm_sched_job_timedout+0x74/0xf0 [gpu_sched] > > Jul 25 11:02:19 frog kernel: [240784.019903] process_one_work+0x227/0x440 > > Jul 25 11:02:19 frog kernel: [240784.019908] worker_thread+0x31/0x3d0 > > Jul 25 11:02:19 frog kernel: [240784.019912] ? process_one_work+0x440/0x440 > > Jul 25 11:02:19 frog kernel: [240784.019914] kthread+0xfe/0x130 > > Jul 25 11:02:19 frog kernel: [240784.019918] ? > > kthread_complete_and_exit+0x20/0x20 > > Jul 25 11:02:19 frog kernel: [240784.019923] ret_from_fork+0x22/0x30 > > Jul 25 11:02:19 frog kernel: [240784.019930] > > Jul 25 11:02:19 frog kernel: [240784.019934] amdgpu :04:00.0: > > amdgpu: MODE2 reset > > Jul 25 11:02:19 frog kernel: [240784.020178] amdgpu :04:00.0: > > amdgpu: GPU reset succeeded, trying to resume > > Jul 25 11:02:19 frog kernel: [240784.020552] [drm] PCIE GART of 1024M > > enabled. > > Jul 25 11:02:19 frog kernel: [240784.020555] [drm] PTB located at > > 0x00F40090 > > Jul 25 11:02:19 frog kernel: [240784.020577] [drm] VRAM is lost due to > > GPU reset! > > Jul 25 11:02:19 frog kernel: [240784.020579] [drm] PSP is resuming... > > Jul 25 11:02:19 frog kernel: [240784.040465] [drm] reserve 0x40 > > from 0xf47fc0 for PSP TMR > > > > I'm running the latest BIOS from HP. Is there anything I can do to > > work around this? Or anything I can do to help debug it? > > > > Regards, > > Tom Cook
[PATCH] dma-buf: use struct_size helper instead of kzalloc
Replace zero-length array allocation with flexible-array member
because Dynamic calculations should not be performed for memory
allocator due to the risk of them overflowing. So using struct_size()
helper instead of an open-coded version in order to avoid any potential
type mistakes.
Signed-off-by: Arvind Yadav
---
drivers/dma-buf/dma-fence-array.c | 6 ++
include/linux/dma-fence-array.h | 2 ++
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/dma-buf/dma-fence-array.c
b/drivers/dma-buf/dma-fence-array.c
index 5c8a7084577b..3ebb6c5fa287 100644
--- a/drivers/dma-buf/dma-fence-array.c
+++ b/drivers/dma-buf/dma-fence-array.c
@@ -70,7 +70,7 @@ static void dma_fence_array_cb_func(struct dma_fence *f,
static bool dma_fence_array_enable_signaling(struct dma_fence *fence)
{
struct dma_fence_array *array = to_dma_fence_array(fence);
- struct dma_fence_array_cb *cb = (void *)(&array[1]);
+ struct dma_fence_array_cb *cb = array->array_cb;
unsigned i;
for (i = 0; i < array->num_fences; ++i) {
@@ -157,13 +157,11 @@ struct dma_fence_array *dma_fence_array_create(int
num_fences,
bool signal_on_any)
{
struct dma_fence_array *array;
- size_t size = sizeof(*array);
WARN_ON(!num_fences || !fences);
/* Allocate the callback structures behind the array. */
- size += num_fences * sizeof(struct dma_fence_array_cb);
- array = kzalloc(size, GFP_KERNEL);
+ array = kzalloc(struct_size(array, array_cb, num_fences), GFP_KERNEL);
if (!array)
return NULL;
diff --git a/include/linux/dma-fence-array.h b/include/linux/dma-fence-array.h
index ec7f25def392..bd2d2db55840 100644
--- a/include/linux/dma-fence-array.h
+++ b/include/linux/dma-fence-array.h
@@ -33,6 +33,7 @@ struct dma_fence_array_cb {
* @num_pending: fences in the array still pending
* @fences: array of the fences
* @work: internal irq_work function
+ * @array_cb: callback helper for fence array
*/
struct dma_fence_array {
struct dma_fence base;
@@ -43,6 +44,7 @@ struct dma_fence_array {
struct dma_fence **fences;
struct irq_work work;
+ struct dma_fence_array_cb array_cb[];
};
/**
--
2.25.1
[PATCH] drm/amdkfd: use time_is_before_jiffies(a + b) to replace "jiffies - a > b"
time_is_before_jiffies deals with timer wrapping correctly.
Signed-off-by: Yu Zhe
---
drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index a9466d154395..6397926e059c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
@@ -156,7 +156,7 @@ static void interrupt_wq(struct work_struct *work)
while (dequeue_ih_ring_entry(dev, ih_ring_entry)) {
dev->device_info.event_interrupt_class->interrupt_wq(dev,
ih_ring_entry);
- if (jiffies - start_jiffies > HZ) {
+ if (time_is_before_jiffies(start_jiffies + HZ)) {
/* If we spent more than a second processing signals,
* reschedule the worker to avoid soft-lockup warnings
*/
--
2.11.0
[PATCH -next] drm/amd/display: remove unneeded semicolon
Eliminate the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c:2344:67-68: Unneeded semicolon Reported-by: Abaci Robot Signed-off-by: Yang Li --- drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 39428488a052..ca44df4fca74 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -2341,7 +2341,7 @@ void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc, dout_wb.wb_dst_width = wb_info->dwb_params.dest_width; dout_wb.wb_dst_height = wb_info->dwb_params.dest_height; dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; - dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;; + dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; dout_wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; dout_wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ? -- 2.20.1.7.g153144c
