Re: [PATCH 7/8] drm/amd/display: Introduce KUnit tests to dc_dmub_srv library

[Maíra Canal]

On 8/11/22 04:37, David Gow wrote:

On Thu, Aug 11, 2022 at 8:41 AM Tales Aparecida
 wrote:


From: Maíra Canal 

Add unit test to the SubVP feature in order to avoid possible
regressions and assure the code robustness.

Signed-off-by: Maíra Canal 
Signed-off-by: Tales Aparecida 
---


FYI: This seems to have a dependency issue. See below.

Otherwise, I haven't had a chance to review it properly yet, but I'll
try to take a closer look over the next few days.

Cheers,
-- David


  drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |   4 +
  .../amd/display/tests/dc/dc_dmub_srv_test.c   | 285 ++
  2 files changed, 289 insertions(+)
  create mode 100644 drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 2d61c2a91cee..f5dd1f69840e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -809,3 +809,7 @@ void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv 
*dc_dmub_srv)
 diag_data.is_cw0_enabled,
 diag_data.is_cw6_enabled);
  }
+
+#if IS_ENABLED(CONFIG_AMD_DC_BASICS_KUNIT_TEST)
+#include "../tests/dc/dc_dmub_srv_test.c"
+#endif
diff --git a/drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c 
b/drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c
new file mode 100644
index ..051079cbf65e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: MIT
+/*
+ * KUnit tests for dc_dmub_srv.c
+ *
+ * Copyright (C) 2022, Maíra Canal 
+ */
+
+#include 
+#include "dc_dmub_srv.h"
+
+struct populate_subvp_cmd_drr_info_test_case {
+   const char *desc;
+   struct dc *dc;
+   struct pipe_ctx *subvp_pipe;
+   struct pipe_ctx *vblank_pipe;
+   const u8 drr_in_use;
+   const u8 drr_window_size_ms;
+   const u16 min_vtotal_supported;
+   const u16 max_vtotal_supported;
+   const u8 use_ramping;
+};
+
+struct populate_subvp_cmd_drr_info_test_case 
populate_subvp_cmd_drr_info_cases[] = {
+   {
+   .desc = "Same Clock Frequency",
+   .dc = &(struct dc) {
+   .caps = {
+   .subvp_prefetch_end_to_mall_start_us = 0,
+   }
+   },
+   .subvp_pipe = &(struct pipe_ctx) {
+   .stream = &(struct dc_stream_state) {
+   .timing = {
+   .h_total = 2784,
+   .v_addressable = 1080,
+   .pix_clk_100hz = 1855800,
+   },
+   .mall_stream_config = {
+   .paired_stream = &(struct 
dc_stream_state) {
+   .timing = {
+   .h_total = 3600,
+   .v_total = ,
+   .v_addressable = 1080,
+   .v_front_porch = 3,
+   .pix_clk_100hz = 
1855800,
+   },
+   },
+   },
+   },
+   },
+   .vblank_pipe = &(struct pipe_ctx) {
+   .stream = &(struct dc_stream_state) {
+   .timing = {
+   .h_total = 2784,
+   .v_total = ,
+   .v_addressable = 1080,
+   .pix_clk_100hz = 1855800,
+   },
+   },
+   },
+   .drr_in_use = true,
+   .use_ramping = false,
+   .drr_window_size_ms = 4,
+   .min_vtotal_supported = 2540,
+   .max_vtotal_supported = 2619,
+   },
+   {
+   .desc = "Same Clock Frequency with Prefetch End to Mall Start",
+   .dc = &(struct dc) {
+   .caps = {
+   .subvp_prefetch_end_to_mall_start_us = 500,
+   }
+   },
+   .subvp_pipe = &(struct pipe_ctx) {
+   .stream = &(struct dc_stream_state) {
+   .timing = {
+   .h_total = 2784,
+   .v_addressable = 1080,
+   .pix_clk_100hz = 1855800,
+   },
+   .mall_stream_config = {
+   .paired_stream = &

[PATCH 7/8] drm/amd/display: Introduce KUnit tests to dc_dmub_srv library

[Tales Aparecida]

From: Maíra Canal 

Add unit test to the SubVP feature in order to avoid possible
regressions and assure the code robustness.

Signed-off-by: Maíra Canal 
Signed-off-by: Tales Aparecida 
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |   4 +
 .../amd/display/tests/dc/dc_dmub_srv_test.c   | 285 ++
 2 files changed, 289 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 2d61c2a91cee..f5dd1f69840e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -809,3 +809,7 @@ void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv 
*dc_dmub_srv)
diag_data.is_cw0_enabled,
diag_data.is_cw6_enabled);
 }
+
+#if IS_ENABLED(CONFIG_AMD_DC_BASICS_KUNIT_TEST)
+#include "../tests/dc/dc_dmub_srv_test.c"
+#endif
diff --git a/drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c 
b/drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c
new file mode 100644
index ..051079cbf65e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: MIT
+/*
+ * KUnit tests for dc_dmub_srv.c
+ *
+ * Copyright (C) 2022, Maíra Canal 
+ */
+
+#include 
+#include "dc_dmub_srv.h"
+
+struct populate_subvp_cmd_drr_info_test_case {
+   const char *desc;
+   struct dc *dc;
+   struct pipe_ctx *subvp_pipe;
+   struct pipe_ctx *vblank_pipe;
+   const u8 drr_in_use;
+   const u8 drr_window_size_ms;
+   const u16 min_vtotal_supported;
+   const u16 max_vtotal_supported;
+   const u8 use_ramping;
+};
+
+struct populate_subvp_cmd_drr_info_test_case 
populate_subvp_cmd_drr_info_cases[] = {
+   {
+   .desc = "Same Clock Frequency",
+   .dc = &(struct dc) {
+   .caps = {
+   .subvp_prefetch_end_to_mall_start_us = 0,
+   }
+   },
+   .subvp_pipe = &(struct pipe_ctx) {
+   .stream = &(struct dc_stream_state) {
+   .timing = {
+   .h_total = 2784,
+   .v_addressable = 1080,
+   .pix_clk_100hz = 1855800,
+   },
+   .mall_stream_config = {
+   .paired_stream = &(struct 
dc_stream_state) {
+   .timing = {
+   .h_total = 3600,
+   .v_total = ,
+   .v_addressable = 1080,
+   .v_front_porch = 3,
+   .pix_clk_100hz = 
1855800,
+   },
+   },
+   },
+   },
+   },
+   .vblank_pipe = &(struct pipe_ctx) {
+   .stream = &(struct dc_stream_state) {
+   .timing = {
+   .h_total = 2784,
+   .v_total = ,
+   .v_addressable = 1080,
+   .pix_clk_100hz = 1855800,
+   },
+   },
+   },
+   .drr_in_use = true,
+   .use_ramping = false,
+   .drr_window_size_ms = 4,
+   .min_vtotal_supported = 2540,
+   .max_vtotal_supported = 2619,
+   },
+   {
+   .desc = "Same Clock Frequency with Prefetch End to Mall Start",
+   .dc = &(struct dc) {
+   .caps = {
+   .subvp_prefetch_end_to_mall_start_us = 500,
+   }
+   },
+   .subvp_pipe = &(struct pipe_ctx) {
+   .stream = &(struct dc_stream_state) {
+   .timing = {
+   .h_total = 2784,
+   .v_addressable = 1080,
+   .pix_clk_100hz = 1855800,
+   },
+   .mall_stream_config = {
+   .paired_stream = &(struct 
dc_stream_state) {
+   .timing = {
+   .h_total = 3600,
+   .v_total = ,
+   .v_addressabl