Re: [casper] over mapping

2009-11-18 Thread Mark Wagner
Hi Laura,

For FPGA utilization, I look at the file:
sysgen/synth_model/modelfilename_cw.syr

Mark


On Wed, Nov 18, 2009 at 2:26 PM, Laura Spitler wrote:

> Hi everyone,
>
> I have a general question about over mapping a design. What's the
> easiest way to determine by how much I've over utilized the chip?
> The log files don't seem to give a resource summary when mapping fails
> with an error.
>
> Thanks!
> Laura
>
>


Re: [casper] over mapping

2009-11-18 Thread G Jones
Hi Laura,
At least with 7.1, the output of system generator includes a log file
that gives some rough usage numbers. The IO will always be overmapped
in these reports because all of the connections for shared registers
and brams and such are considered IO pins, but you may be able to get
some useful info about the logic usage.
Glenn

On Wed, Nov 18, 2009 at 2:26 PM, Laura Spitler  wrote:
> Hi everyone,
>
> I have a general question about over mapping a design. What's the
> easiest way to determine by how much I've over utilized the chip?
> The log files don't seem to give a resource summary when mapping fails
> with an error.
>
> Thanks!
> Laura
>
>