r298208 - [X86][AVX512][Clang][Intrinsics] Adding missing intrinsics to Clang .
Author: ibreger
Date: Sun Mar 19 03:27:16 2017
New Revision: 298208
URL: http://llvm.org/viewvc/llvm-project?rev=298208&view=rev
Log:
[X86][AVX512][Clang][Intrinsics] Adding missing intrinsics to Clang .
Summary:
Adding missing intrinsics :
_mm512_set_epi16,
_mm512_set_epi8,
_mm512_permutevar_epi32
_mm512_mask_permutevar_epi32
Reviewers: zvi, guyblank, eladcohen, craig.topper
Reviewed By: craig.topper
Subscribers: craig.topper, cfe-commits
Differential Revision: https://reviews.llvm.org/D31034
Modified:
cfe/trunk/lib/Headers/avx512fintrin.h
cfe/trunk/test/CodeGen/avx512f-builtins.c
Modified: cfe/trunk/lib/Headers/avx512fintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/avx512fintrin.h?rev=298208&r1=298207&r2=298208&view=diff
==
--- cfe/trunk/lib/Headers/avx512fintrin.h (original)
+++ cfe/trunk/lib/Headers/avx512fintrin.h Sun Mar 19 03:27:16 2017
@@ -8848,6 +8848,8 @@ _mm512_permutexvar_epi32 (__m512i __X, _
(__mmask16) -1);
}
+#define _mm512_permutevar_epi32 _mm512_permutexvar_epi32
+
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_mask_permutexvar_epi32 (__m512i __W, __mmask16 __M, __m512i __X,
__m512i __Y)
@@ -8858,6 +8860,8 @@ _mm512_mask_permutexvar_epi32 (__m512i _
__M);
}
+#define _mm512_mask_permutevar_epi32 _mm512_mask_permutexvar_epi32
+
static __inline__ __mmask16 __DEFAULT_FN_ATTRS
_mm512_kand (__mmask16 __A, __mmask16 __B)
{
@@ -9625,6 +9629,45 @@ _mm512_mask_set1_epi64 (__m512i __O, __m
}
#endif
+static __inline __m512i __DEFAULT_FN_ATTRS
+_mm512_set_epi8 (char __e63, char __e62, char __e61, char __e60, char __e59,
+char __e58, char __e57, char __e56, char __e55, char __e54, char __e53,
+char __e52, char __e51, char __e50, char __e49, char __e48, char __e47,
+char __e46, char __e45, char __e44, char __e43, char __e42, char __e41,
+char __e40, char __e39, char __e38, char __e37, char __e36, char __e35,
+char __e34, char __e33, char __e32, char __e31, char __e30, char __e29,
+char __e28, char __e27, char __e26, char __e25, char __e24, char __e23,
+char __e22, char __e21, char __e20, char __e19, char __e18, char __e17,
+char __e16, char __e15, char __e14, char __e13, char __e12, char __e11,
+char __e10, char __e9, char __e8, char __e7, char __e6, char __e5,
+char __e4, char __e3, char __e2, char __e1, char __e0) {
+
+ return __extension__ (__m512i)(__v64qi)
+{__e0, __e1, __e2, __e3, __e4, __e5, __e6, __e7,
+ __e8, __e9, __e10, __e11, __e12, __e13, __e14, __e15,
+ __e16, __e17, __e18, __e19, __e20, __e21, __e22, __e23,
+ __e24, __e25, __e26, __e27, __e28, __e29, __e30, __e31,
+ __e32, __e33, __e34, __e35, __e36, __e37, __e38, __e39,
+ __e40, __e41, __e42, __e43, __e44, __e45, __e46, __e47,
+ __e48, __e49, __e50, __e51, __e52, __e53, __e54, __e55,
+ __e56, __e57, __e58, __e59, __e60, __e61, __e62, __e63};
+}
+
+static __inline __m512i __DEFAULT_FN_ATTRS
+_mm512_set_epi16(short __e31, short __e30, short __e29, short __e28,
+short __e27, short __e26, short __e25, short __e24, short __e23,
+short __e22, short __e21, short __e20, short __e19, short __e18,
+short __e17, short __e16, short __e15, short __e14, short __e13,
+short __e12, short __e11, short __e10, short __e9, short __e8,
+short __e7, short __e6, short __e5, short __e4, short __e3,
+short __e2, short __e1, short __e0) {
+ return __extension__ (__m512i)(__v32hi)
+{__e0, __e1, __e2, __e3, __e4, __e5, __e6, __e7,
+ __e8, __e9, __e10, __e11, __e12, __e13, __e14, __e15,
+ __e16, __e17, __e18, __e19, __e20, __e21, __e22, __e23,
+ __e24, __e25, __e26, __e27, __e28, __e29, __e30, __e31 };
+}
+
static __inline __m512i __DEFAULT_FN_ATTRS
_mm512_set_epi32 (int __A, int __B, int __C, int __D,
int __E, int __F, int __G, int __H,
Modified: cfe/trunk/test/CodeGen/avx512f-builtins.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx512f-builtins.c?rev=298208&r1=298207&r2=298208&view=diff
==
--- cfe/trunk/test/CodeGen/avx512f-builtins.c (original)
+++ cfe/trunk/test/CodeGen/avx512f-builtins.c Sun Mar 19 03:27:16 2017
@@ -7712,6 +7712,133 @@ __m512i test_mm512_mask_set1_epi32 (__m5
return _mm512_mask_set1_epi32 ( __O, __M, __A);
}
+__m512i test_mm512_set_epi8(char e63, char e62, char e61, char e60, char e59,
+char e58, char e57, char e56, char e55, char e54, char e53, char e52,
+char e51, char e50, char e49, char e48, char e47, char e46, char e45,
+char e44, char e43, char e42, char e41, char e40, char e39, char e38,
+char e37, char e36, char e35, char e34, char e33, char e32, char e31,
+char e30, char e29, char e28, char e27, char e26, char e25, char e24,
+char e23, char e22, char e21, char e20, char e19, char e18, ch
[PATCH] D26021: [X86][AVX512][Clang] Add support for mask_{move|store|load}_s{s/d} and int2mask/mask2int intrinsics.
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM Comment at: lib/Headers/avx512fintrin.h:9123 + __m128 res=__A; + res[0] = (__U&1)? __B[0]:__W[0]; + return res; . Comment at: lib/Headers/avx512fintrin.h:9155 + __builtin_ia32_storess128_mask ((__v16sf *)__W, +(__v16sf) _mm512_castps128_ps512(__A), +(__mmask16) __U & (__mmask16)1); . https://reviews.llvm.org/D26021 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D24961: [avx512] Add aliases to some missing avx512 intrinsics.
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D24961 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D24785: [AVX512] Fix return types on __builtin_ia32_gather3XivXdi builtins
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D24785 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D23753: [AVX512] Arguments to _mm512_[mask_]abs_ps|d must have "__" prefix
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D23753 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21836: [AVX512][BUILTIN][vpermilps][intrinsics] Fixing two incorrect IMM check.
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM http://reviews.llvm.org/D21836 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r274110 - [AVX512] Zero extend cmp intrinsic return value.
Author: ibreger
Date: Wed Jun 29 03:14:17 2016
New Revision: 274110
URL: http://llvm.org/viewvc/llvm-project?rev=274110&view=rev
Log:
[AVX512] Zero extend cmp intrinsic return value.
Differential Revision: http://reviews.llvm.org/D21746
Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/CodeGen/avx512vl-builtins.c
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=274110&r1=274109&r2=274110&view=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Wed Jun 29 03:14:17 2016
@@ -6460,8 +6460,8 @@ static Value *EmitX86MaskedCompare(CodeG
Indices[i] = i;
for (unsigned i = NumElts; i != 8; ++i)
Indices[i] = NumElts;
-Cmp = CGF.Builder.CreateShuffleVector(Cmp, UndefValue::get(Cmp->getType()),
- Indices);
+Cmp = CGF.Builder.CreateShuffleVector(
+Cmp, llvm::Constant::getNullValue(Cmp->getType()), Indices);
}
return CGF.Builder.CreateBitCast(Cmp,
IntegerType::get(CGF.getLLVMContext(),
Modified: cfe/trunk/test/CodeGen/avx512vl-builtins.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx512vl-builtins.c?rev=274110&r1=274109&r2=274110&view=diff
==
--- cfe/trunk/test/CodeGen/avx512vl-builtins.c (original)
+++ cfe/trunk/test/CodeGen/avx512vl-builtins.c Wed Jun 29 03:14:17 2016
@@ -8,6 +8,7 @@
__mmask8 test_mm_cmpeq_epu32_mask(__m128i __a, __m128i __b) {
// CHECK-LABEL: @test_mm_cmpeq_epu32_mask
// CHECK: icmp eq <4 x i32> %{{.*}}, %{{.*}}
+ // CHECK: shufflevector <4 x i1> %{{.*}}, <4 x i1> zeroinitializer, <8 x
i32>
return (__mmask8)_mm_cmpeq_epu32_mask(__a, __b);
}
___
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[PATCH] D21746: [AVX512] Zero extend cmp intrinsic return value.
igorb created this revision.
igorb added reviewers: delena, craig.topper.
igorb added a subscriber: cfe-commits.
igorb set the repository for this revision to rL LLVM.
[AVX512] Zero extend cmp intrinsic return value.
Repository:
rL LLVM
http://reviews.llvm.org/D21746
Files:
lib/CodeGen/CGBuiltin.cpp
test/CodeGen/avx512vl-builtins.c
Index: test/CodeGen/avx512vl-builtins.c
===
--- test/CodeGen/avx512vl-builtins.c
+++ test/CodeGen/avx512vl-builtins.c
@@ -8,6 +8,7 @@
__mmask8 test_mm_cmpeq_epu32_mask(__m128i __a, __m128i __b) {
// CHECK-LABEL: @test_mm_cmpeq_epu32_mask
// CHECK: icmp eq <4 x i32> %{{.*}}, %{{.*}}
+ // CHECK: shufflevector <4 x i1> %{{.*}}, <4 x i1> zeroinitializer, <8 x
i32>
return (__mmask8)_mm_cmpeq_epu32_mask(__a, __b);
}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -6456,8 +6456,10 @@
Indices[i] = i;
for (unsigned i = NumElts; i != 8; ++i)
Indices[i] = NumElts;
-Cmp = CGF.Builder.CreateShuffleVector(Cmp, UndefValue::get(Cmp->getType()),
- Indices);
+Cmp = CGF.Builder.CreateShuffleVector(
+Cmp,
+llvm::Constant::getNullValue(Cmp->getType()),
+Indices);
}
return CGF.Builder.CreateBitCast(Cmp,
IntegerType::get(CGF.getLLVMContext(),
Index: test/CodeGen/avx512vl-builtins.c
===
--- test/CodeGen/avx512vl-builtins.c
+++ test/CodeGen/avx512vl-builtins.c
@@ -8,6 +8,7 @@
__mmask8 test_mm_cmpeq_epu32_mask(__m128i __a, __m128i __b) {
// CHECK-LABEL: @test_mm_cmpeq_epu32_mask
// CHECK: icmp eq <4 x i32> %{{.*}}, %{{.*}}
+ // CHECK: shufflevector <4 x i1> %{{.*}}, <4 x i1> zeroinitializer, <8 x i32>
return (__mmask8)_mm_cmpeq_epu32_mask(__a, __b);
}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -6456,8 +6456,10 @@
Indices[i] = i;
for (unsigned i = NumElts; i != 8; ++i)
Indices[i] = NumElts;
-Cmp = CGF.Builder.CreateShuffleVector(Cmp, UndefValue::get(Cmp->getType()),
- Indices);
+Cmp = CGF.Builder.CreateShuffleVector(
+Cmp,
+llvm::Constant::getNullValue(Cmp->getType()),
+Indices);
}
return CGF.Builder.CreateBitCast(Cmp,
IntegerType::get(CGF.getLLVMContext(),
___
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Re: [PATCH] D21734: [Intrinsics][AVX512][BuiltIn] adding intrinsics for vrangesd instruction set
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM http://reviews.llvm.org/D21734 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21322: [Clang][avx512][Intrinsics] adding prefetch gather intrinsics
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM http://reviews.llvm.org/D21322 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r272141 - [AVX512] Emit select instruction instead of using x86 specific instrinsics.
Author: ibreger Date: Wed Jun 8 08:59:20 2016 New Revision: 272141 URL: http://llvm.org/viewvc/llvm-project?rev=272141&view=rev Log: [AVX512] Emit select instruction instead of using x86 specific instrinsics. This will allow us to remove the x86 instrinics from the backend. Differential Revision: http://reviews.llvm.org/D21060 Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def cfe/trunk/lib/CodeGen/CGBuiltin.cpp cfe/trunk/lib/Headers/avx512bwintrin.h cfe/trunk/lib/Headers/avx512fintrin.h cfe/trunk/lib/Headers/avx512vlbwintrin.h cfe/trunk/lib/Headers/avx512vlintrin.h cfe/trunk/test/CodeGen/avx512bw-builtins.c cfe/trunk/test/CodeGen/avx512f-builtins.c cfe/trunk/test/CodeGen/avx512vl-builtins.c cfe/trunk/test/CodeGen/avx512vlbw-builtins.c Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=272141&r1=272140&r2=272141&view=diff == --- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original) +++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Wed Jun 8 08:59:20 2016 @@ -1002,10 +1002,6 @@ TARGET_BUILTIN(__builtin_ia32_pminud512_ TARGET_BUILTIN(__builtin_ia32_pminuq512_mask, "V8LLiV8LLiV8LLiV8LLiUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_pmuldq512_mask, "V8LLiV16iV16iV8LLiUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_pmuludq512_mask, "V8LLiV16iV16iV8LLiUc", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_blendmd_512_mask, "V16iV16iV16iUs", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_blendmq_512_mask, "V8LLiV8LLiV8LLiUc", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_blendmps_512_mask, "V16fV16fV16fUs", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_blendmpd_512_mask, "V8dV8dV8dUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_ptestmd512, "UsV16iV16iUs", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_ptestmq512, "UcV8LLiV8LLiUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_pbroadcastd512, "V16iV4iV16iUs","","avx512f") @@ -1190,8 +1186,6 @@ TARGET_BUILTIN(__builtin_ia32_orpd128_ma TARGET_BUILTIN(__builtin_ia32_orps256_mask, "V8fV8fV8fV8fUc", "", "avx512vl,avx512dq") TARGET_BUILTIN(__builtin_ia32_orps128_mask, "V4fV4fV4fV4fUc", "", "avx512vl,avx512dq") -TARGET_BUILTIN(__builtin_ia32_blendmb_512_mask, "V64cV64cV64cULLi", "", "avx512bw") -TARGET_BUILTIN(__builtin_ia32_blendmw_512_mask, "V32sV32sV32sUi", "", "avx512bw") TARGET_BUILTIN(__builtin_ia32_pabsb512_mask, "V64cV64cV64cULLi", "", "avx512bw") TARGET_BUILTIN(__builtin_ia32_pabsw512_mask, "V32sV32sV32sUi", "", "avx512bw") TARGET_BUILTIN(__builtin_ia32_packssdw512_mask, "V32sV16iV16iV32sUi", "", "avx512bw") @@ -1231,10 +1225,6 @@ TARGET_BUILTIN(__builtin_ia32_vpconflict TARGET_BUILTIN(__builtin_ia32_vplzcntd_512_mask, "V16iV16iV16iUs", "", "avx512cd") TARGET_BUILTIN(__builtin_ia32_vplzcntq_512_mask, "V8LLiV8LLiV8LLiUc", "", "avx512cd") -TARGET_BUILTIN(__builtin_ia32_blendmb_128_mask, "V16cV16cV16cUs", "", "avx512vl,avx512bw") -TARGET_BUILTIN(__builtin_ia32_blendmb_256_mask, "V32cV32cV32cUi", "", "avx512vl,avx512bw") -TARGET_BUILTIN(__builtin_ia32_blendmw_128_mask, "V8sV8sV8sUc", "", "avx512vl,avx512bw") -TARGET_BUILTIN(__builtin_ia32_blendmw_256_mask, "V16sV16sV16sUs", "", "avx512vl,avx512bw") TARGET_BUILTIN(__builtin_ia32_pabsb128_mask, "V16cV16cV16cUs", "", "avx512vl,avx512bw") TARGET_BUILTIN(__builtin_ia32_pabsb256_mask, "V32cV32cV32cUi", "", "avx512vl,avx512bw") TARGET_BUILTIN(__builtin_ia32_pabsw128_mask, "V8sV8sV8sUc", "", "avx512vl,avx512bw") @@ -1326,14 +1316,6 @@ TARGET_BUILTIN(__builtin_ia32_addpd128_m TARGET_BUILTIN(__builtin_ia32_addpd256_mask, "V4dV4dV4dV4dUc", "", "avx512vl") TARGET_BUILTIN(__builtin_ia32_addps128_mask, "V4fV4fV4fV4fUc", "", "avx512vl") TARGET_BUILTIN(__builtin_ia32_addps256_mask, "V8fV8fV8fV8fUc", "", "avx512vl") -TARGET_BUILTIN(__builtin_ia32_blendmd_128_mask, "V4iV4iV4iUc", "", "avx512vl") -TARGET_BUILTIN(__builtin_ia32_blendmd_256_mask, "V8iV8iV8iUc", "", "avx512vl") -TARGET_BUILTIN(__builtin_ia32_blendmpd_128_mask, "V2dV2dV2dUc", "", "avx512vl") -TARGET_BUILTIN(__builtin_ia32_blendmpd_256_mask, "V4dV4dV4dUc", "", "avx512vl") -TARGET_BUILTIN(__builtin_ia32_blendmps_128_mask, "V4fV4fV4fUc", "", "avx512vl") -TARGET_BUILTIN(__builtin_ia32_blendmps_256_mask, "V8fV8fV8fUc", "", "avx512vl") -TARGET_BUILTIN(__builtin_ia32_blendmq_128_mask, "V2LLiV2LLiV2LLiUc", "", "avx512vl") -TARGET_BUILTIN(__builtin_ia32_blendmq_256_mask, "V4LLiV4LLiV4LLiUc", "", "avx512vl") TARGET_BUILTIN(__builtin_ia32_compressdf128_mask, "V2dV2dV2dUc", "", "avx512vl") TARGET_BUILTIN(__builtin_ia32_compressdf256_mask, "V4dV4dV4dUc", "", "avx512vl") TARGET_BUILTIN(__builtin_ia32_compressdi128_mask, "V2LLiV2LLiV2LLiUc", "", "avx512vl") @@ -1700,30 +1682,18 @@ TARGET_BUILTIN(__builtin_ia32_psrlw128_m TARGET_BUILTIN(__builtin_ia32_psrlw256_mask, "V16sV16sV8sV16sUs","","avx512bw,avx512vl") T
Re: [PATCH] D21058: [Clang][AVX512][BUILTIN]Adding missing intrinsics srl and sll
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM http://reviews.llvm.org/D21058 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D21060: [AVX512] Emit select instruction instead of using x86 specific instrinsics.
igorb created this revision.
igorb added reviewers: craig.topper, delena.
igorb added a subscriber: cfe-commits.
igorb set the repository for this revision to rL LLVM.
[AVX512] Emit select instruction instead of using x86 specific instrinsics.
This will allow us to remove the x86 instrinics from the backend.
Repository:
rL LLVM
http://reviews.llvm.org/D21060
Files:
include/clang/Basic/BuiltinsX86.def
lib/CodeGen/CGBuiltin.cpp
lib/Headers/avx512bwintrin.h
lib/Headers/avx512fintrin.h
lib/Headers/avx512vlbwintrin.h
lib/Headers/avx512vlintrin.h
test/CodeGen/avx512bw-builtins.c
test/CodeGen/avx512f-builtins.c
test/CodeGen/avx512vl-builtins.c
test/CodeGen/avx512vlbw-builtins.c
Index: test/CodeGen/avx512vlbw-builtins.c
===
--- test/CodeGen/avx512vlbw-builtins.c
+++ test/CodeGen/avx512vlbw-builtins.c
@@ -800,24 +800,24 @@
__m128i test_mm_mask_blend_epi8(__mmask16 __U, __m128i __A, __m128i __W) {
// CHECK-LABEL: @test_mm_mask_blend_epi8
- // CHECK: @llvm.x86.avx512.mask.blend.b.128
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}
return _mm_mask_blend_epi8(__U,__A,__W);
}
__m256i test_mm256_mask_blend_epi8(__mmask32 __U, __m256i __A, __m256i __W) {
// CHECK-LABEL: @test_mm256_mask_blend_epi8
- // CHECK: @llvm.x86.avx512.mask.blend.b.256
+ // CHECK: select <32 x i1> %{{.*}}, <32 x i8> %{{.*}}, <32 x i8> %{{.*}}
return _mm256_mask_blend_epi8(__U,__A,__W);
}
__m128i test_mm_mask_blend_epi16(__mmask8 __U, __m128i __A, __m128i __W) {
// CHECK-LABEL: @test_mm_mask_blend_epi16
- // CHECK: @llvm.x86.avx512.mask.blend.w.128
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_mask_blend_epi16(__U,__A,__W);
}
__m256i test_mm256_mask_blend_epi16(__mmask16 __U, __m256i __A, __m256i __W) {
// CHECK-LABEL: @test_mm256_mask_blend_epi16
- // CHECK: @llvm.x86.avx512.mask.blend.w.256
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_mask_blend_epi16(__U,__A,__W);
}
@@ -1959,49 +1959,49 @@
__m128i test_mm_mask_mov_epi16(__m128i __W, __mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_mask_mov_epi16
- // CHECK: @llvm.x86.avx512.mask.movu.w.128
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_mask_mov_epi16(__W, __U, __A);
}
__m128i test_mm_maskz_mov_epi16(__mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_maskz_mov_epi16
- // CHECK: @llvm.x86.avx512.mask.movu.w.128
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
return _mm_maskz_mov_epi16(__U, __A);
}
__m256i test_mm256_mask_mov_epi16(__m256i __W, __mmask16 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_mask_mov_epi16
- // CHECK: @llvm.x86.avx512.mask.movu.w.256
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_mask_mov_epi16(__W, __U, __A);
}
__m256i test_mm256_maskz_mov_epi16(__mmask16 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_maskz_mov_epi16
- // CHECK: @llvm.x86.avx512.mask.movu.w.256
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
return _mm256_maskz_mov_epi16(__U, __A);
}
__m128i test_mm_mask_mov_epi8(__m128i __W, __mmask16 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_mask_mov_epi8
- // CHECK: @llvm.x86.avx512.mask.movu.b.128
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}
return _mm_mask_mov_epi8(__W, __U, __A);
}
__m128i test_mm_maskz_mov_epi8(__mmask16 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_maskz_mov_epi8
- // CHECK: @llvm.x86.avx512.mask.movu.b.128
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}
return _mm_maskz_mov_epi8(__U, __A);
}
__m256i test_mm256_mask_mov_epi8(__m256i __W, __mmask32 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_mask_mov_epi8
- // CHECK: @llvm.x86.avx512.mask.movu.b.256
+ // CHECK: select <32 x i1> %{{.*}}, <32 x i8> %{{.*}}, <32 x i8> %{{.*}}
return _mm256_mask_mov_epi8(__W, __U, __A);
}
__m256i test_mm256_maskz_mov_epi8(__mmask32 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_maskz_mov_epi8
- // CHECK: @llvm.x86.avx512.mask.movu.b.256
+ // CHECK: select <32 x i1> %{{.*}}, <32 x i8> %{{.*}}, <32 x i8> %{{.*}}
return _mm256_maskz_mov_epi8(__U, __A);
}
Index: test/CodeGen/avx512vl-builtins.c
===
--- test/CodeGen/avx512vl-builtins.c
+++ test/CodeGen/avx512vl-builtins.c
@@ -1467,42 +1467,42 @@
}
__m128i test_mm_mask_blend_epi32(__mmask8 __U, __m128i __A, __m128i __W) {
// CHECK-LABEL: @test_mm_mask_blend_epi32
- // CHECK: @llvm.x86.avx512.mask.blend.d.128
+ // CHECK: select <4 x i1> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}
return _mm_mask_blend_epi32(__U,__A,__W);
}
__m256i test_mm256_mask_blend_epi32(__mmask8 __U, __m256i __A, _
Re: [PATCH] D20861: [AVX512] add missing integer to float conversion
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM http://reviews.llvm.org/D20861 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20620: [Clang][AVX512][Builtin] Fix palignr intrinsics header
igorb accepted this revision. igorb added a comment. This revision is now accepted and ready to land. LGTM http://reviews.llvm.org/D20620 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20321: [Clang][AVX512][intrinsics] Fix vperm intrinsics.
igorb added a comment. In http://reviews.llvm.org/D20321#436494, @craig.topper wrote: > Looking at this again. This doesn't match the gcc implementation of the > builtins. Unless their header file is also wrong. Can you clarify? Thanks, You are correct. I implemented all changes in code-gen ( http://reviews.llvm.org/D20515 ). If there's no objection, I abandon this review. Repository: rL LLVM http://reviews.llvm.org/D20321 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20321: [Clang][AVX512][intrinsics] Fix vperm intrinsics.
igorb updated this revision to Diff 58055.
igorb added a comment.
Update path according to comments.
Thanks for review, Craig !
Repository:
rL LLVM
http://reviews.llvm.org/D20321
Files:
include/clang/Basic/BuiltinsX86.def
lib/Headers/avx512bwintrin.h
lib/Headers/avx512fintrin.h
lib/Headers/avx512vlbwintrin.h
lib/Headers/avx512vlintrin.h
Index: lib/Headers/avx512vlintrin.h
===
--- lib/Headers/avx512vlintrin.h
+++ lib/Headers/avx512vlintrin.h
@@ -8940,111 +8940,111 @@
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_permutexvar_pd (__m256i __X, __m256d __Y)
{
- return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __Y,
- (__v4di) __X,
+ return (__m256d) __builtin_ia32_permvardf256_mask ((__v4di) __X /* idx */,
+ (__v4df) __Y,
(__v4df) _mm256_undefined_si256 (),
(__mmask8) -1);
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_mask_permutexvar_pd (__m256d __W, __mmask8 __U, __m256i __X,
__m256d __Y)
{
- return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __Y,
- (__v4di) __X,
+ return (__m256d) __builtin_ia32_permvardf256_mask ((__v4di) __X /* idx */,
+ (__v4df) __Y,
(__v4df) __W,
(__mmask8) __U);
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_maskz_permutexvar_pd (__mmask8 __U, __m256i __X, __m256d __Y)
{
- return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __Y,
- (__v4di) __X,
+ return (__m256d) __builtin_ia32_permvardf256_mask ((__v4di) __X /* idx */,
+ (__v4df) __Y,
(__v4df) _mm256_setzero_pd (),
(__mmask8) __U);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_maskz_permutexvar_epi64 (__mmask8 __M, __m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __Y,
- (__v4di) __X,
+ return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __X /* idx */,
+ (__v4di) __Y,
(__v4di) _mm256_setzero_si256 (),
(__mmask8) __M);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_permutexvar_epi64 (__mmask8 __M, __m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __Y,
- (__v4di) __X,
+ return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __X /* idx */,
+ (__v4di) __Y,
(__v4di) _mm256_undefined_si256 (),
(__mmask8) -1);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_mask_permutexvar_epi64 (__m256i __W, __mmask8 __M, __m256i __X,
__m256i __Y)
{
- return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __Y,
- (__v4di) __X,
+ return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __X /* idx */,
+ (__v4di) __Y,
(__v4di) __W,
__M);
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_mask_permutexvar_ps (__m256 __W, __mmask8 __U, __m256i __X,
__m256 __Y)
{
- return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __Y,
-(__v8si) __X,
+ return (__m256) __builtin_ia32_permvarsf256_mask ((__v8si) __X /* idx */,
+(__v8sf) __Y,
(__v8sf) __W,
(__mmask8) __U);
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_maskz_permutexvar_ps (__mmask8 __U, __m256i __X, __m256 __Y)
{
- return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __Y,
-(__v8si) __X,
+ return (__m256) __builtin_ia32_permvarsf256_mask ((__v8si) __X /* idx */,
+(__v8sf) __Y,
(__v8sf) _mm256_setzero_ps (),
(__mmask8) __U);
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_permutexvar_ps (__m256i __X, __m256 __Y)
{
- return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __Y,
-(__v8si) __X,
+ return (__m256) __builtin_ia32_permvarsf256_mask ((__v8si) __X /* idx */,
+(__v8sf) __Y,
(__v8sf) _mm256_undefined_si256 (),
(__mmask8) -1);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_maskz_permutexvar_epi32 (__mmask8 __M, __m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_permvarsi256_mask ((__v8si) __Y,
- (__v8si) __X,
+ return (__m256i) __builtin_ia32_permvarsi256_mask ((__v8si) __X /* idx */,
+ (__v8si) __Y,
(__v8si) _mm256_setzero_si256 (),
__M);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_mask_permutexvar_epi32 (__m256i __W, __mmask8 __M, __m256i __X,
__m256i __Y)
{
- return (__m256i) __builtin_ia32_permvarsi256_mask ((__v8si) __Y,
- (__v8si) __X,
+ return (__m256i) __builtin_ia32_permvarsi256_mask ((__v8s
[PATCH] D20321: [Clang][AVX512][intrinsics] Fix vperm intrinsics.
igorb created this revision.
igorb added reviewers: m_zuckerman, AsafBadouh, delena.
igorb added a subscriber: cfe-commits.
igorb set the repository for this revision to rL LLVM.
[Clang][AVX512][intrinsics] Fix vperm{w|d|q|ps|pd} intrinsics. Index is first
argument to buildin function.
Repository:
rL LLVM
http://reviews.llvm.org/D20321
Files:
lib/Headers/avx512bwintrin.h
lib/Headers/avx512fintrin.h
lib/Headers/avx512vlbwintrin.h
lib/Headers/avx512vlintrin.h
Index: lib/Headers/avx512vlintrin.h
===
--- lib/Headers/avx512vlintrin.h
+++ lib/Headers/avx512vlintrin.h
@@ -9100,111 +9100,111 @@
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_permutexvar_pd (__m256i __X, __m256d __Y)
{
- return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __Y,
- (__v4di) __X,
+ return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __X /* idx */,
+ (__v4di) __Y,
(__v4df) _mm256_undefined_si256 (),
(__mmask8) -1);
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_mask_permutexvar_pd (__m256d __W, __mmask8 __U, __m256i __X,
__m256d __Y)
{
- return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __Y,
- (__v4di) __X,
+ return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __X /* idx */,
+ (__v4di) __Y,
(__v4df) __W,
(__mmask8) __U);
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_maskz_permutexvar_pd (__mmask8 __U, __m256i __X, __m256d __Y)
{
- return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __Y,
- (__v4di) __X,
+ return (__m256d) __builtin_ia32_permvardf256_mask ((__v4df) __X /* idx */,
+ (__v4di) __Y,
(__v4df) _mm256_setzero_pd (),
(__mmask8) __U);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_maskz_permutexvar_epi64 (__mmask8 __M, __m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __Y,
- (__v4di) __X,
+ return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __X /* idx */,
+ (__v4di) __Y,
(__v4di) _mm256_setzero_si256 (),
(__mmask8) __M);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_permutexvar_epi64 (__mmask8 __M, __m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __Y,
- (__v4di) __X,
+ return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __X /* idx */,
+ (__v4di) __Y,
(__v4di) _mm256_undefined_si256 (),
(__mmask8) -1);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_mask_permutexvar_epi64 (__m256i __W, __mmask8 __M, __m256i __X,
__m256i __Y)
{
- return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __Y,
- (__v4di) __X,
+ return (__m256i) __builtin_ia32_permvardi256_mask ((__v4di) __X /* idx */,
+ (__v4di) __Y,
(__v4di) __W,
__M);
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_mask_permutexvar_ps (__m256 __W, __mmask8 __U, __m256i __X,
__m256 __Y)
{
- return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __Y,
-(__v8si) __X,
+ return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __X /* idx */,
+(__v8si) __Y,
(__v8sf) __W,
(__mmask8) __U);
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_maskz_permutexvar_ps (__mmask8 __U, __m256i __X, __m256 __Y)
{
- return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __Y,
-(__v8si) __X,
+ return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __X /* idx */,
+(__v8si) __Y,
(__v8sf) _mm256_setzero_ps (),
(__mmask8) __U);
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_permutexvar_ps (__m256i __X, __m256 __Y)
{
- return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __Y,
-(__v8si) __X,
+ return (__m256) __builtin_ia32_permvarsf256_mask ((__v8sf) __X /* idx */,
+(__v8si) __Y,
(__v8sf) _mm256_undefined_si256 (),
(__mmask8) -1);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_maskz_permutexvar_epi32 (__mmask8 __M, __m256i __X, __m256i __Y)
{
- return (__m256i) __builtin_ia32_permvarsi256_mask ((__v8si) __Y,
- (__v8si) __X,
+ return (__m256i) __builtin_ia32_permvarsi256_mask ((__v8si) __X /* idx */,
+ (__v8si) __Y,
(__v8si) _mm256_setzero_si256 (),
__M);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_mask_permutexvar_epi32 (__m256i __W, __mmask8 __M, __m256i __X,
__m256i __Y)
{
- return (__m256i) __builtin_ia32_pe
r260088 - AVX512: Change builtin function name for scalar intrinsics. Add "mask" to function name to reflect the function behavior.
Author: ibreger Date: Mon Feb 8 06:36:48 2016 New Revision: 260088 URL: http://llvm.org/viewvc/llvm-project?rev=260088&view=rev Log: AVX512: Change builtin function name for scalar intrinsics. Add "mask" to function name to reflect the function behavior. Differential Revision: http://reviews.llvm.org/D16957 Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def cfe/trunk/lib/Headers/avx512erintrin.h cfe/trunk/lib/Headers/avx512fintrin.h Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=260088&r1=260087&r2=260088&view=diff == --- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original) +++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Mon Feb 8 06:36:48 2016 @@ -931,23 +931,23 @@ TARGET_BUILTIN(__builtin_ia32_wrpkru, "v // AVX-512 TARGET_BUILTIN(__builtin_ia32_sqrtpd512_mask, "V8dV8dV8dUcIi", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_sqrtps512_mask, "V16fV16fV16fUsIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_rsqrt14sd, "V2dV2dV2dV2dUc", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_rsqrt14ss, "V4fV4fV4fV4fUc", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_rsqrt14sd_mask, "V2dV2dV2dV2dUc", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_rsqrt14ss_mask, "V4fV4fV4fV4fUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_rsqrt14pd512_mask, "V8dV8dV8dUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_rsqrt14ps512_mask, "V16fV16fV16fUs", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_rsqrt28sd_round, "V2dV2dV2dV2dUcIi", "", "avx512er") -TARGET_BUILTIN(__builtin_ia32_rsqrt28ss_round, "V4fV4fV4fV4fUcIi", "", "avx512er") +TARGET_BUILTIN(__builtin_ia32_rsqrt28sd_round_mask, "V2dV2dV2dV2dUcIi", "", "avx512er") +TARGET_BUILTIN(__builtin_ia32_rsqrt28ss_round_mask, "V4fV4fV4fV4fUcIi", "", "avx512er") TARGET_BUILTIN(__builtin_ia32_rsqrt28pd_mask, "V8dV8dV8dUcIi", "", "avx512er") TARGET_BUILTIN(__builtin_ia32_rsqrt28ps_mask, "V16fV16fV16fUsIi", "", "avx512er") -TARGET_BUILTIN(__builtin_ia32_rcp14sd, "V2dV2dV2dV2dUc", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_rcp14ss, "V4fV4fV4fV4fUc", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_rcp14sd_mask, "V2dV2dV2dV2dUc", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_rcp14ss_mask, "V4fV4fV4fV4fUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_rcp14pd512_mask, "V8dV8dV8dUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_rcp14ps512_mask, "V16fV16fV16fUs", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_rcp28sd_round, "V2dV2dV2dV2dUcIi", "", "avx512er") -TARGET_BUILTIN(__builtin_ia32_rcp28ss_round, "V4fV4fV4fV4fUcIi", "", "avx512er") +TARGET_BUILTIN(__builtin_ia32_rcp28sd_round_mask, "V2dV2dV2dV2dUcIi", "", "avx512er") +TARGET_BUILTIN(__builtin_ia32_rcp28ss_round_mask, "V4fV4fV4fV4fUcIi", "", "avx512er") TARGET_BUILTIN(__builtin_ia32_rcp28pd_mask, "V8dV8dV8dUcIi", "", "avx512er") TARGET_BUILTIN(__builtin_ia32_rcp28ps_mask, "V16fV16fV16fUsIi", "", "avx512er") TARGET_BUILTIN(__builtin_ia32_exp2pd_mask, "V8dV8dV8dUcIi", "", "avx512er") @@ -1310,18 +1310,18 @@ TARGET_BUILTIN(__builtin_ia32_subps512_m TARGET_BUILTIN(__builtin_ia32_pmaddubsw512_mask, "V32sV64cV64cV32sUi", "", "avx512bw") TARGET_BUILTIN(__builtin_ia32_pmaddwd512_mask, "V16iV32sV32sV16iUs", "", "avx512bw") -TARGET_BUILTIN(__builtin_ia32_addss_round, "V4fV4fV4fV4fUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_divss_round, "V4fV4fV4fV4fUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_mulss_round, "V4fV4fV4fV4fUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_subss_round, "V4fV4fV4fV4fUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_maxss_round, "V4fV4fV4fV4fUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_minss_round, "V4fV4fV4fV4fUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_addsd_round, "V2dV2dV2dV2dUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_divsd_round, "V2dV2dV2dV2dUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_mulsd_round, "V2dV2dV2dV2dUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_subsd_round, "V2dV2dV2dV2dUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_maxsd_round, "V2dV2dV2dV2dUcIi", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_minsd_round, "V2dV2dV2dV2dUcIi", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_addss_round_mask, "V4fV4fV4fV4fUcIi", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_divss_round_mask, "V4fV4fV4fV4fUcIi", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_mulss_round_mask, "V4fV4fV4fV4fUcIi", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_subss_round_mask, "V4fV4fV4fV4fUcIi", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_maxss_round_mask, "V4fV4fV4fV4fUcIi", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_minss_round_mask, "V4fV4fV4fV4fUcIi", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_addsd_round_mask, "V2dV2dV2dV2dUcIi", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_divsd_round_mask, "V2dV2dV2dV2dUcIi", "", "avx512f"
r247277 - AVX-512: Changed nidx parameter in extractf64/32 intrinsic from i8 to i32 according to the Intel Spec
Author: ibreger Date: Thu Sep 10 07:55:54 2015 New Revision: 247277 URL: http://llvm.org/viewvc/llvm-project?rev=247277&view=rev Log: AVX-512: Changed nidx parameter in extractf64/32 intrinsic from i8 to i32 according to the Intel Spec Differential Revision: http://reviews.llvm.org/D12752 Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=247277&r1=247276&r2=247277&view=diff == --- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original) +++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Thu Sep 10 07:55:54 2015 @@ -1032,8 +1032,8 @@ TARGET_BUILTIN(__builtin_ia32_vpermt2var TARGET_BUILTIN(__builtin_ia32_vpermt2varpd512_mask, "V8dV8LLiV8dV8dUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_alignq512_mask, "V8LLiV8LLiV8LLiIiV8LLiUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_alignd512_mask, "V16iV16iV16iIiV16iUs", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_extractf64x4_mask, "V4dV8dIcV4dUc", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_extractf32x4_mask, "V4fV16fIcV4fUc", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_extractf64x4_mask, "V4dV8dIiV4dUc", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_extractf32x4_mask, "V4fV16fIiV4fUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_gathersiv8df, "V8dV8dvC*V8iUcIi", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_gathersiv16sf, "V16fV16fvC*UsIi", "", "avx512f") ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r246430 - AVX-512: Changed cnt parameter in valignq/d intrinsic from i8 to i32 according to the Intel Spec
Author: ibreger Date: Mon Aug 31 06:15:06 2015 New Revision: 246430 URL: http://llvm.org/viewvc/llvm-project?rev=246430&view=rev Log: AVX-512: Changed cnt parameter in valignq/d intrinsic from i8 to i32 according to the Intel Spec Differential Revision: http://reviews.llvm.org/D12274 Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=246430&r1=246429&r2=246430&view=diff == --- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original) +++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Mon Aug 31 06:15:06 2015 @@ -1030,8 +1030,8 @@ TARGET_BUILTIN(__builtin_ia32_vpermt2var TARGET_BUILTIN(__builtin_ia32_vpermt2varq512_mask, "V8LLiV8LLiV8LLiV8LLiUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_vpermt2varps512_mask, "V16fV16iV16fV16fUs", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_vpermt2varpd512_mask, "V8dV8LLiV8dV8dUc", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_alignq512_mask, "V8LLiV8LLiV8LLiIcV8LLiUc", "", "avx512f") -TARGET_BUILTIN(__builtin_ia32_alignd512_mask, "V16iV16iV16iIcV16iUs", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_alignq512_mask, "V8LLiV8LLiV8LLiIiV8LLiUc", "", "avx512f") +TARGET_BUILTIN(__builtin_ia32_alignd512_mask, "V16iV16iV16iIiV16iUs", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_extractf64x4_mask, "V4dV8dIcV4dUc", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_extractf32x4_mask, "V4fV16fIcV4fUc", "", "avx512f") ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
