Re: [PATCH v4 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Thanks for your review.
These are fixed in v5 as following link.
https://lore.kernel.org/patchwork/patch/1372271/
Nick Fan
On Thu, 2021-01-14 at 14:14 -0600, Rob Herring wrote:
> On Tue, Jan 12, 2021 at 02:49:32PM +0800, Nick Fan wrote:
> > Add devicetree schema for Arm Mali Valhall GPU
> >
> > Define a compatible string for the Mali Valhall GPU
> > for Mediatek's SoC platform.
> >
> > Signed-off-by: Nick Fan
> > ---
> > .../bindings/gpu/arm,mali-valhall.yaml| 252 ++
> > 1 file changed, 252 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > new file mode 100644
> > index ..ecf249a58435
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > @@ -0,0 +1,252 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: ARM Mali Valhall GPU
> > +
> > +maintainers:
> > + - Rob Herring
> > +
> > +properties:
> > + $nodename:
> > +pattern: '^gpu@[a-f0-9]+$'
> > +
> > + compatible:
> > +items:
> > + - enum:
> > + - mediatek,mt8192-mali
> > + - const: arm,mali-valhall
> > +
> > + reg:
> > +maxItems: 1
> > +
> > + interrupts:
> > +items:
> > + - description: GPU interrupt
> > + - description: MMU interrupt
> > + - description: Job interrupt
> > +
> > + interrupt-names:
> > +items:
> > + - const: gpu
> > + - const: mmu
> > + - const: job
> > +
> > + clocks:
> > +minItems: 1
> > +
> > + power-domains:
> > +minItems: 1
> > +maxItems: 5
> > +
> > + mali-supply: true
> > + sram-supply: true
> > +
> > + operating-points-v2: true
> > +
> > + "#cooling-cells":
> > +const: 2
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +allOf:
> > + - if:
> > + properties:
> > +compatible:
> > + contains:
> > +const: mediatek,mt8192-mali
> > +then:
> > + properties:
> > +sram-supply: true
> > +power-domains:
> > + description:
> > +List of phandle and PM domain specifier as documented in
> > +Documentation/devicetree/bindings/power/power_domain.txt
> > + minItems: 5
> > + maxItems: 5
> > +power-domain-names:
> > + items:
> > +- const: core0
> > +- const: core1
> > +- const: core2
> > +- const: core3
> > +- const: core4
> > +
> > + required:
> > +- sram-supply
> > +- power-domains
> > +
> > +examples:
> > + - |
> > +#include
> > +#include
> > +
> > +gpu@1300 {
> > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
> > + reg = <0x1300 0x4000>;
> > + interrupts =
> > + ,
> > + ,
> > + ;
> > + interrupt-names =
> > + "gpu",
> > + "mmu",
> > + "job";
> > +
> > + clocks = <&mfgcfg 0>;
> > +
> > + power-domains =
> > + <&spm 4>,
> > + <&spm 5>,
> > + <&spm 6>,
> > + <&spm 7>,
> > + <&spm 8>;
> > +
> > + operating-points-v2 = <&gpu_opp_table>;
> > + mali-supply = <&mt6315_7_vbuck1>;
> > + sram-supply = <&mt6359_vsram_others_ldo_reg>;
> > +};
> > +
> > +gpu_opp_table: opp_table0 {
>
> Make this a child node of the gpu node.
>
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-35800 {
> > + opp-hz = /bits/ 64 <35800>;
> > + opp-hz-real = /bits/ 64 <35800>,
> > +/bits/ 64 <35800>;
>
> This is not part of the OPP binding. It's not clear what it's purpose
> would be given the values are always the same as opp-hz.
>
>
> > + opp-microvolt = <606250>,
> > + <75>;
> > + };
> > +
> > + opp-39900 {
> > + opp-hz = /bits/ 64 <39900>;
> > + opp-hz-real = /bits/ 64 <39900>,
> > +/bits/ 64 <39900>;
> > + opp-microvolt = <618750>,
> > + <75>;
> > + };
> > +
> > + opp-44000 {
> > + opp-hz = /bits/ 64 <44000>;
> > + opp-hz-real = /bits/ 64 <44000>,
> > +/bits/ 64 <44000>;
> > +
Re: [PATCH v4 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
On Tue, Jan 12, 2021 at 02:49:32PM +0800, Nick Fan wrote:
> Add devicetree schema for Arm Mali Valhall GPU
>
> Define a compatible string for the Mali Valhall GPU
> for Mediatek's SoC platform.
>
> Signed-off-by: Nick Fan
> ---
> .../bindings/gpu/arm,mali-valhall.yaml| 252 ++
> 1 file changed, 252 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
>
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> new file mode 100644
> index ..ecf249a58435
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> @@ -0,0 +1,252 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM Mali Valhall GPU
> +
> +maintainers:
> + - Rob Herring
> +
> +properties:
> + $nodename:
> +pattern: '^gpu@[a-f0-9]+$'
> +
> + compatible:
> +items:
> + - enum:
> + - mediatek,mt8192-mali
> + - const: arm,mali-valhall
> +
> + reg:
> +maxItems: 1
> +
> + interrupts:
> +items:
> + - description: GPU interrupt
> + - description: MMU interrupt
> + - description: Job interrupt
> +
> + interrupt-names:
> +items:
> + - const: gpu
> + - const: mmu
> + - const: job
> +
> + clocks:
> +minItems: 1
> +
> + power-domains:
> +minItems: 1
> +maxItems: 5
> +
> + mali-supply: true
> + sram-supply: true
> +
> + operating-points-v2: true
> +
> + "#cooling-cells":
> +const: 2
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> +
> +additionalProperties: false
> +
> +allOf:
> + - if:
> + properties:
> +compatible:
> + contains:
> +const: mediatek,mt8192-mali
> +then:
> + properties:
> +sram-supply: true
> +power-domains:
> + description:
> +List of phandle and PM domain specifier as documented in
> +Documentation/devicetree/bindings/power/power_domain.txt
> + minItems: 5
> + maxItems: 5
> +power-domain-names:
> + items:
> +- const: core0
> +- const: core1
> +- const: core2
> +- const: core3
> +- const: core4
> +
> + required:
> +- sram-supply
> +- power-domains
> +
> +examples:
> + - |
> +#include
> +#include
> +
> +gpu@1300 {
> + compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
> + reg = <0x1300 0x4000>;
> + interrupts =
> + ,
> + ,
> + ;
> + interrupt-names =
> + "gpu",
> + "mmu",
> + "job";
> +
> + clocks = <&mfgcfg 0>;
> +
> + power-domains =
> + <&spm 4>,
> + <&spm 5>,
> + <&spm 6>,
> + <&spm 7>,
> + <&spm 8>;
> +
> + operating-points-v2 = <&gpu_opp_table>;
> + mali-supply = <&mt6315_7_vbuck1>;
> + sram-supply = <&mt6359_vsram_others_ldo_reg>;
> +};
> +
> +gpu_opp_table: opp_table0 {
Make this a child node of the gpu node.
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-35800 {
> + opp-hz = /bits/ 64 <35800>;
> + opp-hz-real = /bits/ 64 <35800>,
> +/bits/ 64 <35800>;
This is not part of the OPP binding. It's not clear what it's purpose
would be given the values are always the same as opp-hz.
> + opp-microvolt = <606250>,
> + <75>;
> + };
> +
> + opp-39900 {
> + opp-hz = /bits/ 64 <39900>;
> + opp-hz-real = /bits/ 64 <39900>,
> +/bits/ 64 <39900>;
> + opp-microvolt = <618750>,
> + <75>;
> + };
> +
> + opp-44000 {
> + opp-hz = /bits/ 64 <44000>;
> + opp-hz-real = /bits/ 64 <44000>,
> +/bits/ 64 <44000>;
> + opp-microvolt = <631250>,
> + <75>;
> + };
> +
> + opp-48200 {
> + opp-hz = /bits/ 64 <48200>;
> + opp-hz-real = /bits/ 64 <48200>,
> +/bits/ 64 <48200>;
> + opp-microvolt = <643750>,
> + <75>;
> + };
> +
> + opp-52300 {
> + opp-hz = /bits/ 64 <52300>;
> + opp-hz-real = /bits/ 64 <52300>,
> +
[PATCH v4 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Add devicetree schema for Arm Mali Valhall GPU
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..ecf249a58435
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall
+
+ reg:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+ - description: MMU interrupt
+ - description: Job interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+ - const: mmu
+ - const: job
+
+ clocks:
+minItems: 1
+
+ power-domains:
+minItems: 1
+maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+
+ "#cooling-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8192-mali
+then:
+ properties:
+sram-supply: true
+power-domains:
+ description:
+List of phandle and PM domain specifier as documented in
+Documentation/devicetree/bindings/power/power_domain.txt
+ minItems: 5
+ maxItems: 5
+power-domain-names:
+ items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+ required:
+- sram-supply
+- power-domains
+
+examples:
+ - |
+#include
+#include
+
+gpu@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x1300 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = <&mfgcfg 0>;
+
+ power-domains =
+ <&spm 4>,
+ <&spm 5>,
+ <&spm 6>,
+ <&spm 7>,
+ <&spm 8>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+ mali-supply = <&mt6315_7_vbuck1>;
+ sram-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+/bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+/bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+/bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-hz-real = /bits/ 64 <48200>,
+/bits/ 64 <48200>;
+ opp-microvolt = <643750>,
+ <75>;
+ };
+
+ opp-52300 {
+ opp-hz = /bits/ 64 <52300>;
+ opp-hz-real = /bits/ 64 <52300>,
+/bits/ 64 <52300>;
+ opp-microvolt = <656250>,
+ <75>;
+ };
+
+ opp-56400 {
+ opp-hz = /bits/ 64 <56400>;
+ opp-hz-real = /bits/ 64 <56400>,
+/bits/ 64 <56400>;
+ opp-microvolt = <668750>,
+ <75>;
+ };
+
+ opp-60500 {
+ opp-hz = /bits/ 64 <60500>;
+ opp-hz-real = /bits/ 64 <60500>,
+/bits/ 64 <60500>;
+
