Re: gEDA-user: Design changs required to mill PCBs?
On Wed, 4 Oct 2006, Robert Fitzsimons wrote: >> Do you still have the code? would you share? I have an old plotter and >> learned some HPGL years ago, even wrote some simple plotting tools. Now I >> would use HPGL as an example exporter with the scriptable PCB project. > >I didn't see a response from Dave, but I've attached the code wrote to >work with my plotter last year. It is able to convert a DXF file to >HPGL format. > >Hope it helps. Thanx, it's extremly useful, I will be able to reuse many functions :) Igor2 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design changs required to mill PCBs?
DJ Delorie wrote: I'm guessing it's using a variant of HPGL embedded in a PCL data stream. I.e. a mode switch between languages. The PCL5 spec has commands for this. That would make sense for driving the laser. It is just an X-Y device. The laser can be turned on and off, of course, and also you can adjust power level and traversal speed. Power * dwell time, adjusted for material properties and thickness, determines whether you get cutting or engraving. It also does raster engraving, so maybe the raster features of PCL5 are used there, and the vector functions of HPGL are used for shape cutting. I'm itchy to set up a protocol sniffer. Anyway, it could be a nifty way to make 1 and 2 sided "milled" PCB's. "Engrave" to remove copper, and let the laser cut all the way through the FR4 for vias. And of course I've mentioned before the possibility of doing el-cheapo solder paste stencils, which should be easy. It also has possibilities for doing odd-shaped PCB's, or for depanelizing. I've yet to see how well cuts FR4, though. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design changs required to mill PCBs?
Dave N6NZ wrote: Dave McGuire wrote: On Oct 4, 2006, at 6:48 PM, Robert Fitzsimons wrote: Do you still have the code? would you share? I have an old plotter and learned some HPGL years ago, even wrote some simple plotting tools. Now I would use HPGL as an example exporter with the scriptable PCB project. I didn't see a response from Dave, but I've attached the code wrote to work with my plotter last year. It is able to convert a DXF file to HPGL format. Sweet, that looks like it'll be handy. :-) I'm still looking for my old code; it's on one of about a hundred tapes. I know I have it, I'm just not sure where! Ok, it's getting pretty late in the day, so I had better ask my bone-head question of the day if I'm going to get it done. Is HPGL at all like PCL? I'm not very familiar with printer languages other than Postscript. The reason I ask is that the Epilog laser cutter to which I will soon have access is rumored to run on slightly tweaked PCL5. Epilog does not publish specs, but some work has already been done to reverse engineer the protocol, and from what I gather it is mostly PCL5. I can't really speak about PCL, but HPGL is quite simple. Remember it was developed for pen plotters so the commands are things like (not using the real HPGL syntax but rather the meaning of the command) "select pen #1", "pen up", "pen down", "draw a line from here to there", etc. The book "The HP-GL/2 Reference Guide" from HP is a pretty easy read. Perhaps someone else can give some tips on PCL5. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design changs required to mill PCBs?
> Is HPGL at all like PCL? HPGL is more like gerber. It's a vector plotting language - pen up, pen down, move here, move there, etc. PCL is primarily a raster language. Move cursor here, draw text/raster/whatever. Postscript is a combination, more of a generic programming language that happens to have a lot of graphics-oriented primitives. It can do both vector and raster operations. > I'm not very familiar with printer languages other than > Postscript. The reason I ask is that the Epilog laser cutter to > which I will soon have access is rumored to run on slightly tweaked > PCL5. Epilog does not publish specs, but some work has already been > done to reverse engineer the protocol, and from what I gather it is > mostly PCL5. I'm guessing it's using a variant of HPGL embedded in a PCL data stream. I.e. a mode switch between languages. The PCL5 spec has commands for this. You can download the PCL5 spec from HP's web site. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design changs required to mill PCBs?
Dave McGuire wrote: On Oct 4, 2006, at 6:48 PM, Robert Fitzsimons wrote: Do you still have the code? would you share? I have an old plotter and learned some HPGL years ago, even wrote some simple plotting tools. Now I would use HPGL as an example exporter with the scriptable PCB project. I didn't see a response from Dave, but I've attached the code wrote to work with my plotter last year. It is able to convert a DXF file to HPGL format. Sweet, that looks like it'll be handy. :-) I'm still looking for my old code; it's on one of about a hundred tapes. I know I have it, I'm just not sure where! Ok, it's getting pretty late in the day, so I had better ask my bone-head question of the day if I'm going to get it done. Is HPGL at all like PCL? I'm not very familiar with printer languages other than Postscript. The reason I ask is that the Epilog laser cutter to which I will soon have access is rumored to run on slightly tweaked PCL5. Epilog does not publish specs, but some work has already been done to reverse engineer the protocol, and from what I gather it is mostly PCL5. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design changs required to mill PCBs?
On Oct 4, 2006, at 6:48 PM, Robert Fitzsimons wrote: Do you still have the code? would you share? I have an old plotter and learned some HPGL years ago, even wrote some simple plotting tools. Now I would use HPGL as an example exporter with the scriptable PCB project. I didn't see a response from Dave, but I've attached the code wrote to work with my plotter last year. It is able to convert a DXF file to HPGL format. Sweet, that looks like it'll be handy. :-) I'm still looking for my old code; it's on one of about a hundred tapes. I know I have it, I'm just not sure where! -Dave -- Dave McGuire Cape Coral, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog Release 0.8.3
Stephen Williams wrote: Hi, I've noted that the Icarus Verilog 0.8 branch gets widespread use, and also the devel branch is still unstable, so I'm still actively maintaining the 0.8 branch; and that leads us to the new release 0.8.3. This is a stable, incremental release of the compiler. It only fixes bugs and some portability issues on the 0.8 branch, so those who are relying on the stability of 0.8 should try 0.8.3. I've uploaded the source code, a soruce RPM, and an x86_64 binary for SuSE 10.1. Other packagers are highly encouraged to get to work on this release. NetBSD pkgsrc has been updated. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design changs required to mill PCBs?
> Do you still have the code? would you share? I have an old plotter and
> learned some HPGL years ago, even wrote some simple plotting tools. Now I
> would use HPGL as an example exporter with the scriptable PCB project.
I didn't see a response from Dave, but I've attached the code wrote to
work with my plotter last year. It is able to convert a DXF file to
HPGL format.
Hope it helps.
Robert
/*
* Copyright (C) 2005, 2006 Robert Fitzsimons
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*
* This is a basic program which can convert a CAD file in DXF format
* to a HPGL file which can then be sent to a plotter. Initially
* developed for use with a HP 7475A plotter.
*
*
* Email: robfitz at 273k dot net
* Build: gcc -Wall -std=c99 -lm dxf2hpgl.c -o dxf2hpgl
* Usage: dxf2hpgl > output
*/
#include
#include
#include
#include
#include
#include
#include
#include
#define FLAG_TYPE_MASK 0xFF
#define FLAG_TYPE_POINT0x01
#define FLAG_TYPE_LINE 0x02
#define FLAG_TYPE_CIRCLE 0x03
#define FLAG_USED0x0100
#define FLAG_PRINTED 0x0200
#define FLAG_LINK0x0400
struct point {
double x;
double y;
double z;
};
struct line {
struct point p1;
struct point p2;
};
struct circle {
struct point p;
double radius;
};
struct object {
struct object *next;
int flags;
char line_type[128];
union {
struct point point;
struct line line;
struct circle circle;
} data;
};
struct object *object_list;
enum side {
SIDE_X1Y1 = 1,
SIDE_X2Y2 = 2
};
long int unit_convert(double unit) {
return lround(unit * 1000.0);
}
enum side find_link_end(struct object *link_obj, enum side link_side, struct object **link_end) {
struct object *obj;
struct point *p;
link_obj->flags |= (FLAG_LINK);
p = (link_side == SIDE_X1Y1) ? (&link_obj->data.line.p1) : (&link_obj->data.line.p2);
for (obj = object_list; obj != NULL; obj = obj->next) {
if ((obj->flags & FLAG_LINK) || (obj->flags & FLAG_PRINTED) || (obj->flags & FLAG_USED) || ((obj->flags & FLAG_TYPE_MASK) != FLAG_TYPE_LINE)) {
continue;
}
if ((p->x == obj->data.line.p1.x) && (p->y == obj->data.line.p1.y)) {
return find_link_end(obj, SIDE_X2Y2, link_end);
}
if ((p->x == obj->data.line.p2.x) && (p->y == obj->data.line.p2.y)) {
return find_link_end(obj, SIDE_X1Y1, link_end);
}
}
if (*(link_end) == NULL) {
*(link_end) = link_obj;
}
return link_side;
}
int print_link(struct object *link_obj, enum side link_side) {
struct object *obj;
struct point *p;
link_obj->flags |= (FLAG_PRINTED | FLAG_USED);
p = (link_side == SIDE_X1Y1) ? (&link_obj->data.line.p1) : (&link_obj->data.line.p2);
for (obj = object_list; obj != NULL; obj = obj->next) {
if ((obj->flags & FLAG_PRINTED) || (obj->flags & FLAG_USED) || ((obj->flags & FLAG_TYPE_MASK) != FLAG_TYPE_LINE)) {
continue;
}
if ((p->x == obj->data.line.p1.x) && (p->y == obj->data.line.p1.y)) {
fprintf(stdout, ",%ld,%ld", unit_convert(obj->data.line.p2.x), unit_convert(obj->data.line.p2.y));
return print_link(obj, SIDE_X2Y2);
}
if ((p->x == obj->data.line.p2.x) && (p->y == obj->data.line.p2.y)) {
fprintf(stdout, ",%ld,%ld", unit_convert(obj->data.line.p1.x), unit_convert(obj->data.line.p1.y));
return print_link(obj, SIDE_X1Y1);
}
}
return 0;
}
int print_line(struct object *object) {
struct object *link_end = NULL;
enum side link_side;
link_side = find_link_end(object, SIDE_X1Y1, &link_end);
if (link_side == SIDE_X1Y1) {
fprintf(stdout, "PU%ld,%ld;PD%ld,%ld", unit_convert(link_end->data.line.p1.x), unit_convert(link_end->data.line.p1.y), unit_convert(link_end->data.line.p2.x), unit_convert(link_end->data.line.p2.y));
print_link(link_end, SIDE_X2Y2);
} else {
fprintf(stdout, "PU%ld,%ld;PD%ld,%ld", unit_convert(link_end->data.line.p2.x), unit_convert(link_end->data.line.p2.y), unit_convert(link_end->data.line.p1.x), unit_convert(link_end->data.line.p1.y));
print_link(link_end, SIDE_X1Y1);
}
fprintf(stdout, ";\n");
return 0;
}
int print_circle(struct object *object) {
fprintf(stdout, "PU%ld,%ld:CI%ld;\n", unit_convert(object->data.circle.p.x), unit_convert(object->data.circle.p.y), unit_convert(object->data.circle.radius));
object->flags |= (FLAG_USED);
return 0;
}
int io_buffer_size = 64;
char io_buffer[64 + 1];
char *io_buffer_start
gEDA-user: Re: gEDA-dev: Filechooser and component selector code
Choices like leaving some windows open after a sequence, or toolbars that are visible is the kind I was thinking of. The keyboard commands are two letter in gschem, so that's not likely to change very easily, but starting some alternate way to execute commands with keys not claimed by the gschem UI would be good. It's handy in pcb. Some of the core functions act on the selected set and leave it selected, so you can do a big sequence of changes to a big group and get way ahead. John Griessen Peter Clifton wrote: I was thinking that the toobar layout might be customisable, but I just remembered it is hardcoded. Peter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog Release 0.8.3
Hi, I've noted that the Icarus Verilog 0.8 branch gets widespread use, and also the devel branch is still unstable, so I'm still actively maintaining the 0.8 branch; and that leads us to the new release 0.8.3. This is a stable, incremental release of the compiler. It only fixes bugs and some portability issues on the 0.8 branch, so those who are relying on the stability of 0.8 should try 0.8.3. I've uploaded the source code, a soruce RPM, and an x86_64 binary for SuSE 10.1. Other packagers are highly encouraged to get to work on this release. -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Design changs required to mill PCBs?
> How did you get that pcbpool quote? > I just got one for a 4 layer 50x50mm prototype and it was 143 euro > which is way more than $104. I'd love to get 4 layers for $100! 4" x 5" [*] 4 layer board, qty 1, gc-preview format, 8 days, = $94.38 Add $12.50 for top silk = $106.88 (84.27 euro) None of my prices include shipping, but that only adds $10 if you're not in a hurry. Note that there's a 16 in2 minimum from pcbpool; your board is only 4 in2 so you're paying for board space you aren't using. [*] my "20 in2" board is really 19.75 in2 - 3.5 x 5.5 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Newbie PCB DRC questions
Ah, my mistake then. Maybe they were auto routed segments I'd ripped up and manually routed. Apologies for the unwarranted slur on the auto router. > I don't believe these small segments are due to the autoroute process. > I see them a lot and I've never used the auto-router. I believe they > can occur when: > You add a line containing several segments with snap to pins and pads > turned on. This can put a short (< 1 grid long) segment in the line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
