Vendor FPGA tools (was Re: gEDA-user: Re: Pointer to 3d CAD?)
Michael - On Tue, Oct 31, 2006 at 05:05:21AM +, Michael Sokolov wrote: > [EMAIL PROTECTED] wrote: > > Ditto for the Xilinx toolchain on my box. [chop] > I've tried it, but got turned off in utter disgust when I saw that the > thing is packaged in encrypted (!) ZIPs specifically to make it > impossible to bypass their stinky GUI installer. The installer is indeed the worst part of the Xilinx setup. After it's installed, I too use the command-line-only programs. With some scripting, they embed nicely in my Makefiles. > > The free download version [of Quartus-II] [chop] > I'm not using that version, I'm using the native Linux version. You can > download it from ftp.altera.com:/outgoing/release. Thanks for the pointer! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Pointer to 3d CAD?
[EMAIL PROTECTED] wrote: > Ditto for the Xilinx toolchain on my box. At least once you are > registered, get the free-as-in-beer download, Xilinx XST works natively > and without monkeying with license keys. I've tried it, but got turned off in utter disgust when I saw that the thing is packaged in encrypted (!) ZIPs specifically to make it impossible to bypass their stinky GUI installer. > The free download version > of Quartus-II I found seems to need WINE and (no cost) keys. > Can you confirm that, or did I do something wrong? I'm not using that version, I'm using the native Linux version. You can download it from ftp.altera.com:/outgoing/release. It's a normal tar file containing .tar.gz's inside, no GUIs crammed down your throat. In fact I can't even use its GUI at all, only the command line utilities because my bootleg license file only has FEATURE quartus but not the other FEATURE (altera_mainwin_lnx or quartus_mainwin_lnx, something like that) that enables the GUI. But that's perfectly fine with me because command line tools are exactly what I want, my 80-column mind can't handle GUI. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Pointer to 3d CAD?
Friends - On Mon, Oct 30, 2006 at 11:45:08PM +, Michael Sokolov wrote: > Kai-Martin Knaak <[EMAIL PROTECTED]> wrote: > > That's why varicad is the only non open source software on my box. > So you don't work with FPGAs then, huh? The FPGA compiler (Altera > Quartus, Linux/x86 version) is the only sans-source piece of software > that I grudgingly put up with in my environment. Ditto for the Xilinx toolchain on my box. At least once you are registered, get the free-as-in-beer download, Xilinx XST works natively and without monkeying with license keys. The free download version of Quartus-II I found seems to need WINE and (no cost) keys. Can you confirm that, or did I do something wrong? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Orcad binary file format
Patrick Doyle wrote: Hello Friends, Does anybody on this list know where I could learn the binary file format of Orcad schematic files? Ultimately, I would like to create a set of tools to convert back and forth between gschem and Orcad designs. (Ideally, somebody has already done this, and I don't have to). I've looked a little at olib, but it presumes an older format. how about sarlacc? -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Orcad binary file format
Patrick Doyle wrote: On 10/30/06, Dan McMahill <[EMAIL PROTECTED]> wrote: Stuart Brorson wrote: >> Does an EDIF<->gschem translator exist? >> Would it be ridiculous to write one? (Anybody can step in here and >> say, "Well, you could write one, but you would never get the library >> interface to Orcad to work because they don't document the frozbazz >> interface and that is absolutely required", etc...) >> Would this be of use to anybody else in the universe? >> Any other thoughts? > > The problem is that EDIF is just a netlist format, and doesn't hold > info about the actual component's symbol (like is it a box, triangle, > where are the pins, etc). As such, any schematic you create from it > would be confusing at best. Are you sure that EDIF (for some version of EDIF) doesn't contain graphical info too? I thought it could but I could be wrong. Well, I started down the path this afternoon, and it appears that the EDIF file generated by Orcad contains most, perhaps even all, of the information stored in the binary Orcad design file. At least I saw things like references to librarys on my PC, instructions for drawin wires (separate from the actual netlist related instructions), junctions, etc... Now, all I need to do is to track down an EDIF file format specification and see where that leads me. The patch to allow edif netlist import into PCB (connectivity netlist only) is at: http://sourceforge.net/tracker/index.php?func=detail&aid=1516885&group_id=73743&atid=538813 you might look at that parser and see what it may tell you. I think the last time I looked I wasn't able to get a copy of the edif spec. But that was about 5 years ago. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Orcad binary file format
I hate rereading my emails _after_ I've clicked "send"!!! things like references to librarys on my PC, instructions for drawin Of course, that would be "libraries" and "drawing" :-) Perhaps I'll click "Check spelling" now... At least this one might be legible :-) --wpd ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Orcad binary file format
On 10/30/06, Dan McMahill <[EMAIL PROTECTED]> wrote: Stuart Brorson wrote: >> Does an EDIF<->gschem translator exist? >> Would it be ridiculous to write one? (Anybody can step in here and >> say, "Well, you could write one, but you would never get the library >> interface to Orcad to work because they don't document the frozbazz >> interface and that is absolutely required", etc...) >> Would this be of use to anybody else in the universe? >> Any other thoughts? > > The problem is that EDIF is just a netlist format, and doesn't hold > info about the actual component's symbol (like is it a box, triangle, > where are the pins, etc). As such, any schematic you create from it > would be confusing at best. Are you sure that EDIF (for some version of EDIF) doesn't contain graphical info too? I thought it could but I could be wrong. Well, I started down the path this afternoon, and it appears that the EDIF file generated by Orcad contains most, perhaps even all, of the information stored in the binary Orcad design file. At least I saw things like references to librarys on my PC, instructions for drawin wires (separate from the actual netlist related instructions), junctions, etc... Now, all I need to do is to track down an EDIF file format specification and see where that leads me. --wpd ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
DJ Delorie wrote: Tips like this really help cut down the learning curve. The curve would be shorter if it just didn't do that, of course. With the current CVS code, it doesn't do that. Is their a way to assign a "PCB layer" or set of copper to a specific net? So for instance my GND plane or polygon would be assigned to the GND net. Draw the polygon and tie it into the net with a thermal. PCB should figure the rest out from that. Any kind of connection will do - it can be done with a joining line instead of a thermal. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Pointer to 3d CAD?
Kai-Martin Knaak <[EMAIL PROTECTED]> wrote: > That's why varicad is the only non open source software on my box. ^^^ So you don't work with FPGAs then, huh? The FPGA compiler (Altera Quartus, Linux/x86 version) is the only sans-source piece of software that I grudgingly put up with in my environment. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Orcad binary file format
Stuart Brorson wrote: Does an EDIF<->gschem translator exist? Would it be ridiculous to write one? (Anybody can step in here and say, "Well, you could write one, but you would never get the library interface to Orcad to work because they don't document the frozbazz interface and that is absolutely required", etc...) Would this be of use to anybody else in the universe? Any other thoughts? The problem is that EDIF is just a netlist format, and doesn't hold info about the actual component's symbol (like is it a box, triangle, where are the pins, etc). As such, any schematic you create from it would be confusing at best. Are you sure that EDIF (for some version of EDIF) doesn't contain graphical info too? I thought it could but I could be wrong. On the topic of EDIF, there is a patch on sourceforge to allow loading EDIF netlists into PCB. I glanced briefly at it. Mostly what I need to do is contact the author of the edif parser and see if it is ok for inclusion in a gpl-ed program. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Pointer to 3d CAD?
On Mon, 30 Oct 2006 11:27:59 -0800, Dave N6NZ wrote: > Off topic I know, but I need a pointer. Is there a decent FOSS 3D CAD > program that will create STL files for simple parts? No. Even commercial 3D CAD programs that run on linux are few. I know just one. That's why varicad is the only non open source software on my box. ---<(kaimartin)>--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Orcad binary file format
On Mon, 30 Oct 2006, Patrick Doyle wrote: On 10/27/06, Patrick Doyle <[EMAIL PROTECTED]> wrote: Hello Friends, Does anybody on this list know where I could learn the binary file format of Orcad schematic files? Ultimately, I would like to create a set of tools to convert back and forth between gschem and Orcad designs. (Ideally, somebody has already done this, and I don't have to). I've looked a little at olib, but it presumes an older format. --wpd I just noticed that Orcad (10.5 is what I'm running, which I should have mentioned previously) has an "export to EDIF" option. Suppose I were to export my design to EDIF, import it into gschem, play with it there, and reverse the process... Does an EDIF<->gschem translator exist? Would it be ridiculous to write one? (Anybody can step in here and say, "Well, you could write one, but you would never get the library interface to Orcad to work because they don't document the frozbazz interface and that is absolutely required", etc...) Would this be of use to anybody else in the universe? Any other thoughts? The problem is that EDIF is just a netlist format, and doesn't hold info about the actual component's symbol (like is it a box, triangle, where are the pins, etc). As such, any schematic you create from it would be confusing at best. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On Mon, 30 Oct 2006, John Luciani wrote: On 10/30/06, Peter Baxendale <[EMAIL PROTECTED]> wrote: Another dumb question. I teach a class of undergraduates about ECAD and this year abandoned commercial tools in favour of geda. Students being students, they tend to try things I wouldn't think of doing. Today, a couple of them decided to be creative and on their schematic used names like "CONNpower" and "CONNsignal" for refdes values. Whilst I thought it unconventional and probably inadvisable, I couldn't offhand see why they shouldn't do that. A reason not to have long refdes values is clutter. Names that are seven and eight characters get difficult to place (legibly) on dense schematics and PCBs. A seven character refdes will probably take up more board area than most of you SMD components. I'll add a second reason. In a very common design flow, you first create a schematic with refdeses R1, R2, R3, C1, C2, C3, etc. Then you lay out the board. Then when the layout is done, the layout engineer *renumbers* the refdeses from e.g. upper left to lower right. The new refdeses are then backannotated into the final schematic. The idea is that refdeses with similar number all lie close to each other so that when it comes time to service the board (or during DVT) you can more easily find the components. Note that you can't do this with things like CONNpower and CONNsignal. How do you renumber alpha refdeses? Admittedly, CONNpower and the like are easier to deal with than J1, J2, etc, but if you've got a board with thousands of components on it, then you can't give each a unique alpha refdes, and the above renumbering scheme is extremely convenient. Since we can't do backanno in gschem/PCB, this point is moot, however. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
> I found a command in the manual called ChangeJoin( SelectedItems). When > I performed a select all and issued the command nothing seemed to > happen. Shouldn't this command perform the same function as j? Try ClrFlag(SelectedLines,Join) Make sure you're running the latest CVS copy of pcb, though. I think Harry fixed a bug in this recently. > Thanks, that clears things up. I really appreciate the patience as > I get up to speed. In the future, please try to trim off unneeded bits of the previous emails you're quoting. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
DJ Delorie wrote: Tips like this really help cut down the learning curve. The curve would be shorter if it just didn't do that, of course. Sure. As a newbie I didn't realize that a small grid spacing would make operations down the road more difficult. While exploring this problem I was also trying to find a different way to set the clear flag. For instance if I draw the polygon over a lot of traces at the end of the routing phase there's probably a handy way to activate the polygon clearance (correct terminology?) for all the traces in that group. I found a command in the manual called ChangeJoin( SelectedItems). When I performed a select all and issued the command nothing seemed to happen. Shouldn't this command perform the same function as j? So if I'm understanding this correctly let me re-summarize, inserting a few more questions as we go. The actual number of manufactured layers is determined by the number of groups in use. Mostly. Actually, it's determined by how many of those groups you send to the FAB :-) For example, I might add a few groups (as individual layers) for other purposes, then just omit those files when I send them off. PCB produces one gerber (CAM) file per layer group. It's up to you to send the right ones to the fab. The buttons labeled "layers" in PCB is actually associated copper. Think "drawing layers". A layer group is the closest analog to "copper layer". Each group of copper ["drawing layer"] be assigned different colors to help visualize the purpose of each set. Yes. How do you communicate to the board house which group(manufactured layer) is the top or layer 1(top), 2,3, bottom? Perhaps it's not so much that there is a top an bottom as it is which copper is grouped with each other. In nearly all cases, you have to tell them which is which via a README or a web form. When you export gerbers, it names the component-side one and the solder-side ones appropriately, with the remaining copper layers being numbered. It's up to you to rename them, rearrange them, document them, whatever, to tell the fab shop which is whick. The exceptions are companies like PCB-Pool, which accept GC-Prevue format, which allows you to import the gerbers and arrange and tag them appropriately, then send the whole project to them as a single file. Note that PCB emits one gerber (or postscript print) for each layer *group*, not for each *layer*. Is their a way to assign a "PCB layer" or set of copper to a specific net? So for instance my GND plane or polygon would be assigned to the GND net. Draw the polygon and tie it into the net with a thermal. PCB should figure the rest out from that. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Thanks, that clears things up. I really appreciate the patience as I get up to speed. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Pointer to 3d CAD?
Off topic I know, but I need a pointer. Is there a decent FOSS 3D CAD program that will create STL files for simple parts? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
> Tips like this really help cut down the learning curve. The curve would be shorter if it just didn't do that, of course. > So if I'm understanding this correctly let me re-summarize, inserting a > few more questions as we go. The actual number of manufactured layers > is determined by the number of groups in use. Mostly. Actually, it's determined by how many of those groups you send to the FAB :-) For example, I might add a few groups (as individual layers) for other purposes, then just omit those files when I send them off. PCB produces one gerber (CAM) file per layer group. It's up to you to send the right ones to the fab. > The buttons labeled "layers" in PCB is actually associated copper. Think "drawing layers". A layer group is the closest analog to "copper layer". > Each group of copper ["drawing layer"] be assigned different colors > to help visualize the purpose of each set. Yes. > How do you communicate to the board house which group(manufactured > layer) is the top or layer 1(top), 2,3, bottom? Perhaps it's not so > much that there is a top an bottom as it is which copper is grouped > with each other. In nearly all cases, you have to tell them which is which via a README or a web form. When you export gerbers, it names the component-side one and the solder-side ones appropriately, with the remaining copper layers being numbered. It's up to you to rename them, rearrange them, document them, whatever, to tell the fab shop which is whick. The exceptions are companies like PCB-Pool, which accept GC-Prevue format, which allows you to import the gerbers and arrange and tag them appropriately, then send the whole project to them as a single file. Note that PCB emits one gerber (or postscript print) for each layer *group*, not for each *layer*. > Is their a way to assign a "PCB layer" or set of copper to a > specific net? So for instance my GND plane or polygon would be > assigned to the GND net. Draw the polygon and tie it into the net with a thermal. PCB should figure the rest out from that. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
DJ Delorie wrote: If I can get away with 2 layers I want a GND plane on the bottom layer which will be split up by traces that just couldn't fit on the components side of the board. I did something like that here: http://www.delorie.com/pcb/m3a/ 1. Even after the polygon was cleared from the trace the rat's nest was claiming that the net associated with the trace on solder side was shorting with GND??? I remove the trace and the error goes away...if I leave the trace and remvoe the GND plane the error goes away. How do I figure out what is wrong when visually the GND polygon is clearing the net? You might have a "stub" trace under one of the pads. Try disabling the pin and via layers to see if there's a tiny trace under one of them. I took a look at this over my lunch break. You were right I had my grid setting to 10 mill and my 80 mill trace had a really short small line right before it connected to the via. The polygon wasn't visually touching the line but it was creating a point right at the short line. When I redrew the line with a larger grid and payed closer attention to making longer continuous lines I was able to j on all the lines. After o the route was complete and there were not shorts to that net. Thanks a lot for the tip. Tips like this really help cut down the learning curve. 2. Should I draw the GND plane at the beginning or should it be the last step? What I did was run traces for power and ground, and complete and DRC the design that way, including checking for shorts. Then, I added the polygons one at a time, re-testing after each. Ok 3. I have unplated holes on one of my symbols that is enforcing a clearance on the component side but not on the Solder side. After I drew polygon associated with GND_SLDER I get warnings about a polygon to close to the holes. Why is there not a clearance on the Solder side of the board enforced for nonplated holes? How do I get this clearance around the holes to work? Might be easier and cheaper to make it a plated hole; most fabs charge extra for nonplated holes. But, it should work anyway. Can you come up with a minimum example board that demonstrates this? I plan on changing them to make it cheaper I just wanted to invest the time now in understanding what I'm doing wrong. I'll make a simple example and make a new post for this. 4. Layer assignments. I understand that PCB goes up to 8 layers. 16 layers. 8 is just the default starting set; you can add and remove layers as your design needs. You can go higher than 16 is you recompile; edit MAX_LAYER in globalconst.h In the preferences there is up to 8 groups and 8 different buttons two of which are unassigned by default. If I changed my design to a 4 layer design with the following configuration: Bottom (Layer 4): Signal and components Middle (Layer 3): GND Middle (Layer 2): VCC: 3.3, 5, and 12 Top (Layer 1): Signal and components How would I configure the groups and Y axis buttons in PCB layer preferences to acheive the results above? I saw in the info tab an example but I don't think it's exactly what I'm after. For a four layer design, just assign the first four layers to the four copper layers, and put each in their own group. You can either delete the remaining layers, or assign them to a separate group. If you need a board outline layer, assign that its own group also. When I did my board, I assigned five layers to each side of the board, only because I wanted different signals to be colored differently. I had colors for trace, power trace, power poly, ground trace, and ground poly; for each side. Ten layers for a two-layer board. It came in handy, as I could de-group the poly layers to hide them or re-check the trace connectivity, or to show only the polygons when editing them became tricky. So if I'm understanding this correctly let me re-summarize, inserting a few more questions as we go. The actual number of manufactured layers is determined by the number of groups in use. The buttons labeled "layers" in PCB is actually associated copper. PCB allows you to have a number of different "sets of associated copper"(PCB layers) to be on the same manufactured layer. Each group of copper be assigned different colors to help visualize the purpose of each set. How do you communicate to the board house which group(manufactured layer) is the top or layer 1(top), 2,3, bottom? Perhaps it's not so much that there is a top an bottom as it is which copper is grouped with each other. Is their a way to assign a "PCB layer" or set of copper to a specific net? So for instance my GND plane or polygon would be assigned to the GND net. Then each pad or pin that needs to be connected to the GND net would actual draw a rat to my GND plane helping me to visualize the routes that actually cross. ___ geda-user mailing list geda-user@moria.seu
Re: gEDA-user: gPCB Polygon Best Practices
> I think you made that board on PCB Lesstif version, am I right? Yup. Just before the polygon clipper code. > Around P9, P8, P7 and P6 has a polygon. Here it appeared in dark > red, first layer (component) That poly should be on the solder side. It connects to VCC (see thermals on P6-9's VCC pin). > but over that polygon passes a lot of lines from that same board, > and they are not connected. That polygon makes sense if become blue > (second layer), and made him blue by changing to the second layer > and pressed m over the polygon, and all made sense. My layer groups: TOP BOT x component x solder x comp-vcc x comp-gnd x solder-vcc x solder-gnd x comp-vcc-poly x comp-gnd-poly x solder-vcc-poly x solder-gnd-poly Note that there are ten layers. > I dont know, but I think there are some incompatibility with lesstif > x gtk .ocb generated files... Shouldn't be. The part that saves the file is independent of the GUI. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
Em Seg 30 Out 2006 15:55, DJ Delorie escreveu: > > If I can get away with 2 layers I want a GND plane on the bottom > > layer which will be split up by traces that just couldn't fit on the > > components side of the board. > > I did something like that here: http://www.delorie.com/pcb/m3a/ Hy DJ. I think you made that board on PCB Lesstif version, am I right? I opened the file on the GTK version, 20060822, and something strange appeared. Around P9, P8, P7 and P6 has a polygon. Here it appeared in dark red, first layer (component) but over that polygon passes a lot of lines from that same board, and they are not connected. That polygon makes sense if become blue (second layer), and made him blue by changing to the second layer and pressed m over the polygon, and all made sense. I dont know, but I think there are some incompatibility with lesstif x gtk .ocb generated files... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
Em Seg 30 Out 2006 15:33, Jeff VR escreveu: > I spent the past few month becoming familiar with PCB and after > finishing my schematic in gschem I'm ready to start the layout. > Hooray! I've got a fairly good handle on the basics but there are few > areas that I need a little assistance/guidance. The first is getting > polygons and lines to play nicely together. My plan is to try and get > my design on a 2 layer board. I've spent a lot of time arranging > components to make routing as painless as possible. If I can get away > with 2 layers I want a GND plane on the bottom layer which will be > split up by traces that just couldn't fit on the components side of > the board. So I did some practicing and drew a line for on the solder > side of the board. Afterwards I drew a large rectangle(polygon) on > the solder side when I had GND_SLDR chosen . I then figured out that > j enforced the clearances around the line and nicely removed the > GND polygon from the trace. > > Problems/Questions: > 1. Even after the polygon was cleared from the trace the rat's nest > was claiming that the net associated with the trace on solder side was > shorting with GND??? I remove the trace and the error goes away...if > I leave the trace and remvoe the GND plane the error goes away. How > do I figure out what is wrong when visually the GND polygon is > clearing the net? I had a strange problem yesterday. I made two polygons that I wish to use to conduct large amount of current, and use thermals to connect them to the pins I wish. Everything was working just right, when PCB started to say a lot of shorts. I tryed everything, I deleted all the polygons, thermals, lines, started again, used lines instead of thermals, nothing. Then I closed PCB, opened again, andthe problem has gone, and I finished my board. The kind of bug really hard to track, because it didnt appeared again... > 2. Should I draw the GND plane at the beginning or should it be the last > step? IMHO thats the last step. I must position the components thinking about the plane, draw the lines thinking on the plane, but only draw the plane when the stage is mounted. Draw the plane thinking about where the current will flow, how it will interfere on other lines, etc. > 3. I have unplated holes on one of my symbols that is enforcing a > clearance on the component side but not on the Solder side. After I > drew polygon associated with GND_SLDER I get warnings about a polygon > to close to the holes. Why is there not a clearance on the Solder > side of the board enforced for nonplated holes? How do I get this > clearance around the holes to work? Sometimes PCB gives a lot of warnings about polygons too close to pins, when I already made the pin connected to the polygon. The problem is that I never waste time looking exactly why PCB did so... > 4. Layer assignments. I understand that PCB goes up to 8 layers. In > the preferences there is up to 8 groups and 8 different buttons two > of which are unassigned by default. If I changed my design to a 4 > layer design with the following configuration: > > Bottom (Layer 4): Signal and components > Middle (Layer 3): GND > Middle (Layer 2): VCC: 3.3, 5, and 12 > Top (Layer 1): Signal and components > > How would I configure the groups and Y axis buttons in PCB layer > preferences to acheive the results above? I saw in the info tab an > example but I don't think it's exactly what I'm after. By default, PCB creates 8 groups with one layer per group. If you want to make the board that way (you wrote above) just rename the layers you want to use with names you like, and go on. Of course, choose names like middle_vcc and middle_gnd or something like that. > Any assitance is greatly appreciated. > > Thanks > Jeff > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Funny problem in PCB
Tip of the day: How to make a via disappear - Place a via anywhere - Press Control+H over it some times. The via disappears, but in the drill table, it appears as a via with 0 mils of size... How do delete it? Good question... try to draw a selection box over the via, and delete all. With a bit of luck, you can find it :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
> If I can get away with 2 layers I want a GND plane on the bottom > layer which will be split up by traces that just couldn't fit on the > components side of the board. I did something like that here: http://www.delorie.com/pcb/m3a/ > 1. Even after the polygon was cleared from the trace the rat's nest > was claiming that the net associated with the trace on solder side was > shorting with GND??? I remove the trace and the error goes away...if > I leave the trace and remvoe the GND plane the error goes away. How > do I figure out what is wrong when visually the GND polygon is > clearing the net? You might have a "stub" trace under one of the pads. Try disabling the pin and via layers to see if there's a tiny trace under one of them. > 2. Should I draw the GND plane at the beginning or should it be the >last step? What I did was run traces for power and ground, and complete and DRC the design that way, including checking for shorts. Then, I added the polygons one at a time, re-testing after each. > 3. I have unplated holes on one of my symbols that is enforcing a > clearance on the component side but not on the Solder side. After I > drew polygon associated with GND_SLDER I get warnings about a > polygon to close to the holes. Why is there not a clearance on the > Solder side of the board enforced for nonplated holes? How do I get > this clearance around the holes to work? Might be easier and cheaper to make it a plated hole; most fabs charge extra for nonplated holes. But, it should work anyway. Can you come up with a minimum example board that demonstrates this? > 4. Layer assignments. I understand that PCB goes up to 8 layers. 16 layers. 8 is just the default starting set; you can add and remove layers as your design needs. You can go higher than 16 is you recompile; edit MAX_LAYER in globalconst.h > In the preferences there is up to 8 groups and 8 different buttons > two of which are unassigned by default. If I changed my design to a > 4 layer design with the following configuration: > > Bottom (Layer 4): Signal and components > Middle (Layer 3): GND > Middle (Layer 2): VCC: 3.3, 5, and 12 > Top (Layer 1): Signal and components > > How would I configure the groups and Y axis buttons in PCB layer > preferences to acheive the results above? I saw in the info tab an > example but I don't think it's exactly what I'm after. For a four layer design, just assign the first four layers to the four copper layers, and put each in their own group. You can either delete the remaining layers, or assign them to a separate group. If you need a board outline layer, assign that its own group also. When I did my board, I assigned five layers to each side of the board, only because I wanted different signals to be colored differently. I had colors for trace, power trace, power poly, ground trace, and ground poly; for each side. Ten layers for a two-layer board. It came in handy, as I could de-group the poly layers to hide them or re-check the trace connectivity, or to show only the polygons when editing them became tricky. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gPCB Polygon Best Practices
I spent the past few month becoming familiar with PCB and after finishing my schematic in gschem I'm ready to start the layout. Hooray! I've got a fairly good handle on the basics but there are few areas that I need a little assistance/guidance. The first is getting polygons and lines to play nicely together. My plan is to try and get my design on a 2 layer board. I've spent a lot of time arranging components to make routing as painless as possible. If I can get away with 2 layers I want a GND plane on the bottom layer which will be split up by traces that just couldn't fit on the components side of the board. So I did some practicing and drew a line for on the solder side of the board. Afterwards I drew a large rectangle(polygon) on the solder side when I had GND_SLDR chosen . I then figured out that j enforced the clearances around the line and nicely removed the GND polygon from the trace. Problems/Questions: 1. Even after the polygon was cleared from the trace the rat's nest was claiming that the net associated with the trace on solder side was shorting with GND??? I remove the trace and the error goes away...if I leave the trace and remvoe the GND plane the error goes away. How do I figure out what is wrong when visually the GND polygon is clearing the net? 2. Should I draw the GND plane at the beginning or should it be the last step? 3. I have unplated holes on one of my symbols that is enforcing a clearance on the component side but not on the Solder side. After I drew polygon associated with GND_SLDER I get warnings about a polygon to close to the holes. Why is there not a clearance on the Solder side of the board enforced for nonplated holes? How do I get this clearance around the holes to work? 4. Layer assignments. I understand that PCB goes up to 8 layers. In the preferences there is up to 8 groups and 8 different buttons two of which are unassigned by default. If I changed my design to a 4 layer design with the following configuration: Bottom (Layer 4): Signal and components Middle (Layer 3): GND Middle (Layer 2): VCC: 3.3, 5, and 12 Top (Layer 1): Signal and components How would I configure the groups and Y axis buttons in PCB layer preferences to acheive the results above? I saw in the info tab an example but I don't think it's exactly what I'm after. Any assitance is greatly appreciated. Thanks Jeff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Current source rail blocking
Karel Kulhavy wrote: In my broadband high sensitivity amplifier I have a rail where bases of all current source transistors are hooked up. . . . . what happens if some load puts a surge of electricity into the collector of one of them and it gets through the C-B capacitance on the connected bases. . . . . The transistor has E-B charged to constant voltage and that corresponds to the pre-set current. Only if the series base resistor is overriding factor so RF thru capacitance from C to base only small percentage effect. How much does the load or driven voltage vary on the output of theese current sources? If not a big voltage swing, maybe lower perf transistor is all you need... If you find some LOW gain transistors (Igain = 30?) for these DC current sources, your series R's will need to be lower, base current higher, and oscillation less likely and feedback thru input or output capacitance less and problems go away... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
> Any lower case suffix is ignored. This is so you can, for example, place > 4 discrete NAND gates on the schematic called U1a, U1b, U1c and U1d, and > they will netlist into a single footprint / component, U1. > Ah, thanks - that explains exactly what I was seeing - CONNpower became CONN. > I'm not sure of any other restrictions. Spaces are probably unwise " ", > but I've not tested that. The students tried that - as you'd expect, spaces are a bad idea. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
> A reason not to have long refdes values is clutter. Names that are seven and > eight characters get difficult to place (legibly) on dense schematics and > PCBs. A seven character refdes will probably take up more board area than most > of you SMD components. Yes, I agree entirely. What I meant was that I was surprised that pcb doesn't work with this kind of refdes. For instance, Ja doesn't work either. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On 10/30/06, Peter Baxendale <[EMAIL PROTECTED]> wrote: Another dumb question. I teach a class of undergraduates about ECAD and this year abandoned commercial tools in favour of geda. Students being students, they tend to try things I wouldn't think of doing. Today, a couple of them decided to be creative and on their schematic used names like "CONNpower" and "CONNsignal" for refdes values. Whilst I thought it unconventional and probably inadvisable, I couldn't offhand see why they shouldn't do that. A reason not to have long refdes values is clutter. Names that are seven and eight characters get difficult to place (legibly) on dense schematics and PCBs. A seven character refdes will probably take up more board area than most of you SMD components. I usually use Jn for connectors. If I want to label a connector "power" or "signal" I will add labels to the schematic and PCB. It is usually easier to place two smaller strings (neatly) than one large one. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Haunted BF982
On 10/30/06, Karel Kulhavy <[EMAIL PROTECTED]> wrote: I can't - the transistor is in a hole in a metal shielding partition, two legs (G1,G2) on one side and the other two on the other (D, S). No way to use the metal shielding itself as a heatsink then? -- Samuel A. Falvo II ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Orcad binary file format
On 10/27/06, Patrick Doyle <[EMAIL PROTECTED]> wrote: Hello Friends, Does anybody on this list know where I could learn the binary file format of Orcad schematic files? Ultimately, I would like to create a set of tools to convert back and forth between gschem and Orcad designs. (Ideally, somebody has already done this, and I don't have to). I've looked a little at olib, but it presumes an older format. --wpd I just noticed that Orcad (10.5 is what I'm running, which I should have mentioned previously) has an "export to EDIF" option. Suppose I were to export my design to EDIF, import it into gschem, play with it there, and reverse the process... Does an EDIF<->gschem translator exist? Would it be ridiculous to write one? (Anybody can step in here and say, "Well, you could write one, but you would never get the library interface to Orcad to work because they don't document the frozbazz interface and that is absolutely required", etc...) Would this be of use to anybody else in the universe? Any other thoughts? --wpd ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: BC547 vs. 2N3904
On Mon, Oct 30, 2006 at 12:52:15PM +0100, Wojciech Kazubski wrote: > > Do you like more BC547C for higher frequency applications or 2N3904? > > I once did a simulation for some Ronja differential limiting amplifier > > which showed that BC547C is a bit better than 2N3904 because, despite > > it being lazy, it has higher amplification. > > Yo can also use BF240 (SMD variant BF840) if you want to amplify up to some > 50MHz or even BFR91 (SMD=> BFR93) if faster transistors are needed. Those > transistors cannot be used for saturated switching. For such case try old Does driving the transistor into cutoff but not saturation also count as saturation switching? CL< > 2N2369 or its derivatives (plastic or SMD). But faster the transistor, more > likely it oscillates. > > > > Is it possible to get rid of oscillating transistors by replacing the > > hand-soldered airwire with a SMD on a 2-sided PCB with a ground-plane? > > Very recommended. Use shortest possible connections to ground and try not to > cut the ground plane with traces, especially long. > > > > What is the major cause of oscillations in high-frequency amplifiers? > > Inductance of wires? > > If your circuit oscillates well above the operating frequency it is mainly > due > to inductance of wires plus parasitic capacitances inside the transistor. The > input-output capacitance is major cause of instability of resonant apmlifiers > (RF or IF) In this case oscillations are at or near operating frequency. > Sometimes amplifiers oscillate on LF due to bad supply decoupling. > > > Wojciech Kazubski > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Haunted BF982
On Mon, Oct 30, 2006 at 08:15:51AM -0500, Dan McMahill wrote: > Karel Kulhavy wrote: > >I was wondering why something is limiting the bandwidth of my 1MHz square > >signal from the bottom so the square wave had higher beginning and lower > >end (significantly). > > Do you have a picture of the waveform you can post? > > >I figured out it is caused by the BF982 transistor. The signal at the > >input gate is fine, on the output (which is drain directly into a 220 ohm > >load), it is already deformed. The source is nailed to the ground. The > >transistor has tons of headroom and runs from 12V. It happens even on > >microscopically small signals. The operating point of G1 is in the middle > >of it's almost-linear space, the G2 is at full amplification point at > >4V, amply blocked to the ground with total of 100nF. > > Have you probed G2 just to be sure it isn't moving around? Yes, it's flat. > > Vds max is 12 V on that device, I might be a bit nervous with a supply > that hits that limit. It actually isn't 12V, it's 11.9V (after RC filtration) and then the 220 ohm resistors eats something more. > > >The transistor was disconnected from the rest of the amplifier, isolated, > >nothing was connected to the 200 Ohm workload. > > > >Is it possible that as the transistor is optimized for 300MHz or 800MHz > >operation, they actually managed to make it start amplifying a bit less > >from 150kHz downwards? > > Not that I know of but I have very little experience in actually using > dual gate FET's. > > >As I couldn't find any physical cause that I could control, I implemented > >a compensation for the deformation in the next stage and now the wave > >is nicely level. The compensation turns out to be perfect when calculated > >for 150kHz simple RC high-pass. > > > >I think I saw this effect in another receiver populated by BF988, too. > > By any chance do things, like the 150 kHz frequency, change if you stick > a heatsink on that transistor? For the purposes of this test, it > doesn't need to be attached very well mechanically as long as its > connected thermally. I'm thinking of just a drop of thermal grease with > a large enough piece of aluminum stuck on top. "Large enough" would be > something that appreciably changes the thermal system. I can't - the transistor is in a hole in a metal shielding partition, two legs (G1,G2) on one side and the other two on the other (D, S). CL< ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Current source rail blocking
On Mon, Oct 30, 2006 at 06:40:13AM -0500, Dan McMahill wrote: > Karel Kulhavy wrote: > >gn Sun, Oct 29, 2006 at 07:09:46PM -0500, Dan McMahill wrote: > > > >>Karel Kulhavy wrote: > >> > >>>Hello > >>> > >>>In my broadband high sensitivity amplifier I have a rail where bases of > >>>all > >>>current source transistors are hooked up. Each current source is a > >>>transistor > >>>with an emitter resistor which compensates variance in aplification so > >>>that > >>>even unmatched transistors produce matched currents. > >>> > >>>Do you have any recommendations how to block the current sources from > >>>picking > >>>up some garbage from the air and causing oscillation? Should I block the > >>>rail > >>>with a single big capacitor against the ground, or use individual > >>>capacitor for > >>>each transistor placed between emitter and base? > >> > >>What sort of transistors are these? Are you seeing oscillations in > > > > > >2N3904 > > > > > >>practice or is this just a concern prior to seeing any real hardware? > > > > > >In practice. > > > > > >>I'd avoid using transistors which are faster than need be. For example, > >>sticking a 20 GHz device in there may not be a good idea. > >> > >>If you can tolerate some additional noise, you can stick some resistance > >>in series with the base if the transistors themselves are oscillating. > > > > > >Why does this help? Slows down the transistor by forming an RC lowpass > >with the inherent E-B capacitance of the transistor? > > Calculate the impedance seen looking into the base of a common emitter > stage that has capacitance from emitter to ground. If you have > capacitance to ground at the emitter, then there is an impedance > proportional to 1/j*w there. Now refer that to the base side. At > higher frequencies, the transistor current gain is falling off with > frequency so now you get a 1/(j*w)^2 term in the impedance looking into > the base. When you actually work out the math, you'll get some > expression that will have a capacitive term along with a *negative* > resistance term. Combine that with some inductance (from the board > layout, package leads, etc) and you have an oscillator. The series R > serves to produce a net positive resistance. > > >Is it possible to hook up a test circuit with the parasitics in gnucap and > >run it and see it if it oscillates? Or is it just going to say "internal > >node open" or fail to converge? > > It should be very easy to simulate the negative input resistance. This > is also easy to calculate by hand. To simulate oscillations you'll need > to be sure you have a correct model for whatever parasitic inductance > you may have in the base circuit. > > > > >BTW how does the reality work that it always converges? Is it possible to > >build a real electronic circuit that causes the universe to fail to > >converge > >and be terminated with an error message? > > > >If not, why isn't the same calculation that is used to run the universe > >just > >put into gnucap so it would converge every time? > > > >Does gnucap convergence failure indicate the circuit would oscillate? > >Does an oscillator circuit in gnucap always cause convergence failure on > >transient mode simulation? > > Many of my convergence problems (not speaking of gnucap but simulators > in general) come from bad inputs. Reality usually doesn't include an > ideal 1F capacitor or an inductor with no loss. Reality usually doesn't > include a voltage coefficient on some element which causes a stable > operating point with internal voltages outside the supply. Certainly a > simulator can mess up too, but it's pretty easy to feed them a model > which does not reflect reality. > > >Well, I want to build a current source from a single 2N3904 (or a double > >one if > >it's a current mirror where the driving half can be recycled for multiple > >mirrors) that gives 2.5mA constant current and behaves like a current > >mirror > >to as high frequencies as possible (i. e. not something that is nicely > >stable but from 10kHz up it starts behaving like a capacitor instead of > >current source). How would you do it? > > When you say behaves like a current mirror to as high freq. as possible, > do you mean Iout/Iin is wideband or that the impedance looking into the > output is as high as possible? The impedance looking into the output. What about putting a coil in series with the collector? > > Your basic approach you already described is fine. I'd just pay > particular attention to the potential for instability. This means don't > add extra C to ground from the emitter and maybe leave room in your > layout for some series R in the bases. The bases of several transistors in the current supplies are wired together. I am concerned what happens if some load puts a surge of electricity into the collector of one of them and it gets through the C-B capacitance on the connected bases. Then the drive voltage of the current supplie
Re: gEDA-user: pcb refdes name restrictions?
On Mon, 2006-10-30 at 13:59 +, Peter Baxendale wrote: > Another dumb question. I teach a class of undergraduates about ECAD and > this year abandoned commercial tools in favour of geda. Students being > students, they tend to try things I wouldn't think of doing. Today, a > couple of them decided to be creative and on their schematic used names > like "CONNpower" and "CONNsignal" for refdes values. Whilst I thought it > unconventional and probably inadvisable, I couldn't offhand see why they > shouldn't do that. > > Gsch2pcb happily produced a netlist and pcb file which both looked fine, > as far as I could tell. But when loaded into pcb, optimising the netlist > causes error messages such as "Can't find CONN pin 4 called for in > netlist". > > So does pcb require that all reference designators be in the form of a > string followed by a numerical value? If so, are there any other refdes > restrictions I should know about? Given time, they're bound to find > them... > > Thanks, > PB Any lower case suffix is ignored. This is so you can, for example, place 4 discrete NAND gates on the schematic called U1a, U1b, U1c and U1d, and they will netlist into a single footprint / component, U1. (The NAND symbols are "slotted", you set the 4 gates to a different slot number - with the "slot" attribute, and they will each netlist to the correct pins in the final package.) So... don't use lowercase suffixes, also: Don't use the hyphen character "-", in the refdes, as it upsets the M4 macro language used to process generating the footprints. (I think "_" is ok. I'm not sure of any other restrictions. Spaces are probably unwise " ", but I've not tested that. Regards -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb refdes name restrictions?
Another dumb question. I teach a class of undergraduates about ECAD and this year abandoned commercial tools in favour of geda. Students being students, they tend to try things I wouldn't think of doing. Today, a couple of them decided to be creative and on their schematic used names like "CONNpower" and "CONNsignal" for refdes values. Whilst I thought it unconventional and probably inadvisable, I couldn't offhand see why they shouldn't do that. Gsch2pcb happily produced a netlist and pcb file which both looked fine, as far as I could tell. But when loaded into pcb, optimising the netlist causes error messages such as "Can't find CONN pin 4 called for in netlist". So does pcb require that all reference designators be in the form of a string followed by a numerical value? If so, are there any other refdes restrictions I should know about? Given time, they're bound to find them... Thanks, PB ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Haunted BF982
Karel Kulhavy wrote: I was wondering why something is limiting the bandwidth of my 1MHz square signal from the bottom so the square wave had higher beginning and lower end (significantly). Do you have a picture of the waveform you can post? I figured out it is caused by the BF982 transistor. The signal at the input gate is fine, on the output (which is drain directly into a 220 ohm load), it is already deformed. The source is nailed to the ground. The transistor has tons of headroom and runs from 12V. It happens even on microscopically small signals. The operating point of G1 is in the middle of it's almost-linear space, the G2 is at full amplification point at 4V, amply blocked to the ground with total of 100nF. Have you probed G2 just to be sure it isn't moving around? Vds max is 12 V on that device, I might be a bit nervous with a supply that hits that limit. The transistor was disconnected from the rest of the amplifier, isolated, nothing was connected to the 200 Ohm workload. Is it possible that as the transistor is optimized for 300MHz or 800MHz operation, they actually managed to make it start amplifying a bit less from 150kHz downwards? Not that I know of but I have very little experience in actually using dual gate FET's. As I couldn't find any physical cause that I could control, I implemented a compensation for the deformation in the next stage and now the wave is nicely level. The compensation turns out to be perfect when calculated for 150kHz simple RC high-pass. I think I saw this effect in another receiver populated by BF988, too. By any chance do things, like the 150 kHz frequency, change if you stick a heatsink on that transistor? For the purposes of this test, it doesn't need to be attached very well mechanically as long as its connected thermally. I'm thinking of just a drop of thermal grease with a large enough piece of aluminum stuck on top. "Large enough" would be something that appreciably changes the thermal system. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: BC547 vs. 2N3904
> Do you like more BC547C for higher frequency applications or 2N3904? > I once did a simulation for some Ronja differential limiting amplifier > which showed that BC547C is a bit better than 2N3904 because, despite > it being lazy, it has higher amplification. Yo can also use BF240 (SMD variant BF840) if you want to amplify up to some 50MHz or even BFR91 (SMD=> BFR93) if faster transistors are needed. Those transistors cannot be used for saturated switching. For such case try old 2N2369 or its derivatives (plastic or SMD). But faster the transistor, more likely it oscillates. > > Is it possible to get rid of oscillating transistors by replacing the > hand-soldered airwire with a SMD on a 2-sided PCB with a ground-plane? Very recommended. Use shortest possible connections to ground and try not to cut the ground plane with traces, especially long. > > What is the major cause of oscillations in high-frequency amplifiers? > Inductance of wires? If your circuit oscillates well above the operating frequency it is mainly due to inductance of wires plus parasitic capacitances inside the transistor. The input-output capacitance is major cause of instability of resonant apmlifiers (RF or IF) In this case oscillations are at or near operating frequency. Sometimes amplifiers oscillate on LF due to bad supply decoupling. > Wojciech Kazubski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Current source rail blocking
Karel Kulhavy wrote: gn Sun, Oct 29, 2006 at 07:09:46PM -0500, Dan McMahill wrote: Karel Kulhavy wrote: Hello In my broadband high sensitivity amplifier I have a rail where bases of all current source transistors are hooked up. Each current source is a transistor with an emitter resistor which compensates variance in aplification so that even unmatched transistors produce matched currents. Do you have any recommendations how to block the current sources from picking up some garbage from the air and causing oscillation? Should I block the rail with a single big capacitor against the ground, or use individual capacitor for each transistor placed between emitter and base? What sort of transistors are these? Are you seeing oscillations in 2N3904 practice or is this just a concern prior to seeing any real hardware? In practice. I'd avoid using transistors which are faster than need be. For example, sticking a 20 GHz device in there may not be a good idea. If you can tolerate some additional noise, you can stick some resistance in series with the base if the transistors themselves are oscillating. Why does this help? Slows down the transistor by forming an RC lowpass with the inherent E-B capacitance of the transistor? Calculate the impedance seen looking into the base of a common emitter stage that has capacitance from emitter to ground. If you have capacitance to ground at the emitter, then there is an impedance proportional to 1/j*w there. Now refer that to the base side. At higher frequencies, the transistor current gain is falling off with frequency so now you get a 1/(j*w)^2 term in the impedance looking into the base. When you actually work out the math, you'll get some expression that will have a capacitive term along with a *negative* resistance term. Combine that with some inductance (from the board layout, package leads, etc) and you have an oscillator. The series R serves to produce a net positive resistance. Is it possible to hook up a test circuit with the parasitics in gnucap and run it and see it if it oscillates? Or is it just going to say "internal node open" or fail to converge? It should be very easy to simulate the negative input resistance. This is also easy to calculate by hand. To simulate oscillations you'll need to be sure you have a correct model for whatever parasitic inductance you may have in the base circuit. BTW how does the reality work that it always converges? Is it possible to build a real electronic circuit that causes the universe to fail to converge and be terminated with an error message? If not, why isn't the same calculation that is used to run the universe just put into gnucap so it would converge every time? Does gnucap convergence failure indicate the circuit would oscillate? Does an oscillator circuit in gnucap always cause convergence failure on transient mode simulation? Many of my convergence problems (not speaking of gnucap but simulators in general) come from bad inputs. Reality usually doesn't include an ideal 1F capacitor or an inductor with no loss. Reality usually doesn't include a voltage coefficient on some element which causes a stable operating point with internal voltages outside the supply. Certainly a simulator can mess up too, but it's pretty easy to feed them a model which does not reflect reality. Well, I want to build a current source from a single 2N3904 (or a double one if it's a current mirror where the driving half can be recycled for multiple mirrors) that gives 2.5mA constant current and behaves like a current mirror to as high frequencies as possible (i. e. not something that is nicely stable but from 10kHz up it starts behaving like a capacitor instead of current source). How would you do it? When you say behaves like a current mirror to as high freq. as possible, do you mean Iout/Iin is wideband or that the impedance looking into the output is as high as possible? Your basic approach you already described is fine. I'd just pay particular attention to the potential for instability. This means don't add extra C to ground from the emitter and maybe leave room in your layout for some series R in the bases. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: BC547 vs. 2N3904
Karel Kulhavy wrote: > Do you like more BC547C for higher frequency applications or > 2N3904? Not sure if everyone knows: Usegroup sci.electronics.design (and de.sci.electronics) exists. In my opinion this is the perfect location to discuss general electronics topics. Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Haunted BF982
I was wondering why something is limiting the bandwidth of my 1MHz square signal from the bottom so the square wave had higher beginning and lower end (significantly). I figured out it is caused by the BF982 transistor. The signal at the input gate is fine, on the output (which is drain directly into a 220 ohm load), it is already deformed. The source is nailed to the ground. The transistor has tons of headroom and runs from 12V. It happens even on microscopically small signals. The operating point of G1 is in the middle of it's almost-linear space, the G2 is at full amplification point at 4V, amply blocked to the ground with total of 100nF. The transistor was disconnected from the rest of the amplifier, isolated, nothing was connected to the 200 Ohm workload. Is it possible that as the transistor is optimized for 300MHz or 800MHz operation, they actually managed to make it start amplifying a bit less from 150kHz downwards? As I couldn't find any physical cause that I could control, I implemented a compensation for the deformation in the next stage and now the wave is nicely level. The compensation turns out to be perfect when calculated for 150kHz simple RC high-pass. I think I saw this effect in another receiver populated by BF988, too. CL< ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: BC547 vs. 2N3904
Do you like more BC547C for higher frequency applications or 2N3904? I once did a simulation for some Ronja differential limiting amplifier which showed that BC547C is a bit better than 2N3904 because, despite it being lazy, it has higher amplification. Is it possible to get rid of oscillating transistors by replacing the hand-soldered airwire with a SMD on a 2-sided PCB with a ground-plane? What is the major cause of oscillations in high-frequency amplifiers? Inductance of wires? CL< ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Current source rail blocking
gn Sun, Oct 29, 2006 at 07:09:46PM -0500, Dan McMahill wrote: > Karel Kulhavy wrote: > >Hello > > > >In my broadband high sensitivity amplifier I have a rail where bases of all > >current source transistors are hooked up. Each current source is a > >transistor > >with an emitter resistor which compensates variance in aplification so that > >even unmatched transistors produce matched currents. > > > >Do you have any recommendations how to block the current sources from > >picking > >up some garbage from the air and causing oscillation? Should I block the > >rail > >with a single big capacitor against the ground, or use individual > >capacitor for > >each transistor placed between emitter and base? > > What sort of transistors are these? Are you seeing oscillations in 2N3904 > practice or is this just a concern prior to seeing any real hardware? In practice. > I'd avoid using transistors which are faster than need be. For example, > sticking a 20 GHz device in there may not be a good idea. > > If you can tolerate some additional noise, you can stick some resistance > in series with the base if the transistors themselves are oscillating. Why does this help? Slows down the transistor by forming an RC lowpass with the inherent E-B capacitance of the transistor? The problem here is that I want the amplifier has to be fast (preserve nice sharp edges in the signal), broadband (from 1MHz to 10MHz without noticeable frequency deformation) and low noise (i. e. the collector current has to be kept low otherwise I get too much shot noise). > If you have some extra capacitance on the emitter and some inductance in With capacitance on emitter do you mean capacitor between E and B or between E and GND? > the base circuit (without much extra resistive loss), then it's not too > hard to build an oscillator. Without knowing some more details anything Is it possible to hook up a test circuit with the parasitics in gnucap and run it and see it if it oscillates? Or is it just going to say "internal node open" or fail to converge? BTW how does the reality work that it always converges? Is it possible to build a real electronic circuit that causes the universe to fail to converge and be terminated with an error message? If not, why isn't the same calculation that is used to run the universe just put into gnucap so it would converge every time? Does gnucap convergence failure indicate the circuit would oscillate? Does an oscillator circuit in gnucap always cause convergence failure on transient mode simulation? > else would be pure speculation. Well, I want to build a current source from a single 2N3904 (or a double one if it's a current mirror where the driving half can be recycled for multiple mirrors) that gives 2.5mA constant current and behaves like a current mirror to as high frequencies as possible (i. e. not something that is nicely stable but from 10kHz up it starts behaving like a capacitor instead of current source). How would you do it? Is it possible to test stability of a current source itself without connecting the rest of the circuit? What is the most poisonous load possible for a BJT-based current source? A resistor? A capacitor? An inductor? Is it possible to improve high-frequency current source behaviour by putting an inductor in series? An inductor enforces stable current in the time short-term, doesn't it? CL< > > -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
