Re: gEDA-user: Ok, who moved pin 4?
DJ Delorie <[EMAIL PROTECTED]> writes: > First off, I've got a board that has a USB chip (FTDI232R) connected > to an R8C/20, connected to a bunch of headers. Update... It works! I had some problems programming the R8C, which turned out to be solder. I used solder wick to remove some shorts, but it sucked enough solder out to make some of the connections marginal. A swipe with the iron and a little more solder cleaned that up. I also added a pullup resistor on one signal line so I wouldn't have to program the 232R chip every time; that lets me use the stock FTDI serial drivers instead of the custom D2XX library. I've updated the web page with my changes: http://www.delorie.com/electronics/usb-gpio/ At the moment the one LED on the r8c is blinking like mad. I've plugged an RGB led board into the gpio pins; that blinks colors too. I have a symbol for the five-pin mini-B if anyone needs it, else it will show up in gedasymbols eventually. Or you can suck it out of the schematic file :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: 2 make errors installing gwave
If you have them both installed, are they in different directories or do
they have different names? If different directories, then just do
something like this
env PATH=/path/to/guile-1.6/bin:${PATH} ./configure
If they are installed in the same place but with different names,
/usr/local/bin/guile and /usr/local/bin/guile16 for example, then you
need to edit that build.. script and change the call at the top from
guile to guile16.
-Dan
Robert Butts wrote:
> Dan is correct in that I have guile-1.6 and 1.8 installed. It was
> suggested that I install 1.6 and see if it would run with 1.8. My
> question is can I remove 1.8 without messing something else up?
>
> On Nov 28, 2007 6:00 PM, al davis <[EMAIL PROTECTED]
> > wrote:
>
> On Wednesday 28 November 2007, Robert Butts wrote:
> > 'm trying to install gwave-20060606 on my system which is
> > Fedora 7, i386. I created a temporary directory and unpacked
> > gwave. I configured gwave with no faults but got 2 make
> > errors.
>
> Most likely you have guile-1.8 installed. You need guile-1.6.
> On debian the package needed is "guile-1.6-dev".
>
>
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Re: gEDA-user: 2 make errors installing gwave
Dan is correct in that I have guile-1.6 and 1.8 installed. It was suggested that I install 1.6 and see if it would run with 1.8. My question is can I remove 1.8 without messing something else up? On Nov 28, 2007 6:00 PM, al davis <[EMAIL PROTECTED]> wrote: > On Wednesday 28 November 2007, Robert Butts wrote: > > 'm trying to install gwave-20060606 on my system which is > > Fedora 7, i386. I created a temporary directory and unpacked > > gwave. I configured gwave with no faults but got 2 make > > errors. > > Most likely you have guile-1.8 installed. You need guile-1.6. > On debian the package needed is "guile-1.6-dev". > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
Peter, My work is heavily derived from geda. If it makes sense for the main geda project to merge my efforts back in then I am very happy to to have contributed. Steve Meier Peter Clifton wrote: > On Wed, 2007-11-28 at 17:43 -0800, Steve Meier wrote: > >> Just to show off what I have been working. The two attached files >> include a script for reading in a schematic file. The second is my >> attempt to document the api that either exists or that I have been >> implementing. Comments, suggestions are always welcome. If we can figure >> out the pcad file formats I would be happy to modify or tweek the api >> for the sake of translating the pcad files. >> >> Depending on interest I can do a code release either (as i had planned) >> after I have the vhdl, spice, verilog netlist formats, or earlier (after >> i complete the basic schematic, symbol file io migration to guile) and a >> trivial translation application. >> > > This is all interesting stuff, please keep us informed. > > If libgeda were to come to a similar level of tidyness, with a sane > guile binding, would you be interested to merge or combine forces? > > In any case, I'm watching this work with interest, as I'm sure the we > have things to learn from each other. > > All the best, > > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-place or PCB_Parse perl module
On Nov 28, 2007 8:23 PM, Didier Villevalois <[EMAIL PROTECTED]> wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > Hi all, > > I've read > there:http://www.luciani.org/not-quite-ready/not-quite-ready-index.html > and on the mailing-list there is tool developped by JC Luciani to place > components from a position configuration file. However i can't get an > hand on it... > > I would really need that tool to help me for my front panel pcbs. Or > maybe just the PCB_Parse perl module so that i don't have to make > another parser/serializer to place my components. I am assuming you saw the write-up I presented a few years ago at a Freedog meeting. I placed the write-up on my site but never got around to posting the script. If you have read write-up and you think the script will meet your needs I could dust it off and place on my site either this weekend or early next week. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
John Doty wrote: >>> It'd >>> be nice if you could draw a subcircuit and just have the IO pins turn >>> into a simple boxsym automatically. > OK, same question, different emphasis: how does Cadence know how to > arrange the pins? Sorry I didn't answer that at first. IIRC it just took schematic yaxis value to choose vertical order, and left or right of schematic midlplane to determine left or right. You could then instantiate the symbol just generated, then "dive into" edit it to change the order and grouping and box size if desired by GUI methods. For things with short names and few enough ports, it was useful. It's obviously best to specify busses and so use bus ports to keep things managably compact. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
On Wed, 2007-11-28 at 17:43 -0800, Steve Meier wrote: > Just to show off what I have been working. The two attached files > include a script for reading in a schematic file. The second is my > attempt to document the api that either exists or that I have been > implementing. Comments, suggestions are always welcome. If we can figure > out the pcad file formats I would be happy to modify or tweek the api > for the sake of translating the pcad files. > > Depending on interest I can do a code release either (as i had planned) > after I have the vhdl, spice, verilog netlist formats, or earlier (after > i complete the basic schematic, symbol file io migration to guile) and a > trivial translation application. This is all interesting stuff, please keep us informed. If libgeda were to come to a similar level of tidyness, with a sane guile binding, would you be interested to merge or combine forces? In any case, I'm watching this work with interest, as I'm sure the we have things to learn from each other. All the best, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Strange issue with images and printing
On Wed, 2007-11-28 at 19:12 -0700, Steven Ball wrote: > > Howdy guys, > > I'd noted this before, but it had been a while and it still seems to > be an issue. > > If I place an image, say, a logo, on my schematic, if I do not zoom in > on it before printing, gschem will print it very blocky, like it > scales it to what it is currently set to on the screen inside of > scaling it properly for print. > > Confused? > > OK, if I zoom extents, and print, the resultant print (or postscript) > ends up with a chunky, distorted image. > > If I zoom in such that the image completely fills my screen, and print > again, the image comes out looking perfect. > > Wonder what does that? Can you file a bug report please.. http://sourceforge.net/tracker/?group_id=161080&atid=818426 I suspect its scaling the on-screen version it's scaled for the screen, rather than trying to scale the original image. Thanks, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Strange issue with images and printing
Howdy guys, I'd noted this before, but it had been a while and it still seems to be an issue. If I place an image, say, a logo, on my schematic, if I do not zoom in on it before printing, gschem will print it very blocky, like it scales it to what it is currently set to on the screen inside of scaling it properly for print. Confused? OK, if I zoom extents, and print, the resultant print (or postscript) ends up with a chunky, distorted image. If I zoom in such that the image completely fills my screen, and print again, the image comes out looking perfect. Wonder what does that? -Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: Simple text-substitution macros for textlabels?
I was just looking into this myself. You have to explicitly tell SVN that it can modify your file by setting the svn:keywords property, ie: $ svn propset svn:keywords "LastChangedDate Author" schematic.sch Of course, I have not tested, but this is what the docs at http://svnbook.red-bean.com/en/1.0/ch07s02.html say. On Nov 28, 2007, at 6:31 PM, Jose, Marshall wrote: > I must be pretty dense, because I've never figured out how to get > SVN to put the save-date and the filename into the text within the > title-block of a gschem .SCH file. Is there some sort of tutorial on > how to accomplish this? > > Thanks, > Marshall > > > -Original Message- > From: [EMAIL PROTECTED] on behalf of Steven Michalske > Sent: Wed 11/28/2007 4:59 PM > To: gEDA user mailing list > Subject: Re: gEDA-user: gschem: Simple text-substitution macros for > textlabels? > > I use SVN with my schematics and layouts to provide revision history > and backup. > > you can use keywords in SVN CVS and many other source control systems. > > Steve > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
Just to show off what I have been working. The two attached files
include a script for reading in a schematic file. The second is my
attempt to document the api that either exists or that I have been
implementing. Comments, suggestions are always welcome. If we can figure
out the pcad file formats I would be happy to modify or tweek the api
for the sake of translating the pcad files.
Depending on interest I can do a code release either (as i had planned)
after I have the vhdl, spice, verilog netlist formats, or earlier (after
i complete the basic schematic, symbol file io migration to guile) and a
trivial translation application.
Steve Meier
Dan McMahill wrote:
> Steven Ball wrote:
>
>> The PDIF writer seems to be able to convert anything to an ASCII output.
>>
>> http://snurkle.net/~hamster/geda/
>>
>
> By any chance does the documentation for PCAD have details on that
> format? If not, it looks like it could largely be figured out.
>
>
>> I'll dig around and see if I can find a .pcb file to convert and post
>> as well. Let me know what you think and how I can be of help.
>>
>
> just to clarify, pcad uses .pcb too as the suffix. The format you'll
> get there is similar in style to the schematics.
>
>
>
>
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>
;;; AKEDA - Alaskan Electronic Design Automation
;;; aknetlist - GNU Netlist
;;; Copyright (C) 2007 Stephen F Meier
;;;
;;; This program is free software; you can redistribute it and/or modify
;;; it under the terms of the GNU General Public License as published by
;;; the Free Software Foundation; either version 2 of the License, or
;;; (at your option) any later version.
;;;
;;; This program is distributed in the hope that it will be useful,
;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;;; GNU General Public License for more details.
;;;
;;; You should have received a copy of the GNU General Public License
;;; along with this program; if not, write to the Free Software
;;; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
;; Inport an AKEDA style schematic as a page in libakeda
(use-modules (srfi srfi-13))
(use-modules (ice-9 popen))
(use-modules (ice-9 rdelim))
(define OBJ_LINE"L" );
(define OBJ_BOX "B" );
(define OBJ_PICTURE "G" );
(define OBJ_CIRCLE "V" );
(define OBJ_NET_SEGMENT "N" );
(define OBJ_BUS_SEGMENT "U" );
(define OBJ_COMPLEX "C" );
(define OBJ_TEXT"T" );
(define OBJ_PIN "P" );
(define OBJ_ARC "A" );
(define OBJ_ROUTE "R" );
(define OBJ_THRU_HOLE "H" );
(define OBJ_BUSRIPPER "S" );
(define OBJ_EMPTY "0" );
(define OBJ_VERSION "v" );
(define OBJ_PLACEHOLDER "X" );
(define STARTATTACH_ATTR "{" );
(define ENDATTACH_ATTR "}" );
(define START_EMBEDDED "[" );
(define END_EMBEDDED "]" );
(define (akeda-sch-read sch-filename tl_bool)
(let ((port (open-input-file sch-filename)))
(define my_page (ak-toplevel-new-page sch-filename tl_bool))
(define buffer "")
(define buf_str "")
(define my_line "")
(define new_obj_smob "")
(define attach_obj_smob "")
(define embed_obj_smob "")
(define str_list "")
(define my_string "")
(define index 0)
(define num_lines 0)
(define selected "0")
(define visible "0")
(define locked "0")
(define schematic_attrib_type "1")
(define symbol_attrib_type "0")
(define state_attach #f)
(define state_embed #f)
(define state_text #f)
(define x2 0)
(define y2 0)
(while (not (eof-object? buf_str))
(set! buffer (%read-line port))
(set! buf_str (car buffer))
(if (not (eof-object? buf_str))
(begin
(set! my_line (string-split buf_str #\space))
(if (string=? (list-ref my_line 0) STARTATTACH_ATTR)
(begin
(set! state_attach #t)
(set! attach_obj_smob new_obj_smob)
)
)
(if (string=? (list-ref my_line 0) ENDATTACH_ATTR)
(begin
(set! state_attach #f)
)
)
(if (string=? (list-ref my_line 0) START_EMBEDDED)
(begin
(set! state_embed #t)
(set! embed_obj_smob new_obj_smob)
)
)
(if (string=? (list-ref my_line 0) END_EMBEDDED)
(begin
(set! state_embed #f)
)
)
(if (string=? (list-ref my_line 0) OBJ_TEXT)
(begin
(set! new_obj_smob (ak-object-new OBJ_TEXT selected visible locked))
(ak-text-new new_obj_smob (list-ref my_line 1) (list-ref my_line 2) (list-ref my_line 4) (list-ref my_line 8)
(list-ref my_line 7) (list-ref my_line 9) (list-ref my_line 5) (list-ref my_line 6) (list-ref my_line 3))
(set! index 0)
(set! n
Re: gEDA-user: [RFC/PATCH] Nicer names for default component libs
On Thu, 2007-11-29 at 10:29 +0900, John Doty wrote:
> > ("transistor" "Misc. transistors")
> > "Transistors"?
>
> What's the problem?
It messes up the logical sort order, "T" for transistors, not "M"
> >
> > ("io" "Generic input/output")
> > "Input / output"?
>
> Suggest an alternative.
Notice I did, "Input / Output".
Just drop the "Generic" and "Misc" prefixes, they add un-necessarily
clutter to the list, consume horizontal real-estate, and mess up the
sort order.
> > (You might then consider "Relays (Tyco)", or just sticking them all
> > into
> > "Relays").
>
> What do you want here? *Any* classification scheme is going to be
> flawed. We have classifications by technology, manufacturer,
> modularization (think "74"), function, etc. Which one is right? Find
> five users, get a dozen opinions. Maybe the library installer should
> make some links...
Sure, anything is going to be flawed, I was merely voicing an idea to
have similar things get sorted close to each other, e.g.:
Relays (Other)
Relays (Tyco)
As opposed to:
...
Misc. relays
...
Tyco relays
...
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
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Re: gEDA-user: gschem: Simple text-substitution macros for textlabels?
I must be pretty dense, because I've never figured out how to get SVN to put the save-date and the filename into the text within the title-block of a gschem .SCH file. Is there some sort of tutorial on how to accomplish this? Thanks, Marshall -Original Message- From: [EMAIL PROTECTED] on behalf of Steven Michalske Sent: Wed 11/28/2007 4:59 PM To: gEDA user mailing list Subject: Re: gEDA-user: gschem: Simple text-substitution macros for textlabels? I use SVN with my schematics and layouts to provide revision history and backup. you can use keywords in SVN CVS and many other source control systems. Steve <> ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [RFC/PATCH] Nicer names for default component libs
On Nov 29, 2007, at 10:08 AM, Peter Clifton wrote:
>
> On Wed, 2007-11-28 at 21:20 +, Peter TB Brett wrote:
>> Hi folks,
>>
>> The attached patch uses some functionality I added a few months
>> ago to change
>> the names presented in the component dialog box to something less
>> offensively
>> cryptic.
>>
>> Comments appreciated.
>
> I think it looks a lot nicer, but I don't like:
>
> ("analog" "Generic basic devices")
> (Are most of these "Passives"?)
Some are not. Maybe call this "basics".
>
> ("misc" "Misc. unsorted symbols")
> Urg... of the misc. prefixes, this is probably the one which could
> stay.
>
> ("power" "Generic power rails")
> "Power rails"?
"Power connection symbols"?
>
> ("transistor" "Misc. transistors")
> "Transistors"?
What's the problem?
>
> ("io" "Generic input/output")
> "Input / output"?
Suggest an alternative.
>
> ("titleblock" "Generic titleblocks")
> "Titleblocks"?
Suggest an alternative.
>
> etc.
>
> ("memory" "Misc. memory devices")
> ("micro" "Misc. microcontrollers")
> ("radio" "Generic radio elements")
> ("tube" "Misc. vacuum tubes")
> ("connector" "Generic connectors")
> ("switch" "Generic switches")
> ("rf" "Misc. RF elements")
> ("pla" "Misc. programmable logic arrays")
> ("supervisor" "Misc. microprocessor supervisors")
> ("opto" "Misc. optocouplers")
> ("diode" "Generic diodes")
> ("relay" "Misc. relays")
>
> IE. the "Misc." and "Generic" prefixing is bad. If any categories are
> ambigious / repeated with commercial vendors, you could postfix..
>
> e.g.
>
> "Diodes (other)"
> "FPGAs (misc)"
>
> or whatever.
>
> There is of course a danger of feeling symbols don't exist, e.g. if
> the
> user is looking for a relay under "Relays", and misses the ones under
> the manufacturer, e.g. "Tyco"
>
> (You might then consider "Relays (Tyco)", or just sticking them all
> into
> "Relays").
What do you want here? *Any* classification scheme is going to be
flawed. We have classifications by technology, manufacturer,
modularization (think "74"), function, etc. Which one is right? Find
five users, get a dozen opinions. Maybe the library installer should
make some links...
>
> Just some random thoughts, otherwise a very good patch.
>
> Best wishes,
>
> --
> Peter Clifton
>
> Electrical Engineering Division,
> Engineering Department,
> University of Cambridge,
> 9, JJ Thomson Avenue,
> Cambridge
> CB3 0FA
>
> Tel: +44 (0)7729 980173 - (No signal in the lab!)
>
>
>
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John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
[EMAIL PROTECTED]
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Re: gEDA-user: pcb-place or PCB_Parse perl module
On Thu, Nov 29, 2007 at 02:23:48AM +0100, Didier Villevalois wrote: > and on the mailing-list there is tool developped by JC Luciani to place > components from a position configuration file. However i can't get an > hand on it... Not exactly the answer you're looking for, but I wrote a distribute/align plugin which might help you with front panel layout (for example, if you place a few reference components carefully, you can easily use Align to set X or Y coordinates on other objects to match). I also wrote an autocrop plugin which has a very clear example of how to move every kind of element, which may be of use to you. You can find both from gedasymbols.org. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb-place or PCB_Parse perl module
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi all, I've read there:http://www.luciani.org/not-quite-ready/not-quite-ready-index.html and on the mailing-list there is tool developped by JC Luciani to place components from a position configuration file. However i can't get an hand on it... I would really need that tool to help me for my front panel pcbs. Or maybe just the PCB_Parse perl module so that i don't have to make another parser/serializer to place my components. Thanks for your help. Didier. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.7 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHThSkVE1mALQL3JsRApPlAJ4+oUOnUvU86UKB+SQMyCZ6Xwp16wCZAXkV nckbBp7dqXrI6SnNzqtAy6Q= =4zE/ -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: "shrink" and overlapping copper areas
In the days of mechanical photoplotting, having an aperture be exposed to small causes the problems you're thinking of. Or, if you have a situation like that and you globally change the size of all lines, for example. Me, I think the bloat/shrink stuff is way obsolete. We need to strip out that DRC and put in a new one that uses current terminology. Of course, the ps exporter *has* a bloat option. Me, I'd set the board's shrink to match my ps bloat, so if I "bloat" the ps lines smaller (as I do, to match my process), they remain connected. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: "shrink" and overlapping copper areas
The PCB DRC tests for 'shrink' compliance by looking for copper areas that stop touching if you draw the individual parts smaller by 'shrink' mil. My question is: Is this a realistic model of how manufacturing 'shrink' would really affect overlapping copper areas? What first led me to notice this was a via I placed which overlapped a SMT pad. The annulus of the via was solidly over the edge of the pad. The DRC would complain, because in its model, the annulus could shrink AND the pad could shrink and the result would not touch. If I connected them with a wire, I was okay. Rendered as 'ideal' sized pieces, the overlap of the via and pad was wider than the connecting wire, but since the code modelled the pad and via as capable of shrinking independently, the wire was required. So if you imagined a square pad made of up four adjoining squares (easy to do with polygons, in fact), the result is indistinguishable onscreen from one BIG square, but the DRC thinks that due to manufacturing, the sub-squares could shrink individually and quit touching. Is this really true? Or should any copper areas (regardless of how they came to be) shrink only around the outermost periphery? -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [RFC/PATCH] Nicer names for default component libs
On Wed, 2007-11-28 at 21:20 +, Peter TB Brett wrote:
> Hi folks,
>
> The attached patch uses some functionality I added a few months ago to change
> the names presented in the component dialog box to something less offensively
> cryptic.
>
> Comments appreciated.
I think it looks a lot nicer, but I don't like:
("analog" "Generic basic devices")
(Are most of these "Passives"?)
("misc" "Misc. unsorted symbols")
Urg... of the misc. prefixes, this is probably the one which could stay.
("power" "Generic power rails")
"Power rails"?
("transistor" "Misc. transistors")
"Transistors"?
("io" "Generic input/output")
"Input / output"?
("titleblock" "Generic titleblocks")
"Titleblocks"?
etc.
("memory" "Misc. memory devices")
("micro" "Misc. microcontrollers")
("radio" "Generic radio elements")
("tube" "Misc. vacuum tubes")
("connector" "Generic connectors")
("switch" "Generic switches")
("rf" "Misc. RF elements")
("pla" "Misc. programmable logic arrays")
("supervisor" "Misc. microprocessor supervisors")
("opto" "Misc. optocouplers")
("diode" "Generic diodes")
("relay" "Misc. relays")
IE. the "Misc." and "Generic" prefixing is bad. If any categories are
ambigious / repeated with commercial vendors, you could postfix..
e.g.
"Diodes (other)"
"FPGAs (misc)"
or whatever.
There is of course a danger of feeling symbols don't exist, e.g. if the
user is looking for a relay under "Relays", and misses the ones under
the manufacturer, e.g. "Tyco"
(You might then consider "Relays (Tyco)", or just sticking them all into
"Relays").
Just some random thoughts, otherwise a very good patch.
Best wishes,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
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Re: gEDA-user: PCAD to GEDA (GSCHEM)
Steven Ball wrote: > The PDIF writer seems to be able to convert anything to an ASCII output. > > http://snurkle.net/~hamster/geda/ By any chance does the documentation for PCAD have details on that format? If not, it looks like it could largely be figured out. > I'll dig around and see if I can find a .pcb file to convert and post > as well. Let me know what you think and how I can be of help. just to clarify, pcad uses .pcb too as the suffix. The format you'll get there is similar in style to the schematics. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Nov 28, 2007, at 1:49 PM, Ben Jackson wrote: > On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller > wrote: >> >> We've discovered that the clock generators in the Xilinx FPGA part >> are >> lousy for generating video clocks. > > DCMs have lousy jitter, yes. Indeed. The Spartan 3E claims +/- 100 ps jitter on the DCM's CLK0 (in- phase) output and +/- 150 ps on the CLK90, CLK180 and CLK270 (phase- shifted) outputs. The clock-doubler outputs claim +/- 1% of the clock- in period + 150 ps jitter. When doing integer division, the CLKDV outputs claim +/- 150 ps jitter. When doing non-integral division, the CLKDV output claims +/- 1% of the clock-in period + 200 ps jitter. Then when one reads the footnotes, one learns that these numbers are in addition to any input clock jitter. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Forwarding?
On Thursday 29 November 2007 00:11:09 Timothy Normand Miller wrote: > On 11/28/07, Peter Clifton <[EMAIL PROTECTED]> wrote: > > On Wed, 2007-11-28 at 14:21 -0500, Timothy Normand Miller wrote: > > > Does this list forward automatically to gEDA-dev? > > > > No, although most of the geda-dev subscribers will probably be > > subscribed to geda-user. > > Ok. Because when I posted to both gEDA-dev and gEDA-user, I got back > THREE emails, one of which had both gEDA-dev and gEDA-user prepended > to the subject. Odd. Yeah, I've noticed it too when I've sent mail to both lists occasionally. No doubt the answer is, "Well don't do that then!" Peter ;) -- Peter Brett Electronic Systems Engineer Integral Informatics Ltd signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Forwarding?
On 11/28/07, Peter Clifton <[EMAIL PROTECTED]> wrote: > > On Wed, 2007-11-28 at 14:21 -0500, Timothy Normand Miller wrote: > > Does this list forward automatically to gEDA-dev? > > No, although most of the geda-dev subscribers will probably be > subscribed to geda-user. Ok. Because when I posted to both gEDA-dev and gEDA-user, I got back THREE emails, one of which had both gEDA-dev and gEDA-user prepended to the subject. Odd. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
On Nov 29, 2007, at 8:49 AM, Dan McMahill wrote: > John Doty wrote: >> On Nov 29, 2007, at 8:05 AM, John Griessen wrote: >> >>> Ben Jackson wrote: >>> I was thinking gschem could use a 'make symbol' wizard for that. It'd be nice if you could draw a subcircuit and just have the IO pins turn into a simple boxsym automatically. It would make it much easier to build hierarchical schematics that have a nice, clear toplevel block diagram as the first sheet. >>> >>> Sure, yes, SOP using Cadence. >> >> OK, same question, different emphasis: how does Cadence know how to >> arrange the pins? >> > > you get a dialog box with a text entry for top, bottom, left, right > side. The entries come filled in by default with inputs on the left, > outputs on the right. I typically then cut/paste to which side I want > and set the order. Then the symbol is created. Users can set up > default symbol templates too in case there is a standard set of things > you want created. In the geda world it might be a set of > attributes and > their visibility. > > It works pretty well as a starting point. OK, rather like tragesym, but with automatic label generation. That would be nice to have. > > The "create cellview from cellview" thing in cadence can go from > symbol > or schematic to schematic, symbol, verilog, verilog-a, etc. If you're > going from say symbol to verilog-A, you get a text editor with the > module definition line and i/o's declared and an empty body. > > -Dan > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Nov 28, 2007 11:09 AM, Timothy Normand Miller <[EMAIL PROTECTED]> wrote: > Does anyone know anything about these? Do you have experience with > specific high-frequency clock generators and know how they perform and > what kind of jitter they produce? > These are kind of like those four pin crystal oscillators except they are six pin devices, with the extra pins for i2c programmeing. Jitter specs look good. http://www.alldatasheet.com/datasheet-pdf/pdf/195314/SILABS/SI570.html -- = Chris Albertson Redondo Beach, California ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
John Doty wrote: > On Nov 29, 2007, at 8:05 AM, John Griessen wrote: > >> Ben Jackson wrote: >> >>> I was thinking gschem could use a 'make symbol' wizard for that. >>> It'd >>> be nice if you could draw a subcircuit and just have the IO pins turn >>> into a simple boxsym automatically. It would make it much easier to >>> build hierarchical schematics that have a nice, clear toplevel block >>> diagram as the first sheet. >> >> Sure, yes, SOP using Cadence. > > OK, same question, different emphasis: how does Cadence know how to > arrange the pins? > you get a dialog box with a text entry for top, bottom, left, right side. The entries come filled in by default with inputs on the left, outputs on the right. I typically then cut/paste to which side I want and set the order. Then the symbol is created. Users can set up default symbol templates too in case there is a standard set of things you want created. In the geda world it might be a set of attributes and their visibility. It works pretty well as a starting point. The "create cellview from cellview" thing in cadence can go from symbol or schematic to schematic, symbol, verilog, verilog-a, etc. If you're going from say symbol to verilog-A, you get a text editor with the module definition line and i/o's declared and an empty body. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
On Nov 28, 2007 5:01 PM, Steven Ball <[EMAIL PROTECTED]> wrote: > I included all the symbols it references, > but it also seems that it embedded the symbol defs in the pdif file. > The PDF file is an actual PDF of what it looks like in PCAD. It - > appears- to be pretty straight forward. It does look straight forward just a *lot* of details ;-) The embedded symbols could be helpful to a translator program. Everytime you see "COMP_DEF" the translator program could create a gschem symbol using the PCAD symbol definition. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
On Nov 29, 2007, at 8:05 AM, John Griessen wrote: > Ben Jackson wrote: > >> I was thinking gschem could use a 'make symbol' wizard for that. >> It'd >> be nice if you could draw a subcircuit and just have the IO pins turn >> into a simple boxsym automatically. It would make it much easier to >> build hierarchical schematics that have a nice, clear toplevel block >> diagram as the first sheet. > > > Sure, yes, SOP using Cadence. OK, same question, different emphasis: how does Cadence know how to arrange the pins? John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
Hi Ben, Have a look at: http://sourceforge.net/tracker/index.php?func=detail&aid=1800913&group_id=161080&atid=818428 Kind regards, Bert Timmerman. On Wed, 2007-11-28 at 13:49 -0800, Ben Jackson wrote: > On Thu, Nov 29, 2007 at 06:46:02AM +0900, John Doty wrote: > > > > Make a symbol representing the subcircuit. Include the attribute > > source=whatever.sch, where whatever.sch is the schematic of the > > subcircuit. In whatever.sch, attach input and output symbols from the > > "io" symbol library. > > I was thinking gschem could use a 'make symbol' wizard for that. It'd > be nice if you could draw a subcircuit and just have the IO pins turn > into a simple boxsym automatically. It would make it much easier to > build hierarchical schematics that have a nice, clear toplevel block > diagram as the first sheet. > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Nov 28, 2007, at 4:02 PM, Larry Doolittle wrote: >> That's kind of surprising, because the DVI spec has a bitrate 10x the >> fundamental clock, so both the transmitter and receiver generally have >> to have PLLs. > > Just the receiver, right? And that cable length comment makes me > suspicious something more subtle is going on. Impedance mismatch and reflections, possibly? -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
Ben Jackson wrote: > I was thinking gschem could use a 'make symbol' wizard for that. It'd > be nice if you could draw a subcircuit and just have the IO pins turn > into a simple boxsym automatically. It would make it much easier to > build hierarchical schematics that have a nice, clear toplevel block > diagram as the first sheet. Sure, yes, SOP using Cadence. JG -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: 2 make errors installing gwave
On Wednesday 28 November 2007, Robert Butts wrote: > 'm trying to install gwave-20060606 on my system which is > Fedora 7, i386. I created a temporary directory and unpacked > gwave. I configured gwave with no faults but got 2 make > errors. Most likely you have guile-1.8 installed. You need guile-1.6. On debian the package needed is "guile-1.6-dev". ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: 2 make errors installing gwave
Robert Butts wrote:
> I'm trying to install gwave-20060606 on my system which is Fedora 7,
> i386. I created a temporary directory and unpacked gwave. I configured
> gwave with no faults but got 2 make errors. I have attached two text
> files, the ./configure output and the make output..
>
> Thanks
>
configure failed:
checking for guile-gtk CFLAGS... Backtrace:
In /usr/bin/build-guil
e-gtk:
105: 0* (define-module (build-guile-gtk) #{:use-module}# ...)
105: 1 (eval-case (# #) (else #))
In unknown file:
...
?: 2 (let ((m (process-define-module #))) (set-current-module m) m)
?: 3* [process-define-module ((build-guile-gtk) #:use-module (#) ...)]
?: 4 (let* (# # # #) (beautify-user-module! module) (letrec # #) ...)
?: 5* (letrec ((loop (lambda # #))) (loop kws (quote ()) (quote ())
(quote (
?: 6 [loop (#:use-module ((gtk-1.2 config)) #:use-module ...) () ...]
...
?: 7 (let* ((interface-args #) (interface #)) (and (eq? # #) (or #
#) ...) ...)
?: 8* [apply # ((gtk-1.2
config))]
?: 9 [resolve-interface (gtk-1.2 config)]
...
?: 10 (let* (# # # #) (and # #) (if # public-i #))
?: 11* (and (or (not module) (not public-i)) (error "no code for
module" name))
?: 12 [error "no code for module" (gtk-1.2 config)]
...
?: 13 [scm-error misc-error #f ...]
: In procedure scm-error in expression (scm-error (quote
misc-error) #f ...):
: no code for module (gtk-1.2 config)
Try running:
build-guile-gtk cflags
once you figure out how to make that work, you'll be good. My guess is
perhaps you have more than one version of guile installed and the wrong
guile is being picked for build-guile-gtk. You may have to muck with
your PATH to pick out the right one.
-Dan
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gEDA-user: 2 make errors installing gwave
I'm trying to install gwave-20060606 on my system which is Fedora 7, i386. I created a temporary directory and unpacked gwave. I configured gwave with no faults but got 2 make errors. I have attached two text files, the ./configure output and the make output.. Thanks gwave configure printout Description: Binary data gwave make printout Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
On Wed, 2007-11-28 at 15:01 -0700, Steven Ball wrote: > The PDIF writer seems to be able to convert anything to an ASCII output. > > http://snurkle.net/~hamster/geda/ > > In that directory, you will find a zip file and the unzipped contents > of that file of a schematic that describes some sort of a car alarm > (easiest thing I could find off hand that I don't have to sanitize too > heavily to put on the web). I included all the symbols it references, > but it also seems that it embedded the symbol defs in the pdif file. > The PDF file is an actual PDF of what it looks like in PCAD. It - > appears- to be pretty straight forward. > > I'll dig around and see if I can find a .pcb file to convert and post > as well. Let me know what you think and how I can be of help. > > I also noted that there are ways to convert from PDIF to an OrCAD > file, and there is already an OrCAD importer of sorts. Maybe that can > be adapted? Possibly. IIRC, the OrCAD importer is for old format OrCAD files, not the newer binary mess files. Peter C. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
On Nov 29, 2007, at 6:49 AM, Ben Jackson wrote: On Thu, Nov 29, 2007 at 06:46:02AM +0900, John Doty wrote: Make a symbol representing the subcircuit. Include the attribute source=whatever.sch, where whatever.sch is the schematic of the subcircuit. In whatever.sch, attach input and output symbols from the "io" symbol library. I was thinking gschem could use a 'make symbol' wizard for that. It'd be nice if you could draw a subcircuit and just have the IO pins turn into a simple boxsym automatically. It would make it much easier to build hierarchical schematics that have a nice, clear toplevel block diagram as the first sheet. How would it know how to arrange the pins? The example symbol I posted started as a tragesym description: # This is the template file for creating symbols with tragesym # every line starting with '#' is a comment line. [options] # wordswap swaps labels if the pin is on the right side an looks like this: # "PB1 (CLK)". That's useful for micro controller port labels # rotate_labels rotates the pintext of top and bottom pins # this is useful for large symbols like FPGAs with more than 100 pins # sort_labels will sort the pins by it's labels # useful for address ports, busses, ... wordswap=yes rotate_labels=yes sort_labels=no generate_pinseq=yes sym_width=1400 pinwidthvertical=300 pinwidthhorizontal=300 [geda_attr] # name will be printed in the top of the symbol # name is only some graphical text, not an attribute # version specifies a gschem version. # if you have a device with slots, you'll have to use slot= and slotdef= # use comment= if there are special information you want to add version=20071026 name=SeqCell device=SeqCell refdes=X? footprint=unknown description=Sequencer building block documentation= author=jpd dist-license=Creative Commons Share Alike use-license=Creative Commons Share Alike numslots=0 #slot=1 #slotdef=1: #slotdef=2: #slotdef=3: #slotdef=4: #comment= #comment= #comment= [pins] # tabseparated list of pin descriptions # # pinnr is the physical number of the pin # seq is the pinseq= attribute, leave it blank if it doesn't matter # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) # style can be (line,dot,clk,dotclk,none). none if only want to add a net # posit. can be (l,r,t,b) or empty for nets # net specifies the name of the net. Vcc or GND for example. # label represents the pinlabel. # negation lines can be added with "\_" example: \_enable\_ # if you want to write a "\" use "\\" as escape sequence #- #pinnr seq typestyle posit. net label #- 1 1 in dot l \_J1A\_ 2 2 in dot l \_J1B\_ 3 3 in dot l \_K1A\_ 4 4 in dot l \_K1B\_ 5 5 in dotclk l \_CLK\_ 6 6 in dot l \_J2A\_ 7 7 in dot l \_J2B\_ 8 8 in dot l \_K2A\_ 9 9 in dot l \_K2B\_ 10 10 out liner Q1 11 11 out liner Q2 12 12 pwr linet +3.3D 13 13 pwr lineb Gnd I note that another interesting use of this gschem/gnetlist feature is to keep all of those hidden power and ground nets organized, since nets in a subcircuit instance are separate from others of the same name unless you connect them explicitly (as I did in this example). -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
The PDIF writer seems to be able to convert anything to an ASCII output. http://snurkle.net/~hamster/geda/ In that directory, you will find a zip file and the unzipped contents of that file of a schematic that describes some sort of a car alarm (easiest thing I could find off hand that I don't have to sanitize too heavily to put on the web). I included all the symbols it references, but it also seems that it embedded the symbol defs in the pdif file. The PDF file is an actual PDF of what it looks like in PCAD. It - appears- to be pretty straight forward. I'll dig around and see if I can find a .pcb file to convert and post as well. Let me know what you think and how I can be of help. I also noted that there are ways to convert from PDIF to an OrCAD file, and there is already an OrCAD importer of sorts. Maybe that can be adapted? -Steve On Nov 28, 2007, at 12:28 PM, Steve Meier wrote: > Sure post an example and see if you can convert a symbol to an ascii > format. > > Steve Meier > > On Wed, 2007-11-28 at 12:19 -0700, Steven Ball wrote: >> On Nov 28, 2007, at 11:48 AM, Steve Meier wrote: >> >>> Steven, >>> >>> Are the files in a text based format? >>> >> >> There is a text header (PC-CAPS database file version, copyright), >> and >> then the rest of the file is binary gibberish. >> >> However, running it through the 'PDIF Writer' produces a .pdf, which >> is actually a 'P-CAD Database Interchange Format' file, which is >> wholly text. >> >> Symbols are still binary, but I might be able to get them to go >> through the PDIF writer as well. >> >> Should I put up an example? I can create an actual PDF of what it >> should look like along with the binary and PDIF outputs. >> >> -Steve >> >> >> ___ >> geda-user mailing list >> geda-user@moria.seul.org >> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: Simple text-substitution macros for text labels?
I use SVN with my schematics and layouts to provide revision history and backup. you can use keywords in SVN CVS and many other source control systems. Steve On Nov 28, 2007, at 10:39 AM, Marshall Jose wrote: > How close is gschem to supporting simple macros or variables to be > included in text strings? I'm thinking about something like > > "$filesavedatetime" expands to the date and time of the most-recent > save > operation involving that current file, or > "$filename" expands to the saved file's name > > such that (e.g.) I don't have to keep editing the title-block > information with every edit. I'm not looking for CPP functionality, > just > some simple, useful substitutions. Also, IMO, applying them to > attribute > strings would just be asking for headaches. > > -- > Marshall Jose, WA3VPZ > > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
On Thu, Nov 29, 2007 at 06:46:02AM +0900, John Doty wrote: > > Make a symbol representing the subcircuit. Include the attribute > source=whatever.sch, where whatever.sch is the schematic of the > subcircuit. In whatever.sch, attach input and output symbols from the > "io" symbol library. I was thinking gschem could use a 'make symbol' wizard for that. It'd be nice if you could draw a subcircuit and just have the IO pins turn into a simple boxsym automatically. It would make it much easier to build hierarchical schematics that have a nice, clear toplevel block diagram as the first sheet. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
On Nov 28, 2007, at 11:23 PM, Klaus Rudolph wrote: Hi, I am searching for the documentation of gschem and especially for creating subcircuits with geschem. I need a subcircuit 16 times on a pcb, so I want to use that feature. Long time ago I have used it, but could not find any documentation anymore. All what I found is the geda-wiki which contains a lot of dead links and circular links to it self but not the information I need. And yes, I want it in a printable version like pdf or ps. Yes, here are two questions: 1) where is the printable documentation gone 2) how to create subcircuits for gschm->pcb toolchain. In gschem: Make a symbol representing the subcircuit. Include the attribute source=whatever.sch, where whatever.sch is the schematic of the subcircuit. In whatever.sch, attach input and output symbols from the "io" symbol library. The refdes= attributes of these symbols should match the corresponding pinlabel= attribute of the subcircuit symbol. You may then put in as many of the subcircuit symbols as you wish into your higher level design. Works with other flows, too: you're not restricted to pcb. Here's a simple example: SeqCell.sym Description: Binary data SeqCell.sch Description: Binary data John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [RFC/PATCH] Nicer names for default component libs
Hi folks,
The attached patch uses some functionality I added a few months ago to change
the names presented in the component dialog box to something less offensively
cryptic.
Comments appreciated.
Peter
--
Peter Brett
Electronic Systems Engineer
Integral Informatics Ltd
From 09ab97a2744cd3d16d1d02d9a8805038f170fd8c Mon Sep 17 00:00:00 2001
From: Peter TB Brett <[EMAIL PROTECTED]>
Date: Wed, 28 Nov 2007 21:16:46 +
Subject: [PATCH] symbols: Nicer names for default libraries
---
symbols/geda-clib.scm | 91 +---
1 files changed, 47 insertions(+), 44 deletions(-)
diff --git a/symbols/geda-clib.scm b/symbols/geda-clib.scm
index e3b33a5..c4f0460 100644
--- a/symbols/geda-clib.scm
+++ b/symbols/geda-clib.scm
@@ -10,53 +10,56 @@
; libraries.
(for-each
(lambda (dir)
- (component-library (build-path geda-sym-path dir)))
+ (if (list? dir)
+ (component-library (build-path geda-sym-path (car dir)) (cadr dir))
+ (component-library (build-path geda-sym-path dir)))
+ )
'(
- "74"
- "4000"
- "IEC417"
- "amphenol"
- "analog"
- "linear"
- "altera"
- "lattice"
- "xilinx"
- "idt"
- "misc"
- "power"
- "philips"
- "minicircuits"
- "st"
- "apex"
- "allegro"
- "irf"
- "transistor"
- "io"
- "titleblock"
- "memory"
- "micro"
- "maxim"
- "national"
- "radio"
- "tube"
- "connector"
- "switch"
- "switcap"
+ ("74" "74-series logic")
+ ("4000" "4000-series logic")
+ ("IEC417" "IEC 60417")
+ ("amphenol" "Amphenol connectors")
+ ("analog" "Generic basic devices")
+ ("linear" "Linear Technology")
+ ("altera" "Altera")
+ ("lattice" "Lattice Semiconductor")
+ ("xilinx" "Xilinx")
+ ("idt" "IDT")
+ ("misc" "Misc. unsorted symbols")
+ ("power" "Generic power rails")
+ ("philips" "Philips Electronics")
+ ("minicircuits" "Mini-Circuits")
+ ("st" "ST Microelectronics")
+ ("apex" "Apex Microtechnology")
+ ("allegro" "Allegro Microsystems")
+ ("irf" "International Rectifier")
+ ("transistor" "Misc. transistors")
+ ("io" "Generic input/output")
+ ("titleblock" "Generic titleblocks")
+ ("memory" "Misc. memory devices")
+ ("micro" "Misc. microcontrollers")
+ ("maxim" "Maxim/Dallas")
+ ("national" "National Semiconductor")
+ ("radio" "Generic radio elements")
+ ("tube" "Misc. vacuum tubes")
+ ("connector" "Generic connectors")
+ ("switch" "Generic switches")
+ ("switcap" "SWITCAP simulation elements")
;"verilog"
;"vhdl"
- "spice"
- "rf"
- "bus"
- "pla"
- "ecl"
- "dec"
- "supervisor"
- "opto"
- "diode"
- "relay"
- "cascade"
- "asic"
- "asicpads"
+ ("spice" "SPICE simulation elements")
+ ("rf" "Misc. RF elements")
+ ("bus" "PC104 bus")
+ ("pla" "Misc. programmable logic arrays")
+ ("ecl" "ECL logic")
+ ("dec" "DEC")
+ ("supervisor" "Misc. microprocessor supervisors")
+ ("opto" "Misc. optocouplers")
+ ("diode" "Generic diodes")
+ ("relay" "Misc. relays")
+ ("cascade" "Cascade simulation elements")
+ ("asic" "ASIC basic devices")
+ ("asicpads" "ASIC contact pads")
;"gnetman"
"local"
))
--
1.5.3.3
signature.asc
Description: This is a digitally signed message part.
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Wed, Nov 28, 2007 at 01:02:00PM -0800, Larry Doolittle wrote: > > > > DCMs have lousy jitter, yes. Altera parts have real PLLs, though. > > Even if the FPGA chip were perfect, there are so many digital signals > flying around the package that ground bounce alone will kill any semblance > of low jitter performance. The Altera PLLs have dedicated supply (and output) pins and are located in the corners of the chip. The Xilinx DCMs are on the 2.5V VCCAUX rail shared with other things. I suppose it's worth seeing if the original board would perform better with a cleaner VCCAUX, but the nature of a DCM is inherently jittery. > This may be too fine a point for video work. My work involves SDR-like > projects where the requirements on the order of 1ps rms. At work I'm on a project that is generating high bandwidth signals up to 1G and our LOs are custom PLL modules (small boards with can lids) from Mini Circuits. Sounds like overkill for DVI, though. > > That's kind of surprising, because the DVI spec has a bitrate 10x the > > fundamental clock, so both the transmitter and receiver generally have > > to have PLLs. > > Just the receiver, right? And that cable length comment makes me > suspicious something more subtle is going on. I've looked at receivers more closely than transmitters, but I assume that the input to the transmitter is the fundamental clock plus the wide (32? 36?) bit RGB+control plane. The serial output has the 10x bitrate, so it must make it internally. One from Conexant I just googled shows a PLL in the block diagram. My point being that the transmitter chip should be fine as long as the jitter does not impact setup-and-hold times at the input and the PLL rides over it. Is there an external loop filter to play with? Ohh it just occured to me that perhaps the problem is that the 10x clock is made from the PLL but the CLK signal on the DVI is the original clock, not a divide-by-10 of the PLL. In that case maybe there are transmitters where this is different? -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
Ben - On Wed, Nov 28, 2007 at 12:49:50PM -0800, Ben Jackson wrote: > On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote: > > > > We've discovered that the clock generators in the Xilinx FPGA part are > > lousy for generating video clocks. > > DCMs have lousy jitter, yes. Altera parts have real PLLs, though. Even if the FPGA chip were perfect, there are so many digital signals flying around the package that ground bounce alone will kill any semblance of low jitter performance. This may be too fine a point for video work. My work involves SDR-like projects where the requirements on the order of 1ps rms. > > which causes artifacts on DVI monitors at resolutions as low as > > 1280x1024 when the cable gets beyond a certain length. (I don't > > recall all the details.) > > That's kind of surprising, because the DVI spec has a bitrate 10x the > fundamental clock, so both the transmitter and receiver generally have > to have PLLs. Just the receiver, right? And that cable length comment makes me suspicious something more subtle is going on. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote: > > We've discovered that the clock generators in the Xilinx FPGA part are > lousy for generating video clocks. DCMs have lousy jitter, yes. Altera parts have real PLLs, though. > which causes artifacts on DVI monitors at resolutions as low as > 1280x1024 when the cable gets beyond a certain length. (I don't > recall all the details.) That's kind of surprising, because the DVI spec has a bitrate 10x the fundamental clock, so both the transmitter and receiver generally have to have PLLs. > So the best solution we can come up with is to put on some external > clock generators. Cypress makes a bunch, and some inexpensive devboards called "candy boards", eg peppermint. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
To be fair . The same circuit --- verilog-A -- // basic CMOS inverter with parameter passing (in, out, vdd, vss) module myinv (2 1 100 200); inout 2, 1, 100, 200; electrical 2, 1, 100, 200; parameter WP=30u, WN=10u; pfet #(.w(WP), .l(1u)) M1 (2 1 100 100) ; nfet #(.w(WN), .l(1u)) M2 (2 1 200 200); endmodule // a buffer (non inverting) module mybuf(in out vdd vss) inout in, vdd, vss,out; electrical in, vdd, vss,out; parameter N=1; myinv #(.WP(N*30u), .WN(N*15u)) xinv1 (in, inv, vdd, vss); myinv #(.WP(N*30u), .WN(N*15u)) xinv2 (inv, out, vdd, vss); endmodule // and now a circuit which uses the buffer module testbench; electrical vdd, vss, in, buf1_out, buf2_out); // power/ground vsource #(.dc(5)) vvdd (vdd 0); vsource #(.dc(0)) vvss (vss 0); // a 1x buffer mybuf xbuf1 (in buf1_out vdd vss); // a 4x buffer mybuf #(.N(4)) xbuf2 (in buf2_out vdd vss); endmodule --- verilog-A -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Forwarding?
On Wed, 2007-11-28 at 14:21 -0500, Timothy Normand Miller wrote: > Does this list forward automatically to gEDA-dev? No, although most of the geda-dev subscribers will probably be subscribed to geda-user. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gerbv-1.0.3 released!
On Wednesday 28 November 2007 20:15:12 Peter Clifton wrote: > Please can we consider moving this to GIT under the umbrella of the > gEDA/gaf project (or even a perhaps GIT repo), as this has proven > invaluable in many cases with gEDA since (and even before) we switched. > I'm biased, as I love GIT - and am starting to feel I know it, but there > are simply things you can't do with CVS. I'd be really happy to see this added as a repo on git.gpleda.org -- but I don't think it would make sense for it to be added into the gaf repository. Peter -- Peter Brett Electronic Systems Engineer Integral Informatics Ltd signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: Simple text-substitution macros for text labels?
> In future, we might support more flexible extensibility. In theory, > we could provide a hook for calling scheme code on file-save, > however the APIs are not really "there" enough yet to do the > manipulation you're after. In PCB, we could put the hook in the HID api; since what we're talking about here is a difference between a string's "value" and it's "appearance". Is there a common point (or at least an easily accessible point) where we have the string's content just before we "print" it (display on screen, export to postscript, render in png)? Those are really the only places we *need* to hook, except perhaps in gnetlist. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: Simple text-substitution macros for text labels?
On Wed, 2007-11-28 at 13:39 -0500, Marshall Jose wrote: > How close is gschem to supporting simple macros or variables to be > included in text strings? I'm thinking about something like > > "$filesavedatetime" expands to the date and time of the most-recent save > operation involving that current file, or > "$filename" expands to the saved file's name > > such that (e.g.) I don't have to keep editing the title-block > information with every edit. I'm not looking for CPP functionality, just > some simple, useful substitutions. Also, IMO, applying them to attribute > strings would just be asking for headaches. A neat way to do this would be with a shell script, as there is no in built text processing in gschem. I personally feel that the place for this processing would be (for now at least) in a user's Makefile or post-processing script. A little bit of "sed" or "awk" usage in conjunction with some /usr/bin/sh scripting should do the trick. In future, we might support more flexible extensibility. In theory, we could provide a hook for calling scheme code on file-save, however the APIs are not really "there" enough yet to do the manipulation you're after. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gerbv-1.0.3 released!
On Wed, 2007-11-28 at 13:39 -0500, Stuart Brorson wrote: > As currently planned, this release is the last release of the 1.0.X series. > With this release, maintainership of gerbv has broadened to include several > more members of the gEDA project (http://geda.seul.org/). This > places gerbv on a good footing for continued active developement. > Moving forward, gerbv will begin to make use of the cairo graphics library (if > it is available on your system). Expect to see other changes as gerbv moves > to the 1.1 series! I've looked at that.. pad rendering quality isn't so high with cairo, as it seems for speed, the "flattening" precision where cairo paths are turned into polylines for rasterising seems to have been turned down. (Presumably a trade-off for speed). If there is anything I can contribute by way of speed improvements, I will do so - although at first glance, it seems to use a pretty standard cairo drawing model - so there is no obvious low hanging fruit. I'm looking at / hitting similar issues for cairo in gschem. > The homepage for gerbv still lives on SourceForge: > http://gerbv.sourceforge.net/. > There you will find a bug database, > a feature request database, the CVS repo and a commit mailinglist. Please can we consider moving this to GIT under the umbrella of the gEDA/gaf project (or even a perhaps GIT repo), as this has proven invaluable in many cases with gEDA since (and even before) we switched. I'm biased, as I love GIT - and am starting to feel I know it, but there are simply things you can't do with CVS. > Special thanks to Stefan Petersen, Dan McMahill, and Julian Lamb for > help in getting this release out the door! > > --Stuart Thanks to you all, Stuart, Stefan, Dan, Julian, all gerbv contributors. I appreciate this effort myself, and I'm sure all other gerbv users do too. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
Timothy - On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote: > We've discovered that the clock generators in the Xilinx FPGA part are > lousy for generating video clocks. Welcome to the club. > So the best solution we can come up with is to put on some external > clock generators. One for each video head. Problems: (1) more time > to mod the design, (2) up to $15 each for the generators, (3) we have > no idea what generators to use, how good they are, how to wire them. > > Does anyone know anything about these? Do you have experience with > specific high-frequency clock generators and know how they perform and > what kind of jitter they produce? I live and breathe high-frequency clock jitter. A good clock subsystem has less than 1 ps rms clock jitter, at least in a limited band (e.g., 20 Hz to 20 MHz). Bad layout can screw up a design even if you use good parts. I have had positive experience with parts from ICS and AD. My experience is not specific to video. > Unfortunately, it could take quite a long time for us to find > suppliers of clock generators, get samples, wire them up and test > them, etc., so we just need find out if someone out there already has > the right answer or knows where to look for it. You haven't mumbled enough about the specific needs for me to help much yet. Frequency range, degree of programmability, signal levels, etc. Do you need a PLL, or is a programmable divider chain enough? An AD9512 is a nice part, and "only" US$20 each, with several programmable outputs. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter clock
Hello Timothy, take a look at Analog Devices AD9516-0 ... 5 family, these are flexible clock generators with many outputs and low jitter performance, as far as i understood in the femti-seconds range (< 1ps jitter). I have no practical experience with them but i plan to use them in a new project. Michael Timothy Normand Miller wrote: > Sorry about the cross-post. We're -><- THIS close to getting OGD1 > done, with artwork in the hands of board makers who are working on > quotes, and we've discovered a problem that could make the video > output unacceptable. > > We've discovered that the clock generators in the Xilinx FPGA part are > lousy for generating video clocks. We're seeing like 900ps of jitter, > which causes artifacts on DVI monitors at resolutions as low as > 1280x1024 when the cable gets beyond a certain length. (I don't > recall all the details.) > > One option is to use the clock generators in the Lattice part, but > even they have like 400ps of jitter, and they also severely limit the > range of frequencies we can generate. > > So the best solution we can come up with is to put on some external > clock generators. One for each video head. Problems: (1) more time > to mod the design, (2) up to $15 each for the generators, (3) we have > no idea what generators to use, how good they are, how to wire them. > > Does anyone know anything about these? Do you have experience with > specific high-frequency clock generators and know how they perform and > what kind of jitter they produce? > > Unfortunately, it could take quite a long time for us to find > suppliers of clock generators, get samples, wire them up and test > them, etc., so we just need find out if someone out there already has > the right answer or knows where to look for it. > > Thank you for your time! > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
Sure post an example and see if you can convert a symbol to an ascii format. Steve Meier On Wed, 2007-11-28 at 12:19 -0700, Steven Ball wrote: > On Nov 28, 2007, at 11:48 AM, Steve Meier wrote: > > > Steven, > > > > Are the files in a text based format? > > > > There is a text header (PC-CAPS database file version, copyright), and > then the rest of the file is binary gibberish. > > However, running it through the 'PDIF Writer' produces a .pdf, which > is actually a 'P-CAD Database Interchange Format' file, which is > wholly text. > > Symbols are still binary, but I might be able to get them to go > through the PDIF writer as well. > > Should I put up an example? I can create an actual PDF of what it > should look like along with the binary and PDIF outputs. > > -Steve > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Forwarding?
Does this list forward automatically to gEDA-dev? -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
On Nov 28, 2007, at 11:48 AM, Steve Meier wrote: > Steven, > > Are the files in a text based format? > There is a text header (PC-CAPS database file version, copyright), and then the rest of the file is binary gibberish. However, running it through the 'PDIF Writer' produces a .pdf, which is actually a 'P-CAD Database Interchange Format' file, which is wholly text. Symbols are still binary, but I might be able to get them to go through the PDIF writer as well. Should I put up an example? I can create an actual PDF of what it should look like along with the binary and PDIF outputs. -Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
Sorry about the cross-post. We're -><- THIS close to getting OGD1 done, with artwork in the hands of board makers who are working on quotes, and we've discovered a problem that could make the video output unacceptable. We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. We're seeing like 900ps of jitter, which causes artifacts on DVI monitors at resolutions as low as 1280x1024 when the cable gets beyond a certain length. (I don't recall all the details.) One option is to use the clock generators in the Lattice part, but even they have like 400ps of jitter, and they also severely limit the range of frequencies we can generate. So the best solution we can come up with is to put on some external clock generators. One for each video head. Problems: (1) more time to mod the design, (2) up to $15 each for the generators, (3) we have no idea what generators to use, how good they are, how to wire them. Does anyone know anything about these? Do you have experience with specific high-frequency clock generators and know how they perform and what kind of jitter they produce? Unfortunately, it could take quite a long time for us to find suppliers of clock generators, get samples, wire them up and test them, etc., so we just need find out if someone out there already has the right answer or knows where to look for it. Thank you for your time! -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
Steven, Are the files in a text based format? Steve Meier On Wed, 2007-11-28 at 11:53 -0700, Steven Ball wrote: > On Nov 28, 2007, at 9:53 AM, Dan McMahill wrote: > > > Peter Clifton wrote: > >> On Wed, 2007-11-28 at 12:41 -0300, Alex Lopes Pereira wrote: > >>> Does someone knows how to convert a schematic made in PCAD to gEDA > >>> gschem ? > >>> > >>> Thanks a lot, > >>> Alex > >> > >> Not off the top of my head, but if PCAD has a "human" readable format > >> (e.g. can be opened in a text editor, and makes "some" _sense_), we > >> could probably have a stab at writing a simple converter. > > > > I believe there is an ascii format option. Many years ago (before > > moving to pcb) I used Accel EDA (what PCAD used to be called) for the > > layout of a patch antenna with microstrip feed network. It was > > terribly > > suited for something like that where the layout is the circuit. I > > ended > > up writing an awk program which spit out an ascii file that Accel > > could > > read. My memory is that the file format was not documented but not > > too > > hard to figure out. > > I have a ton of old schematics in PCAD 8.7, which runs on DOS. If > there was a way to import them to gschem, I'd be pretty darn happy. I > also have a ton of PCAD PCB files as well, which would be neat to get > into PCB, but... > > I don't know where to start to make something like this happen, but if > anyone needs a complex example of a PCAD schematic/PCB, let me know, > and I would be more than happy to provide. I have symbols/footprints > too that I'd love to convert. I'm pretty good at programming and > could help out with the effort once I got up to speed a bit... > > It would be really neat if there was a way to generalize the whole > thing, like, take a Gerber backwards into PCB and gschem. Like, pull > it into PCB, mark up what footprints belong to what component, > generate a netlist, and something of a start for a schematic. Would > make the whole geda suite really compelling for new users if they > could import old designs. > > All new designs I do are with geda tools. I'm more than happy to help > support this project in exchange for knowing I am not going to get > stuck in a bind with a dongle. > > -Steve > > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
Since I build a "flat" netlist for each sheet it should be fairly streight forward to build a hierarchical netlist thus I think it will just be a syntax issue for the various formats. As a side note: I have moved the reading of schematics from the c code to a guile script. I am in process of doing the same for symbols and plan to also write the schematics, symbol files with guile scripts. The netlist application will allow the user to select which script they want for reading and writting thus it should support both standard gda and my non-stock, (tm) Peter C, file formats. Theoretically, given a file structure one should be able to write scripts for any schematic capture program and then this could function as a translator as well. I have been putting together a more extensive and documented guile api to interact with the library contanded data structures. All of this together with a functioning hierarchical bus support and the addition of hierarchical netlists should as I claimed earlier be interesting. Thanks David, Dan and Al for the pointers to the netlist formats. Steve Meier On Wed, 2007-11-28 at 12:54 -0500, Dan McMahill wrote: > Steve Meier wrote: > > I am seeking good references for verilog, VHDL and spice syntext > > specificaly with the idea of supporting hierarchical net lists. Online > > or recomendations for purchase. > > > > I desire this material as my code is reaching a level of maturity that > > would make simulation of complex designs interesting. > > > > Thanks, > > > > Steve Meier > > For verilog and "spice" (I'm including things like spice2, spice3, > hspice, spectre, etc under the "spice" heading), it is quite simple. > > note, exact syntax may vary for the passing of parameters, but this > should demonstrate the idea. See > http://www.ece.uci.edu/docs/hspice/hspice_2001_2-43.html for examples of > hspice. > > You'll note that there is almost nothing special or extra to do with > hierarchy. You simply have a flat netlist for each level in the > hierarchy and instantiate subcircuits. > > --- SPICE -- > > * basic CMOS inverter with parameter passing (in, out, vdd, vss) > .subckt myinv 1 2 100 200 WP=30u WN=10u > M1 2 1 100 100 PFET W='WP' L=1u > M2 2 1 200 200 NFET W='WN' L=1u > .ends > > * a buffer (non inverting) > .subckt mybuf in out vdd vss N=1 > xinv1 in inv vdd vss myinv WP='N*10u' WN='N*5u' > xinv2 inv out vdd vss myinv WP='N*30u' WN='N*15u' > .ends > > * and now a circuit which uses the buffer > > * power/ground > vvdd vdd 0 dc 5.0 > vvss vss 0 dc 0.0 > > * a 1x buffer > xbuf1 in buf1_out vdd vss mybuf > > * a 4x buffer > xbuf2 in buf2_out vdd vss mybuf N=4 > > * add stimulus, etc here... > > --- SPICE -- > > --- spectre -- > > // basic CMOS inverter with parameter passing (in, out, vdd, vss) > subckt myinv 1 2 100 200 > parameters WP=30u WN=10u > M1 (2 1 100 100) PFET W=WP L=1u > M2 (2 1 200 200) NFET W=WN L=1u > ends myinv > > // a buffer (non inverting) > subckt mybuf in out vdd vss > parameters N=1 > xinv1 (in inv vdd vss) myinv WP=N*10u WN=N*5u > xinv2 (inv out vdd vss) myinv WP=N*30u WN=N*15u > ends mybuf > > // and now a circuit which uses the buffer > > // power/ground > vvdd (vdd 0) vsource type=dc dc=5.0 > vvss (vss 0) vsource type=dc dc=0.0 > > // a 1x buffer > xbuf1 (in buf1_out vdd vss) mybuf > > // a 4x buffer > xbuf2 (in buf2_out vdd vss) mybuf N=4 > > // add stimulus, etc here... > > --- spectre -- > > --- verilog -- > > module myinv(in out vdd vss) > input in, vdd, vss; > output out; > wire out; > > parameter DELAY=5; > > // (I may have the delay syntax wrong, verilog book isn't in front of me) > assign #DELAY out = ~in; > endmodule > > module mybuf(in out vdd vss) > input in, vdd, vss; > output out; > wire int, out; > > defparam inv1.DELAY=2 > myinv inv1(.in(in), .out(int), .vdd(vdd), .vss(vss)) > defparam inv1.DELAY=3 > myinv inv2(.in(int),.out(out), .vdd(vdd), .vss(vss)) > > endmodule > > module testbench > > wire in, out1, out2; > reg vdd, vss; > > mybuf buf1(.in(in), .out(out1), .vdd(vdd), .vss(vss)) > mybuf buf2(.in(in), .out(out2), .vdd(vdd), .vss(vss)) > > // some stimulus here... > endmodule > > --- verilog -- > > > > In all of these, the basic idea is the same. Each level of hierarchy > has its own netlist inside of a subcircuit or a module. Then other > blocks are instantiated. > > Note the decided lack of doing anything silly like producing a flattened > netlist for the whole design. That kills the ability for humans to > effectively read the netlist (needed all too often) and simulators to do > various optimizations. > > Hope this helps. > > -Dan >
Re: gEDA-user: PCAD to GEDA (GSCHEM)
On Nov 28, 2007, at 9:53 AM, Dan McMahill wrote: > Peter Clifton wrote: >> On Wed, 2007-11-28 at 12:41 -0300, Alex Lopes Pereira wrote: >>> Does someone knows how to convert a schematic made in PCAD to gEDA >>> gschem ? >>> >>> Thanks a lot, >>> Alex >> >> Not off the top of my head, but if PCAD has a "human" readable format >> (e.g. can be opened in a text editor, and makes "some" _sense_), we >> could probably have a stab at writing a simple converter. > > I believe there is an ascii format option. Many years ago (before > moving to pcb) I used Accel EDA (what PCAD used to be called) for the > layout of a patch antenna with microstrip feed network. It was > terribly > suited for something like that where the layout is the circuit. I > ended > up writing an awk program which spit out an ascii file that Accel > could > read. My memory is that the file format was not documented but not > too > hard to figure out. I have a ton of old schematics in PCAD 8.7, which runs on DOS. If there was a way to import them to gschem, I'd be pretty darn happy. I also have a ton of PCAD PCB files as well, which would be neat to get into PCB, but... I don't know where to start to make something like this happen, but if anyone needs a complex example of a PCAD schematic/PCB, let me know, and I would be more than happy to provide. I have symbols/footprints too that I'd love to convert. I'm pretty good at programming and could help out with the effort once I got up to speed a bit... It would be really neat if there was a way to generalize the whole thing, like, take a Gerber backwards into PCB and gschem. Like, pull it into PCB, mark up what footprints belong to what component, generate a netlist, and something of a start for a schematic. Would make the whole geda suite really compelling for new users if they could import old designs. All new designs I do are with geda tools. I'm more than happy to help support this project in exchange for knowing I am not going to get stuck in a bind with a dongle. -Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gerbv-1.0.3 released!
This is great! I'm glad to see gerbv is being actively developed again. Will do my part by downloading and testing. Thanks to the team! -dave Stuart Brorson wrote: > Hello! > > This is to announce the fourth release in the stable branch of > gerbv, 1.0.3. > > This release represents a point release incorporating a few patches made > against the 1.0.X source over the last 1 1/2 years. Specific updates > include: > > * Incorporate changes from Joost Witteveen to support extended >%SR% commands. > * Fix endless loop bug when gerbv encountered an unknown >% code. Patch from Joost Witteveen. > * Fixed initial scale setting for %MOMM% Gerber files. >Patch from Joost Witteveen. > * Fixed format for small drillfiles. Patch from Trevor Blackwell. > * Fix setting of the initial window size when the screen >is larger than the display. Patch from David Carr. > > As currently planned, this release is the last release of the 1.0.X series. > With this release, maintainership of gerbv has broadened to include several > more members of the gEDA project (http://geda.seul.org/). This > places gerbv on a good footing for continued active developement. > Moving forward, gerbv will begin to make use of the cairo graphics library (if > it is available on your system). Expect to see other changes as gerbv moves > to the 1.1 series! > > The homepage for gerbv still lives on SourceForge: > http://gerbv.sourceforge.net/. > There you will find a bug database, > a feature request database, the CVS repo and a commit mailinglist. > > To download gerbv-1.0.3 go to > http://prdownloads.sourceforge.net/gerbv/ > and grab gerbv-1.0.3.tar.gz > > To install gerbv do this: > 1. tar zxf gerbv-1.0.3.tar.gz > 2. cd gerbv-1.0.3 > 3. ./configure > 4. make install > > Interesting configure options are: > --help : Lists all options > --disable-exportpng : Disable compilation of export of PNGs > --prefix= : Install to dir > --with-maxfiles : Set maximal number of files (default 20). > --enable-unit-mm: Change default unit in status bar to mm from inch. > > Special thanks to Stefan Petersen, Dan McMahill, and Julian Lamb for > help in getting this release out the door! > > --Stuart > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem: Simple text-substitution macros for text labels?
How close is gschem to supporting simple macros or variables to be included in text strings? I'm thinking about something like "$filesavedatetime" expands to the date and time of the most-recent save operation involving that current file, or "$filename" expands to the saved file's name such that (e.g.) I don't have to keep editing the title-block information with every edit. I'm not looking for CPP functionality, just some simple, useful substitutions. Also, IMO, applying them to attribute strings would just be asking for headaches. -- Marshall Jose, WA3VPZ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gerbv-1.0.3 released!
Hello! This is to announce the fourth release in the stable branch of gerbv, 1.0.3. This release represents a point release incorporating a few patches made against the 1.0.X source over the last 1 1/2 years. Specific updates include: * Incorporate changes from Joost Witteveen to support extended %SR% commands. * Fix endless loop bug when gerbv encountered an unknown % code. Patch from Joost Witteveen. * Fixed initial scale setting for %MOMM% Gerber files. Patch from Joost Witteveen. * Fixed format for small drillfiles. Patch from Trevor Blackwell. * Fix setting of the initial window size when the screen is larger than the display. Patch from David Carr. As currently planned, this release is the last release of the 1.0.X series. With this release, maintainership of gerbv has broadened to include several more members of the gEDA project (http://geda.seul.org/). This places gerbv on a good footing for continued active developement. Moving forward, gerbv will begin to make use of the cairo graphics library (if it is available on your system). Expect to see other changes as gerbv moves to the 1.1 series! The homepage for gerbv still lives on SourceForge: http://gerbv.sourceforge.net/. There you will find a bug database, a feature request database, the CVS repo and a commit mailinglist. To download gerbv-1.0.3 go to http://prdownloads.sourceforge.net/gerbv/ and grab gerbv-1.0.3.tar.gz To install gerbv do this: 1. tar zxf gerbv-1.0.3.tar.gz 2. cd gerbv-1.0.3 3. ./configure 4. make install Interesting configure options are: --help : Lists all options --disable-exportpng : Disable compilation of export of PNGs --prefix= : Install to dir --with-maxfiles : Set maximal number of files (default 20). --enable-unit-mm: Change default unit in status bar to mm from inch. Special thanks to Stefan Petersen, Dan McMahill, and Julian Lamb for help in getting this release out the door! --Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-20070912 problems
Is it just a matter of the scroll bars defaulting to the right side, instead of the left? If so, I've fixed that. Have you tried the CVS version of pcb? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb-20070912 problems
People, I'm running the cvs/lesstif version of pcb-20070912 (because the download version won't start properly). I'm having problems with the commands not displaying results fully. For example the commands Connects -> Optomize ratsnest will display ratsnest information on the first request; subsequest requests appear to execute, but no information is ever displayed. Connects -> Lookup connection to object has similiar problems; requests appear to execute, however no information is ever displayed. In fact ths situation is at the point where I'm thinking of re-installing pcb-200702?? mostly because the gtk version seems to work properly. Any comments/help would be appreciated. Harold Skank ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
Steve Meier wrote: > I am seeking good references for verilog, VHDL and spice syntext > specificaly with the idea of supporting hierarchical net lists. Online > or recomendations for purchase. > > I desire this material as my code is reaching a level of maturity that > would make simulation of complex designs interesting. > > Thanks, > > Steve Meier For verilog and "spice" (I'm including things like spice2, spice3, hspice, spectre, etc under the "spice" heading), it is quite simple. note, exact syntax may vary for the passing of parameters, but this should demonstrate the idea. See http://www.ece.uci.edu/docs/hspice/hspice_2001_2-43.html for examples of hspice. You'll note that there is almost nothing special or extra to do with hierarchy. You simply have a flat netlist for each level in the hierarchy and instantiate subcircuits. --- SPICE -- * basic CMOS inverter with parameter passing (in, out, vdd, vss) .subckt myinv 1 2 100 200 WP=30u WN=10u M1 2 1 100 100 PFET W='WP' L=1u M2 2 1 200 200 NFET W='WN' L=1u .ends * a buffer (non inverting) .subckt mybuf in out vdd vss N=1 xinv1 in inv vdd vss myinv WP='N*10u' WN='N*5u' xinv2 inv out vdd vss myinv WP='N*30u' WN='N*15u' .ends * and now a circuit which uses the buffer * power/ground vvdd vdd 0 dc 5.0 vvss vss 0 dc 0.0 * a 1x buffer xbuf1 in buf1_out vdd vss mybuf * a 4x buffer xbuf2 in buf2_out vdd vss mybuf N=4 * add stimulus, etc here... --- SPICE -- --- spectre -- // basic CMOS inverter with parameter passing (in, out, vdd, vss) subckt myinv 1 2 100 200 parameters WP=30u WN=10u M1 (2 1 100 100) PFET W=WP L=1u M2 (2 1 200 200) NFET W=WN L=1u ends myinv // a buffer (non inverting) subckt mybuf in out vdd vss parameters N=1 xinv1 (in inv vdd vss) myinv WP=N*10u WN=N*5u xinv2 (inv out vdd vss) myinv WP=N*30u WN=N*15u ends mybuf // and now a circuit which uses the buffer // power/ground vvdd (vdd 0) vsource type=dc dc=5.0 vvss (vss 0) vsource type=dc dc=0.0 // a 1x buffer xbuf1 (in buf1_out vdd vss) mybuf // a 4x buffer xbuf2 (in buf2_out vdd vss) mybuf N=4 // add stimulus, etc here... --- spectre -- --- verilog -- module myinv(in out vdd vss) input in, vdd, vss; output out; wire out; parameter DELAY=5; // (I may have the delay syntax wrong, verilog book isn't in front of me) assign #DELAY out = ~in; endmodule module mybuf(in out vdd vss) input in, vdd, vss; output out; wire int, out; defparam inv1.DELAY=2 myinv inv1(.in(in), .out(int), .vdd(vdd), .vss(vss)) defparam inv1.DELAY=3 myinv inv2(.in(int),.out(out), .vdd(vdd), .vss(vss)) endmodule module testbench wire in, out1, out2; reg vdd, vss; mybuf buf1(.in(in), .out(out1), .vdd(vdd), .vss(vss)) mybuf buf2(.in(in), .out(out2), .vdd(vdd), .vss(vss)) // some stimulus here... endmodule --- verilog -- In all of these, the basic idea is the same. Each level of hierarchy has its own netlist inside of a subcircuit or a module. Then other blocks are instantiated. Note the decided lack of doing anything silly like producing a flattened netlist for the whole design. That kills the ability for humans to effectively read the netlist (needed all too often) and simulators to do various optimizations. Hope this helps. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
On Wednesday 28 November 2007, Steve Meier wrote: > I am seeking good references for verilog, VHDL and spice > syntext specificaly with the idea of supporting hierarchical > net lists. Online or recomendations for purchase. > > I desire this material as my code is reaching a level of > maturity that would make simulation of complex designs > interesting. The Verilog-AMS LRM can be downloaded from: http://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/2.2/AMS-LRM-2-2.pdf The development version of gnucap accepts (and prefers) netlists in Verilog format. For Spice, there is no standard. The closest thing there is to a standard is the way Spice-2 works. Almost everything else is a proprietary superset of that. A better spec for a Spice "standard" is to take the intersection of what Spice-2 does and what Spice-3 does. It's a mess. It started out as a good design, with two obvious defects that could have been easily fixed at the time, but later extensions were done poorly and have become rather hard to deal with. What are the two obvious defects? 1. The use of the first letter of the label to indicate type. 2. Irregular and inconsistent syntax. To see an example of a Spice-derived format that has the two obvious defects fixed, look at the Spectre format, which is technically proprietary. It's an excellent format. Too bad it isn't used anywhere else except Spectre (and now gnucap, through a plugin). Gnucap still accepts Spice format, and always will. In future, plugins will make it possible to support variants of the Spice format. If all you care about is netlists, it is easy, except Spice. It might make sense to look at the gnucap language plugins. By making a simple driver, we could easily have a complete netlist translation system. If it doesn't get done first, that driver will be one of my proposals for next summer's google soc. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
Steve Meier wrote: > I am seeking good references for verilog, VHDL and spice syntext > specificaly with the idea of supporting hierarchical net lists. Verilog HDL by Palnitkar has been good for reading how to use verilog better. It has a good reference book organization... appendices with lists that would be helpful coding netlist output details -- it was published 1996 so that will probably tell which year of standard it matches best. Principles of Verifiable RTL Design has descriptions of code aimed at verification, and style that lets you use checkers well, and the examples go for simulation speed, so simulation is useful for mdeling more than two seconds of run time... It has a long tutorial that would be useful to refer to as coding. John G -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
Peter Clifton wrote: > On Wed, 2007-11-28 at 12:41 -0300, Alex Lopes Pereira wrote: >> Does someone knows how to convert a schematic made in PCAD to gEDA >> gschem ? >> >> Thanks a lot, >> Alex > > Not off the top of my head, but if PCAD has a "human" readable format > (e.g. can be opened in a text editor, and makes "some" _sense_), we > could probably have a stab at writing a simple converter. I believe there is an ascii format option. Many years ago (before moving to pcb) I used Accel EDA (what PCAD used to be called) for the layout of a patch antenna with microstrip feed network. It was terribly suited for something like that where the layout is the circuit. I ended up writing an awk program which spit out an ascii file that Accel could read. My memory is that the file format was not documented but not too hard to figure out. > In the general case, the only way to translate schematics is to redraw > them. You can insert a picture in the background (of the old layout, > from a screen capture for example) if that helps to "trace" the > original. > > Who make PCAD? > Altium. www.pcad.com It is actually a pretty nice tool. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
On Wed, Nov 28, 2007 at 03:23:52PM +0100, Klaus Rudolph wrote: > > 2) how to create subcircuits for gschm->pcb toolchain. I thought DJ would have answered this already, but his "BlockRenumber" plugin is the only easy way I know that you'll be able to re-use the layout within PCB. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
On Wed, Nov 28, 2007 at 08:17:49AM -0800, Steve Meier wrote: > I am seeking good references for verilog, VHDL and spice syntext You want the LRMs. VHDL is IEEE standard 1076; Verilog is IEEE standard 1364. The correct way would be to purchase them from the IEEE. There may be copies (legal or otherwise) available somewhere on the net if you look hard enough. HTH... -- David Smith| Tel: +44 (0)1454 462380Home: +44 (0)1454 616963 STMicroelectronics | Fax: +44 (0)1454 462305 Mobile: +44 (0)7932 642724 1000 Aztec West| TINA: 065 2380 GPG Key: 0xF13192F2 Almondsbury| Work Email: [EMAIL PROTECTED] BRISTOL, BS32 4SQ | Home Email: [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Request for VHDL and Hierarchical Spice References
I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase. I desire this material as my code is reaching a level of maturity that would make simulation of complex designs interesting. Thanks, Steve Meier ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb printer calibration
Did you type in commas or periods when you typed it in? I.e. 3.99 or 3,99 ? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb printer calibration
In fact i have :-) I've made a correct reading but a wrongfull writing. The measures were X=3,975 in Y=3,999 in so we are not to far from 4 in But if I try to insert 3,975 or 3,999 in the form, it calculate a ratio of 2, in fact for any data I insert that is above 2 it insert 2. But if i've understood the correct ratio should be: 3.975/4 = 0,993 3,999/4 = 0,999 Alle mercoledì 28 novembre 2007, DJ Delorie ha scritto: > > > i was trying to calibrate my printer, so i measure the X and Y lines > > with a caliper and i get x=3,975 in Y=4,999 in (if i've read > > correctly my caliper :-)) > > Hopefully, you haven't. Those lines should both be 4 inches long. If > you type in "4" for both answers, you end up with calibration values > of 1.0. > > What it does is try to guess which line you measured, and compute the > ratio of what you measured to what it drew. So if you measure the 15 > cm line and type in 14.9, it computes 14.9/15. If you enter a value > that's more than 10% off of any of the line lengths, it doesn't know > what you measured, so complains. > signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
On Nov 28, 2007 10:43 AM, DJ Delorie <[EMAIL PROTECTED]> wrote: > > > I am searching for the documentation of gschem and especially for > > creating subcircuits with geschem. I need a subcircuit 16 times on a > > pcb, so I want to use that feature. > > John and I have written scripts to do this. Mine are on > gedasymbols.org; you want page-renumber to copy a schematic page to > other pages (put one copy of the subcircuit on a page, renumber it to > make the other 15) and the RenumberBlock plugin from > http://www.delorie.com/pcb/ to copy the layout (import the first > schematic page and lay it out by hand, cut-n-paste it to the other 15 > while renumbering it as you paste) My scripts, sch-matrix and pcb-matrix, are at http://www.luciani.org/geda/util/util-index.html Create the subcircuit schematic and pcb layout by hand and sch-matrix and pcb-matrix will create the copies and update the refdeses. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCAD to GEDA (GSCHEM)
On Wed, 2007-11-28 at 12:41 -0300, Alex Lopes Pereira wrote: > Does someone knows how to convert a schematic made in PCAD to gEDA > gschem ? > > Thanks a lot, > Alex Not off the top of my head, but if PCAD has a "human" readable format (e.g. can be opened in a text editor, and makes "some" _sense_), we could probably have a stab at writing a simple converter. In the general case, the only way to translate schematics is to redraw them. You can insert a picture in the background (of the old layout, from a screen capture for example) if that helps to "trace" the original. Who make PCAD? -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
> I am searching for the documentation of gschem and especially for > creating subcircuits with geschem. I need a subcircuit 16 times on a > pcb, so I want to use that feature. John and I have written scripts to do this. Mine are on gedasymbols.org; you want page-renumber to copy a schematic page to other pages (put one copy of the subcircuit on a page, renumber it to make the other 15) and the RenumberBlock plugin from http://www.delorie.com/pcb/ to copy the layout (import the first schematic page and lay it out by hand, cut-n-paste it to the other 15 while renumbering it as you paste) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCAD to GEDA (GSCHEM)
Does someone knows how to convert a schematic made in PCAD to gEDA gschem ? Thanks a lot, Alex - Abra sua conta no Yahoo! Mail, o único sem limite de espaço para armazenamento! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb printer calibration
> i was trying to calibrate my printer, so i measure the X and Y lines > with a caliper and i get x=3,975 in Y=4,999 in (if i've read > correctly my caliper :-)) Hopefully, you haven't. Those lines should both be 4 inches long. If you type in "4" for both answers, you end up with calibration values of 1.0. What it does is try to guess which line you measured, and compute the ratio of what you measured to what it drew. So if you measure the 15 cm line and type in 14.9, it computes 14.9/15. If you enter a value that's more than 10% off of any of the line lengths, it doesn't know what you measured, so complains. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Missing the printable docs for gschem
On Wed, 28 Nov 2007 15:23:52 +0100, Klaus Rudolph wrote: > I need a subcircuit 16 times on a pcb, I'd define special symbols with the desired subcircuit. There is a detailed description in the wiki FAQ: http://geda.seul.org/wiki/geda:faq-gschem#can_my_local_library_cover_frequently_needed_sub_circuits cite: 1. Copy the subcircuit to a fresh sheet. (unlock and remove the default title block as you won’t need it) 2. The values of refdes attributes should end with "?", to allow to auto number them later. 3. Move the sub circuit to the lower left of the available space. (You can use symbol-translate from the edit menu) 4. Save the sub circuit as a *.sym file in your local library. 5. Choose “Include component as individual objects” when selecting this complex symbol for your actual schematic. The whole sub circuit will be pasted to your sheet. Be sure to switch back to the default mode for inclusion of ordinary symbols. > All what I found is the > geda-wiki which contains a lot of dead links and circular links to it > self Can you be a bit more specific: Which links are dead? Which circular? > but not the information I need. And yes, I want it in a printable > version like pdf or ps. You volunteer to maintain the docs in various formats? > 2) how to create subcircuits for gschm->pcb toolchain. See above. ---<(kaimartin)>--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Missing the printable docs for gschem
Hi, I am searching for the documentation of gschem and especially for creating subcircuits with geschem. I need a subcircuit 16 times on a pcb, so I want to use that feature. Long time ago I have used it, but could not find any documentation anymore. All what I found is the geda-wiki which contains a lot of dead links and circular links to it self but not the information I need. And yes, I want it in a printable version like pdf or ps. Yes, here are two questions: 1) where is the printable documentation gone 2) how to create subcircuits for gschm->pcb toolchain. Thanks ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: file format of pcb-files needed
Stuart Brorson wrote: >> I am searching for a description of file formats used by pcb. >> Especially a description of library files (m4) and the elements there >> like Elements, Via, Arc, Mark and so on. > > This covers the newlib stuff. > > http://www.brorson.com/gEDA/land_patterns_20070818.pdf You may want to refer to the actual pcb manual though since the file format is fully documented there. The land pattern document is useful but only covers a subset of the allowed syntax. http://pcb.sourceforge.net/pcb-20070912/pcb.html#File%20Formats > No M4 is covered in the above doc since M4 is deprecated. Only the runtime use of m4 is deprecated. The m4 files for pcblib are still the sources for that entire library and pcblib is not deprecated. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: file format of pcb-files needed
> I am searching for a description of file formats used by pcb. > Especially a description of library files (m4) and the elements there > like Elements, Via, Arc, Mark and so on. This covers the newlib stuff. http://www.brorson.com/gEDA/land_patterns_20070818.pdf No M4 is covered in the above doc since M4 is deprecated. Cheers, Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: file format of pcb-files needed
Hi, I am searching for a description of file formats used by pcb. Especially a description of library files (m4) and the elements there like Elements, Via, Arc, Mark and so on. Thanks ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb printer calibration
Hi, i was trying to calibrate my printer, so i measure the X and Y lines with a caliper and i get x=3,975 in Y=4,999 in (if i've read correctly my caliper :-)) But i was unable to insert a number larger than 2,000 and the log window said X value of 2 is too far off. Y value of 2 is too far off. I'm doing something wrong? Could i suggest to insert a label with the unit to use in the window that ask for the two values. Anselmo signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
