Re: gEDA-user: Heavy Symbols and such

[Peter TB Brett]

On Wednesday 05 December 2007 21:40:49 Dave N6NZ wrote:
> Kai-Martin Knaak wrote:
> > On Wed, 05 Dec 2007 11:11:35 -0800, Steve Meier wrote:
> >> I tend to create symbols that have a predefined foot print and then only
> >> override it at the schemtic level when I need to.
> >
> > Me too.
>
> Me three.
>
> > I'd be happy to see an obvious extension of this concept: An attribute
> > that lists a number of preselected footprints for this symbol. E.g. the
> > list for a resistor could be "0805, 0402, RES_RM10, VISHAY_S101. The
> > attribute editor would convert this list into a chooser widget.
>
> I like that idea.  gschem's attribute dialog could use that to be
> smarter -- it could give you a drop-down combo box for pre-defined
> choices, and of course let you type in something different as well.
> That would probably be useful for many attributes with a few sensible
> defaults.

I believe that Peter C was working on this but there were implementation 
difficulties.

There appears to be a tracker item for it:

  [ 1723653 ] Intelligent helper interface for attributes


   Peter

-- 
Peter Brett

Electronic Systems Engineer
Integral Informatics Ltd


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Re: gEDA-user: Heavy Symbols and such

[Peter TB Brett]

On Thursday 06 December 2007 00:02:11 Peter Clifton wrote:
> On Wed, 2007-12-05 at 12:43 -0800, Ben Jackson wrote:
> > On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote:
> > > One way you can do this today is to at the schematic level add a
> > > footprint attribute to each symbol as you place them. The pain is that
> > > if you have a thousand resisters you have to do each one individualy.
> >
> > I basically do this.  I place one resistor, mark it 0603, 10k and then
> > I try to only cut'n'paste it from then on.  Sometimes I royally screw
> > up my refdes's as a result...  Maybe gschem needs a 'copy without refdes'
> > option.
>
> I have a vague memory of seeing an auto-increment refdes thing
> somewhere. 

In gschem: Attributes -> Autonumber text...

> If it doesn't exist (and I just made it up), would it be 
> useful?

It's very useful.

   Peter

-- 
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Electronic Systems Engineer
Integral Informatics Ltd


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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[John Doty]

On Dec 8, 2007, at 4:25 PM, Peter TB Brett wrote:

> On Friday 07 December 2007 23:52:05 John Doty wrote:
>
>> Right now, we, by default, reference light symbols in a common
>> library, and then attach attributes to them. That's wrong, too: if
>> I'm going to use a bunch of, say, OP220's in a design, I want all of
>> them to have the same package and temperature spec. So, right now, I
>> want to reference an editable heavy symbol here. I want neither the
>> library symbol nor a bunch of separate embedded instances (hear that
>> Peter? At best, your scheme gives me a separate instance per page. No
>> good in a multipage schematic). But maybe the heavy symbol approach
>> isn't right either.
>
> Well, it's an improvement on the status quo at least.  I was going  
> to suggest
> multiple pages per schematic file, but I thought I might get  
> trampled by
> enraged users.

I tried that for my first big gEDA project. Very clumsy in other  
ways. Like printing documentation.

>
>> Right now, the mechanics of browsing the libraries for a graphic,
>> copying that to your project library, rescanning symbols to make it
>> visible (arrrggh!), and then finally picking and placing it and going
>> down into it to fix it up are clumsy. But if you don't do that, you
>> may be in trouble down the road when you need to change a footprint
>> or something. Or when somebody "fixes" a common library symbol in the
>> next release.
>
> Oooh, look, another argument for embedded symbols which work. :P

I don't think so. The parts belong to the project first, schematic  
second.

>
> Peter
>
>
>
> -- 
> Peter Brett
>
> Electronic Systems Engineer
> Integral Informatics Ltd
>
>
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John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
[EMAIL PROTECTED]




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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Peter TB Brett]

On Friday 07 December 2007 23:52:05 John Doty wrote:

> Right now, we, by default, reference light symbols in a common
> library, and then attach attributes to them. That's wrong, too: if
> I'm going to use a bunch of, say, OP220's in a design, I want all of
> them to have the same package and temperature spec. So, right now, I
> want to reference an editable heavy symbol here. I want neither the
> library symbol nor a bunch of separate embedded instances (hear that
> Peter? At best, your scheme gives me a separate instance per page. No
> good in a multipage schematic). But maybe the heavy symbol approach
> isn't right either.

Well, it's an improvement on the status quo at least.  I was going to suggest 
multiple pages per schematic file, but I thought I might get trampled by 
enraged users.

> Right now, the mechanics of browsing the libraries for a graphic,
> copying that to your project library, rescanning symbols to make it
> visible (arrrggh!), and then finally picking and placing it and going
> down into it to fix it up are clumsy. But if you don't do that, you
> may be in trouble down the road when you need to change a footprint
> or something. Or when somebody "fixes" a common library symbol in the
> next release.

Oooh, look, another argument for embedded symbols which work. :P

Peter



-- 
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Electronic Systems Engineer
Integral Informatics Ltd


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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Steven Michalske]

think of tables of tables,

i have a resistor table that has all of my companies resistors,  hell
even the reel number for the pick and place machine i am using,  and
my schematic page is linked to a table  it reads that table and sees
that you have resistor known as abc123  it points to the resistor
table and lets you know everything about that resistor.   now think of
this, resistor ABC123 is made in tiwan, and say the container with the
parts was held in customs,  I need 10 million parts YESTERDAY,  in
that database of resistors, it had a list of resistors from local
manufactures that allowed my team to easily find a second and third
source for that resistor. till the crate cleared customs.

see http://computer.howstuffworks.com/question599.htm  or wikipedia
about relational databases

i like the idea of using a SQL database as the backend,  allowing it
to use SQL lite means that it is easy to setup, simple database on the
system
allowing the use of MySQL ( a beast )  allows us to have many 100+
users on the system,  all using the same database.   my fab house can
even get tied in and have up to date information about expected parts
needed.  so that they can pre order if needed.

lots of high level stuff could be done by having it interface to a database.

I know we use SAP to do a lot of this type of stuff, but it is largly
driven by humans to get the data in the right places from the design.

Steve


On Dec 8, 2007 12:04 PM, Dave N6NZ <[EMAIL PROTECTED]> wrote:
>
>
> DJ Delorie wrote:
> >> I'm not advocating making a relational database part of the required
> >> geda tool set
> >
> > No reason it couldn't be, either.  We can hide all that in gattrib and
> > the netlisters.
>
> I should mention one little gotcha... hierarchy always throws in a few
> kinks, since a database table is more naturally a "flat" view.  I'm sure
> the database guru's (which I'm not) have tricks for representing
> hierarchy in a rational way.
>
> -dave
>
>
>
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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Dave N6NZ]

DJ Delorie wrote:
>> I'm not advocating making a relational database part of the required
>> geda tool set
> 
> No reason it couldn't be, either.  We can hide all that in gattrib and
> the netlisters.

I should mention one little gotcha... hierarchy always throws in a few 
kinks, since a database table is more naturally a "flat" view.  I'm sure 
the database guru's (which I'm not) have tricks for representing 
hierarchy in a rational way.

-dave


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gEDA-user: [pcb] Terminology section "done"

[DJ Delorie]

http://www.delorie.com/pcb/docs/gs/

If you find any weirdisms, let me know.


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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[DJ Delorie]

> I'm not advocating making a relational database part of the required
> geda tool set

No reason it couldn't be, either.  We can hide all that in gattrib and
the netlisters.

No reason not to support multiple BOM files in gattrib either; just
like we support multiple SCH files already.


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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Ben Jackson]

On Fri, Dec 07, 2007 at 06:24:00PM -0800, Dave N6NZ wrote:
> 
> In the geda world, I think this makes just as much sense.  The above 5 
> column table would work perfectly fine in mySQL or pick your favorite 
> database.

I don't want to get bogged down in the whole argument, but I will point
out that sqlite would fit in pretty well for this without being obtrusive.

-- 
Ben Jackson AD7GD
<[EMAIL PROTECTED]>
http://www.ben.com/


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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Dave N6NZ]

This problem was solved in the last millennium, and the tools have been 
written. It's called a relational database.

You can't do a CPU design project involving hundreds of engineers with a 
schematic system that doesn't scale.  In the last century I worked on 
several CPU's where the schematics, when printed out, would be as stack 
of B-size sheets 12 feet high.  But I don't think I've ever actually 
seen schematics printed out in full for any CPU design in the last ten 
years...

One of the several refrigerated, walk-in, CPU's that I helped design was 
the Amdahl 5995.  Amdahl's CAD system had a very nice way of dealing 
with attributes.  All the attributes were in a separate data base from 
the schematics.  The attribute database was kept in a relational 
database -- Amdahl used Oracle on a mainframe.

In geda's terminology, imagine a database table with these columns: 
refdes, attrfile, attrfile_revision, attrname, attrvalue.  You joined a 
schematic to an attribute "file" of a particular "revision" based on 
refdes, and *whoosh* you have a full design file.  It was very easy to 
do various placement experiments by keeping two or three placements in 
different attribute files, and you could easily try each one in the 
autorouter and timing analyzer to see which one gave you the best gate 
array.

In the geda world, I think this makes just as much sense.  The above 5 
column table would work perfectly fine in mySQL or pick your favorite 
database.  A tool that connected to an attribute database and updated a 
.sch file accordingly would be a generalized way to attack a lot of the 
problems being discussed in this thread.

I'm not advocating making a relational database part of the required 
geda tool set -- part of the beauty of geda is that for piddly little 8 
sheet projects like I'm doing now, it doesn't have a lot of heavyweight 
baggage that needs to be learned and dealt with.  But I think using the 
existing tools and computer science that the database world makes 
available would go a long way to making gschem attribute management more 
scalable.  Especially as we start talking about BOM driven attribute 
updates, attributes derived from other attributes, bulk updates of 
attributes, etc.

-dave

DJ Delorie wrote:
> Hey, a thought...
> 
> What if gattrib could accept a *.bom on the command line in addition
> to the *.sch ?  We'd have to color code the cells to say which
> attributes go to the schematics and which to the bom, and figure out
> the logistics, but it might fit what we're trying to accomplish.


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Re: gEDA-user: ElementArc

[Ian Chapman]

Thanks again Peter,
This is what I am about to start using.
This is PCB, an interactive
printed circuit board editor
version 20070912

PCB homepage: http://pcb.sf.net
gEDA homepage: http://www.geda.seul.org
gEDA Wiki: http://geda.seul.org/dokuwiki/doku.php?id=geda

- Compile Time Options -
GUI:
gtk : Gtk - The Gimp Toolkit
Exporters:
bom : Exports a Bill of Materials
gerber : RS-274X (Gerber) export.
nelma : Numerical analysis package export.
png : GIF/JPEG/PNG export.
ps : Postscript export.
eps : Encapsulated Postscript
Printers:
lpr : Postscript print.

and gschem is version 1.0.1-20070626, not too old.

Regards Ian.


Compiled on Dec  7 2007 at 19:04:53
On Sat, 2007-12-08 at 00:52 +, Peter Clifton wrote:
> On Fri, 2007-12-07 at 19:11 -0500, Ian Chapman wrote:
> > Okay, I am okay I did the tarball thing and it worked out fine.  My base
> > looks the way I intended too.  Many  thanks for all of your
> > encouragement regards Ian.
> 
> Now you're on Gutsy, the .deb packages I built for use in the
> Engineering department's live-cd should work.. so if you want newer
> versions of things, give me a shout.
> 
> (The live-cd doesn't run Gutsy, but I do.. and I build  + use test on my
> box).
> 
> I've not got all the _very_ latest PCB stuff packaged up, but do have
> the last release tarballs + lots of fixes to make it usable.
> 
> If you're building code from PCB's CVS, you'll probably have all the
> needed fixes.
> 



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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[Peter Clifton]

On Sat, 2007-12-08 at 08:52 +0900, John Doty wrote:
> Right now, we, by default, reference light symbols in a common  
> library, and then attach attributes to them. That's wrong, too: if  
> I'm going to use a bunch of, say, OP220's in a design, I want all of  
> them to have the same package and temperature spec. So, right now, I  
> want to reference an editable heavy symbol here. I want neither the  
> library symbol nor a bunch of separate embedded instances (hear that  
> Peter? At best, your scheme gives me a separate instance per page. No  
  ^ (I assume you mean Peter B, but I'm sure we've both
   discussed embedding stuff in the past).
> good in a multipage schematic). But maybe the heavy symbol approach  
> isn't right either.

At the risk of sounding like a broken record, I was a proponent of the
embedding scheme to be used for a self-contained transfer. If there is
an option to store a cache of symbols in the .sch file, then handing
someone the .sch file gives them something they can open without any
broken symbol errors. No one ever said that was replacing the database /
directory on disk where those symbols originate from.

> Right now, the mechanics of browsing the libraries for a graphic,  
> copying that to your project library, rescanning symbols to make it  
> visible (arrrggh!), and then finally picking and placing it and going  
> down into it to fix it up are clumsy. But if you don't do that, you  
> may be in trouble down the road when you need to change a footprint  
> or something. Or when somebody "fixes" a common library symbol in the  
> next release.

Sounds like a royal pain. File a feature-request (or email here) how you
want it to work, so any future work on the library system can refer to
it. I can't immediately see how to implement it in a "gEDA" way (e.g. to
retain flexibility about where that symbol might be copied to for your
project).

I do appreciate that a per-project symbol store is the way to go for
designs like you're making here, and that it would be nice to provide
some short-cut way to working with that flow.

> The place where this all comes together is the BOM: that's where all  
> of the non-graphical information about the parts is. But right now,  
> we derive that from the graphics. That's wrong, too: the graphics  
> should represent graphical aspects of the design. Symbols and their  
> connections. But the graphics are an inefficient place to control and  
> edit the textual aspects of the design.

I must say, I like the suggestions about a BOM centric design, but I see
this as another view onto the underlying ECAD database or data
structures.

I can't imagine starting a project, and listing every decoupling cap
before I use it.. but I can imagine a view (gattrib on steroids) which
can be used to edit this information.

> Another thing to cogitate on is textual netlist input. In the old  
> Viewlogic days, I sometimes made text files that were pin maps for  
> connectors. Pin number to net name. I had awk scripts that could  
> merge them with Viewlogic's text netlist format, and also make tbl/ 
> troff pages for documentation. Very handy. But in gEDA we have many  
> different netlist output formats, and the only netlist input format  
> is .sch.

Agree... this would be very nice to have. It might even help the
back-anno problem.

My take on this (theory only as yet), is that gschem needs a rats-nest
"mode", where it imports some notion of the "truth" from another tool,
PCB, text-input netlist etc.., and gives you the opportunity to frob
your schematic until it matches. "Congratulations your schematic matches
the input netlist". (I see that paperclip on screen again in my head!)

I'd include "rat-parts", e.g. symbols / sub-circuits which should exist,
but aren't on the page, and in the same vein, I'd like to see
"rat-parts" in PCB, e.g. a "folder" of footprints to drop down which
"should" be on the board, but aren't yet.

Best wishes,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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Re: gEDA-user: ElementArc

[Peter Clifton]

On Fri, 2007-12-07 at 19:11 -0500, Ian Chapman wrote:
> Okay, I am okay I did the tarball thing and it worked out fine.  My base
> looks the way I intended too.  Many  thanks for all of your
> encouragement regards Ian.

Now you're on Gutsy, the .deb packages I built for use in the
Engineering department's live-cd should work.. so if you want newer
versions of things, give me a shout.

(The live-cd doesn't run Gutsy, but I do.. and I build  + use test on my
box).

I've not got all the _very_ latest PCB stuff packaged up, but do have
the last release tarballs + lots of fixes to make it usable.

If you're building code from PCB's CVS, you'll probably have all the
needed fixes.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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Re: gEDA-user: ElementArc

[Dan McMahill]

DJ Delorie wrote:
>> I do not see lessif in synaptic package manager.
> 
> It's not about what's installed, it's about how pcb was built.  If it
> has a bunch of layer buttons along the left side, you're using the gtk
> hid.  If it doesn't, you're using the lesstif hid.

also the "about" dialog box explicitly says which HID.

-Dan




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Re: gEDA-user: ElementArc

[Ian Chapman]

Okay, I am okay I did the tarball thing and it worked out fine.  My base
looks the way I intended too.  Many  thanks for all of your
encouragement regards Ian.


On Fri, 2007-12-07 at 14:10 -0500, DJ Delorie wrote:
> > version 20070208
> 
> That's old.  We might have fixed it since then.
> 
> > This was newly updated together with the newest Ubuntu on an AMD64.
> 
> I'm guessing it was the GTK gui, and not the Lesstif one, then?
> Although, it works OK for gtk also, for me.
> 
> 
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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[DJ Delorie]

Hey, a thought...

What if gattrib could accept a *.bom on the command line in addition
to the *.sch ?  We'd have to color code the cells to say which
attributes go to the schematics and which to the bom, and figure out
the logistics, but it might fit what we're trying to accomplish.


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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[John Doty]

On Dec 7, 2007, at 4:08 PM, Steve Meier wrote:

> John Doty wrote:
>> The interesting idea so far in this discussion has been to let the
>> BOM be source rather than product.
>>
>>
> Dang, That was the idea I intentionally left out of my last diatribe.
> And you cut right to it. I agree, that the world being bom specific as
> opposed to schematic specific is interesting even if i havn't got a
> clear vission oh what being bom specific means. I was going to ask,  
> that
> does being bom specific mean that we build new designs with an a
> bias to the components we already have?

That's one consequence. But consider what happened to me yesterday:

I had made up a 100 slot symbol representing one pin of a 100 pin  
connector. I had two of these connectors in a design, with pins  
spread over many pages. So far so good. But yesterday, I got a look  
at the space (in a vacuum chamber) where these boards need to fit. It  
wasn't as previously described to me, and it really needed a somewhat  
different connector with a different part number and footprint.

OK, now what? It's only two parts, but it's a *lot* of symbols I had  
to track down and fix. Fortunately, there were no others with that  
device= or footprint= attribute, so a multi-file global search and  
replace in nedit did the trick. The joys of text files: thanks, Ales.  
But what if I'd needed to fix one connector, but not the other?

The way we have it now, part attributes are attached to symbols. But  
symbols aren't parts, so that's wrong. And often, attributes should  
be common to many parts of the same type.

Right now, we, by default, reference light symbols in a common  
library, and then attach attributes to them. That's wrong, too: if  
I'm going to use a bunch of, say, OP220's in a design, I want all of  
them to have the same package and temperature spec. So, right now, I  
want to reference an editable heavy symbol here. I want neither the  
library symbol nor a bunch of separate embedded instances (hear that  
Peter? At best, your scheme gives me a separate instance per page. No  
good in a multipage schematic). But maybe the heavy symbol approach  
isn't right either.

Right now, the mechanics of browsing the libraries for a graphic,  
copying that to your project library, rescanning symbols to make it  
visible (arrrggh!), and then finally picking and placing it and going  
down into it to fix it up are clumsy. But if you don't do that, you  
may be in trouble down the road when you need to change a footprint  
or something. Or when somebody "fixes" a common library symbol in the  
next release.

The place where this all comes together is the BOM: that's where all  
of the non-graphical information about the parts is. But right now,  
we derive that from the graphics. That's wrong, too: the graphics  
should represent graphical aspects of the design. Symbols and their  
connections. But the graphics are an inefficient place to control and  
edit the textual aspects of the design.

Another thing to cogitate on is textual netlist input. In the old  
Viewlogic days, I sometimes made text files that were pin maps for  
connectors. Pin number to net name. I had awk scripts that could  
merge them with Viewlogic's text netlist format, and also make tbl/ 
troff pages for documentation. Very handy. But in gEDA we have many  
different netlist output formats, and the only netlist input format  
is .sch.

>
> Seems like the purchasing department/ inventory management groups  
> might
> like the idea?
>
> I would rather find a way to describe a problem economically... The  
> cost
> of using one component over another as long as the availability and
> capability of the componet doesn't become an issue,  should determine
> the selection of the component.
>
> Or, should the potential future cost of a component be includded in  
> the
> selection of what goes into the new design?
>
> You have heard the joke that if you took all the economists in the  
> world
> and lined them up head to foot they would not reach a conclussion?
>
> Hey add hardware engineers debating the meritts of languages to that
> last thought ;)
>
> Steve Meier
>
>
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John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
[EMAIL PROTECTED]




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Re: gEDA-user: ElementArc

[DJ Delorie]

> I do not see lessif in synaptic package manager.

It's not about what's installed, it's about how pcb was built.  If it
has a bunch of layer buttons along the left side, you're using the gtk
hid.  If it doesn't, you're using the lesstif hid.

> pcb_20070912.orig.tar.gz.

Even that's a few months old, but it might have the fix in it.


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Re: gEDA-user: ElementArc

[Ian Chapman]

I have
gtk2-engines 1.2.12.2-Oubuntu1
gtk2-engines-pixbuf 2.12.0-lubunt3
gtk2-engines-ubuntulooks 0.9.12.8

I do not see lessif in synaptic package manager.

I can see but not installed
lessif2 1.0.95.0-2.1 plus a dev, bin and doc

 I guess I am a bit lost as to how it works without gtk 2.4 min.  I do
not see simple gtk in the packet manager ready to be installed.  I'll
try to install the latest version of PCB from the tarball
pcb_20070912.orig.tar.gz.
Regards Ian.


On Fri, 2007-12-07 at 14:10 -0500, DJ Delorie wrote:
> > version 20070208
> 
> That's old.  We might have fixed it since then.
> 
> > This was newly updated together with the newest Ubuntu on an AMD64.
> 
> I'm guessing it was the GTK gui, and not the Lesstif one, then?
> Although, it works OK for gtk also, for me.
> 
> 
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Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter

[Dan McMahill]

Timothy Normand Miller wrote:
> Sorry about the cross-post.  We're -><- THIS close to getting OGD1
> done, with artwork in the hands of board makers who are working on
> quotes, and we've discovered a problem that could make the video
> output unacceptable.
> 
> We've discovered that the clock generators in the Xilinx FPGA part are
> lousy for generating video clocks.  We're seeing like 900ps of jitter,
> which causes artifacts on DVI monitors at resolutions as low as
> 1280x1024 when the cable gets beyond a certain length.  (I don't
> recall all the details.)
> 
> One option is to use the clock generators in the Lattice part, but
> even they have like 400ps of jitter, and they also severely limit the
> range of frequencies we can generate.
> 
> So the best solution we can come up with is to put on some external
> clock generators.  One for each video head.  Problems:  (1) more time
> to mod the design, (2) up to $15 each for the generators, (3) we have
> no idea what generators to use, how good they are, how to wire them.
> 
> Does anyone know anything about these?  Do you have experience with
> specific high-frequency clock generators and know how they perform and
> what kind of jitter they produce?


Try the MAX3674.  Jitter is less than a picosecond or two.  Stick a 
crystal one side and you can program the thing for and output from 
21.25MHz to 1360MHz.  It has parallel or I2C programming.  PSRR is good.

http://www.maxim-ic.com/quick_view2.cfm/qv_pk/5634

-Dan



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gEDA-user: New system log from my crashed fedora

[Robert Butts]

Here is the latest message file the fedora forum people suggested I get.
See attached


rc.sysinit
Description: Binary data


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Re: gEDA-user: PCAD to GEDA (GSCHEM)

[Steve Meier]

Looks like it has the relevent info.

Steve Meier

On Fri, 2007-12-07 at 11:15 -0700, Steven Ball wrote:
> I was doing some digging today, and look what I found:
> 
> http://www.cedcc.psu.edu/cadtools/pcaddoc/pdif.pdf
> 
> Documentation on the format of the PDIF output from PCAD.  Hope it is  
> helpful.
> 
> See also:  http://www.cedcc.psu.edu/cadtools/interfaces.html
> 
> -Steve
> 
> 
> On Nov 28, 2007, at 6:43 PM, Steve Meier wrote:
> 
> > Just to show off what I have been working. The two attached files
> > include a script for reading in a schematic file. The second is my
> > attempt to document the api that either exists or that I have been
> > implementing. Comments, suggestions are always welcome. If we can  
> > figure
> > out the pcad file formats I would be happy to modify or tweek the api
> > for the sake of translating the pcad files.
> >
> > Depending on interest I can do a code release either (as i had  
> > planned)
> > after I have the vhdl, spice, verilog netlist formats, or earlier  
> > (after
> > i complete the basic schematic, symbol file io migration to guile)  
> > and a
> > trivial translation application.
> >
> > Steve Meier
> >
> >
> >
> > Dan McMahill wrote:
> >> Steven Ball wrote:
> >>
> >>> The PDIF writer seems to be able to convert anything to an ASCII  
> >>> output.
> >>>
> >>> http://snurkle.net/~hamster/geda/
> >>>
> >>
> >> By any chance does the documentation for PCAD have details on that
> >> format?  If not, it looks like it could largely be figured out.
> >>
> >>
> >>> I'll dig around and see if I can find a .pcb file to convert and  
> >>> post
> >>> as well.  Let me know what you think and how I can be of help.
> >>>
> >>
> >> just to clarify, pcad uses .pcb too as the suffix.  The format you'll
> >> get there is similar in style to the schematics.
> >>
> >>
> >>
> >>
> >> ___
> >> geda-user mailing list
> >> geda-user@moria.seul.org
> >> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
> >>
> >>
> >
> > ;;; AKEDA - Alaskan Electronic Design Automation
> > ;;; aknetlist - GNU Netlist
> > ;;; Copyright (C) 2007 Stephen F Meier
> > ;;;
> > ;;; This program is free software; you can redistribute it and/or  
> > modify
> > ;;; it under the terms of the GNU General Public License as  
> > published by
> > ;;; the Free Software Foundation; either version 2 of the License, or
> > ;;; (at your option) any later version.
> > ;;;
> > ;;; This program is distributed in the hope that it will be useful,
> > ;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> > ;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > ;;; GNU General Public License for more details.
> > ;;;
> > ;;; You should have received a copy of the GNU General Public License
> > ;;; along with this program; if not, write to the Free Software
> > ;;; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> >
> > ;; Inport an AKEDA style schematic as a page in libakeda
> >
> > (use-modules (srfi srfi-13))
> > (use-modules (ice-9 popen))
> > (use-modules (ice-9 rdelim))
> >
> >
> > (define OBJ_LINE"L" );
> > (define OBJ_BOX "B" );
> > (define OBJ_PICTURE "G" );
> > (define OBJ_CIRCLE  "V" );
> > (define OBJ_NET_SEGMENT "N" );
> > (define OBJ_BUS_SEGMENT "U" );
> > (define OBJ_COMPLEX "C" );
> > (define OBJ_TEXT"T" );
> > (define OBJ_PIN "P" );
> > (define OBJ_ARC "A" );
> > (define OBJ_ROUTE   "R" );
> > (define OBJ_THRU_HOLE   "H" );
> > (define OBJ_BUSRIPPER   "S" );
> > (define OBJ_EMPTY   "0" );
> > (define OBJ_VERSION "v" );
> > (define OBJ_PLACEHOLDER "X" );
> >
> > (define STARTATTACH_ATTR"{" );  
> > (define ENDATTACH_ATTR  "}" );  
> > (define START_EMBEDDED  "[" );  
> > (define END_EMBEDDED"]" );  
> >
> > (define (akeda-sch-read sch-filename tl_bool)
> >  (let ((port (open-input-file sch-filename)))
> >(define my_page (ak-toplevel-new-page sch-filename tl_bool))
> >(define buffer "")
> >(define buf_str "")
> >(define my_line "")
> >(define new_obj_smob "")
> >(define attach_obj_smob "")
> >(define embed_obj_smob "")
> >
> >(define str_list "")
> >(define my_string "")
> >(define index 0)
> >(define num_lines 0)
> >
> >(define selected "0")
> >(define visible "0")
> >(define locked "0")
> >
> >(define schematic_attrib_type "1")
> >(define symbol_attrib_type "0")
> >
> >(define state_attach #f)
> >(define state_embed #f)
> >(define state_text #f)
> >
> >(define x2 0)
> >(define y2 0)
> >
> >(while (not (eof-object? buf_str))
> >(set! buffer (%read-line port))
> > 
> >(set! buf_str (car buffer))
> > 
> >(if (not (eof-object? buf_str))
> >(begin
> >  (set! my_line (string-split buf_str #\space))
> > 
> >  (if (string=? (list-ref my_line 0) STARTATTAC

Re: gEDA-user: ElementArc

[DJ Delorie]

> version 20070208

That's old.  We might have fixed it since then.

>   This was newly updated together with the newest Ubuntu on an AMD64.

I'm guessing it was the GTK gui, and not the Lesstif one, then?
Although, it works OK for gtk also, for me.


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Re: gEDA-user: ElementArc

[Ian Chapman]

Sorry DJ, I was using PCB version ...

This is PCB, an interactive
printed circuit board editor
version 20070208

Compiled on Jul 20 2007 at 19:19:50

This was newly updated together with the newest Ubuntu on an AMD64.

... Then File / load element data / click to footprint and
place it on a new blank screen.  I only wanted to get an outline to be able
to have it cut to size.  What looks wrong to me was on the screen.

Regards Ian.




613-287-0470 (227)

-Original Message-
From: DJ Delorie [mailto:[EMAIL PROTECTED] 
Sent: Friday, December 07, 2007 1:45 PM
To: [EMAIL PROTECTED]
Cc: geda-user@moria.seul.org
Subject: Re: gEDA-user: ElementArc


They both look fine to me, but you didn't say which GUI or exporter
you're seeing the erratic behavior in.  Some graphics libraries, like
X, act funny when you give them out-of-range angles like that, so
we've been fixing them as we encounter them.



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Re: gEDA-user: ElementArc

[DJ Delorie]

They both look fine to me, but you didn't say which GUI or exporter
you're seeing the erratic behavior in.  Some graphics libraries, like
X, act funny when you give them out-of-range angles like that, so
we've been fixing them as we encounter them.


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Re: gEDA-user: [pcb] "first board" docs

[DJ Delorie]

> I think your original idea was pretty good. It seems like a natural
> progression for learning PCB layout or evaluating the tool.

Yeah, you're probably right.  I can put the more complex board in the
user's guide, too.


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Re: gEDA-user: how to add a rat to a via?

[DJ Delorie]

> I've got a chip on my layout. In gscheme I didn't bind some of it's
> pins, though I'd like to, once in pcb, add a via and connect the pin
> to it, How do you use to do this?
> 
> In pcb, I can add rat lines from such a chip's pins to existing
> layout components but if I create a via and try to link it to it, it
> doesn't work.

You have to shut off auto-enforce-DRC, otherwise you can't connect to
anything that doesn't look like it's part of the net, according to the
netlist.

In the long run, it's better to put the pins in the schematic, because
a via with only one connection is likely to be optimized away or
inadvertently left tented, resulting in a useless trace.


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Re: gEDA-user: PCAD to GEDA (GSCHEM)

[Steven Ball]

I was doing some digging today, and look what I found:

http://www.cedcc.psu.edu/cadtools/pcaddoc/pdif.pdf

Documentation on the format of the PDIF output from PCAD.  Hope it is  
helpful.

See also:  http://www.cedcc.psu.edu/cadtools/interfaces.html

-Steve


On Nov 28, 2007, at 6:43 PM, Steve Meier wrote:

> Just to show off what I have been working. The two attached files
> include a script for reading in a schematic file. The second is my
> attempt to document the api that either exists or that I have been
> implementing. Comments, suggestions are always welcome. If we can  
> figure
> out the pcad file formats I would be happy to modify or tweek the api
> for the sake of translating the pcad files.
>
> Depending on interest I can do a code release either (as i had  
> planned)
> after I have the vhdl, spice, verilog netlist formats, or earlier  
> (after
> i complete the basic schematic, symbol file io migration to guile)  
> and a
> trivial translation application.
>
> Steve Meier
>
>
>
> Dan McMahill wrote:
>> Steven Ball wrote:
>>
>>> The PDIF writer seems to be able to convert anything to an ASCII  
>>> output.
>>>
>>> http://snurkle.net/~hamster/geda/
>>>
>>
>> By any chance does the documentation for PCAD have details on that
>> format?  If not, it looks like it could largely be figured out.
>>
>>
>>> I'll dig around and see if I can find a .pcb file to convert and  
>>> post
>>> as well.  Let me know what you think and how I can be of help.
>>>
>>
>> just to clarify, pcad uses .pcb too as the suffix.  The format you'll
>> get there is similar in style to the schematics.
>>
>>
>>
>>
>> ___
>> geda-user mailing list
>> geda-user@moria.seul.org
>> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>>
>>
>
> ;;; AKEDA - Alaskan Electronic Design Automation
> ;;; aknetlist - GNU Netlist
> ;;; Copyright (C) 2007 Stephen F Meier
> ;;;
> ;;; This program is free software; you can redistribute it and/or  
> modify
> ;;; it under the terms of the GNU General Public License as  
> published by
> ;;; the Free Software Foundation; either version 2 of the License, or
> ;;; (at your option) any later version.
> ;;;
> ;;; This program is distributed in the hope that it will be useful,
> ;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> ;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> ;;; GNU General Public License for more details.
> ;;;
> ;;; You should have received a copy of the GNU General Public License
> ;;; along with this program; if not, write to the Free Software
> ;;; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>
> ;; Inport an AKEDA style schematic as a page in libakeda
>
> (use-modules (srfi srfi-13))
> (use-modules (ice-9 popen))
> (use-modules (ice-9 rdelim))
>
>
> (define OBJ_LINE"L" );
> (define OBJ_BOX "B" );
> (define OBJ_PICTURE "G" );
> (define OBJ_CIRCLE  "V" );
> (define OBJ_NET_SEGMENT "N" );
> (define OBJ_BUS_SEGMENT "U" );
> (define OBJ_COMPLEX "C" );
> (define OBJ_TEXT"T" );
> (define OBJ_PIN "P" );
> (define OBJ_ARC "A" );
> (define OBJ_ROUTE   "R" );
> (define OBJ_THRU_HOLE   "H" );
> (define OBJ_BUSRIPPER   "S" );
> (define OBJ_EMPTY   "0" );
> (define OBJ_VERSION "v" );
> (define OBJ_PLACEHOLDER "X" );
>
> (define STARTATTACH_ATTR  "{" );  
> (define ENDATTACH_ATTR"}" );  
> (define START_EMBEDDED"[" );  
> (define END_EMBEDDED  "]" );  
>
> (define (akeda-sch-read sch-filename tl_bool)
>  (let ((port (open-input-file sch-filename)))
>(define my_page (ak-toplevel-new-page sch-filename tl_bool))
>(define buffer "")
>(define buf_str "")
>(define my_line "")
>(define new_obj_smob "")
>(define attach_obj_smob "")
>(define embed_obj_smob "")
>
>(define str_list "")
>(define my_string "")
>(define index 0)
>(define num_lines 0)
>
>(define selected "0")
>(define visible "0")
>(define locked "0")
>
>(define schematic_attrib_type "1")
>(define symbol_attrib_type "0")
>
>(define state_attach #f)
>(define state_embed #f)
>(define state_text #f)
>
>(define x2 0)
>(define y2 0)
>
>(while (not (eof-object? buf_str))
>  (set! buffer (%read-line port))
>   
>  (set! buf_str (car buffer))
>   
>  (if (not (eof-object? buf_str))
>  (begin
>(set! my_line (string-split buf_str #\space))
>   
>(if (string=? (list-ref my_line 0) STARTATTACH_ATTR)
>(begin
>  (set! state_attach #t)
>  (set! attach_obj_smob new_obj_smob)
>  )
>)
>   
>(if (string=? (list-ref my_line 0) ENDATTACH_ATTR)
>(begin
>  (set! state_attach #f)
>  )
>  

Re: gEDA-user: Subscribing to this list

[Ian Chapman]

Hi Alan, a copy of my original post has been sent to Ales Hvezda.  I guess
he is a busy guy and looking after us and other groups is not his day job.
Regards  Ian.

  _  

From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] 
Sent: Friday, December 07, 2007 7:53 AM
To: [EMAIL PROTECTED]; gEDA user mailing list
Subject: RE: gEDA-user: Subscribing to this list

 

And when I tried to modify my subscription from receiving individual emails
to receiving a daily digest, the instructions at
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user were not as clear as
they could have been about how to do that. The page claims that it allows me
to "change your existing subscription". That capability is actually under
"geda-user Subscribers" (a logical place), but that section begins with "The
subscribers list is only available to the list administrator", leading me to
the false conclusion that there was nothing in that section for me. Simply
moving that message under the subscribers list feature would make the page
clearer. My false conclusion caused me to try to subscribe again, selecting
daily digest, but that failed because of my existing subscription.

By the way, Ian, whomever you "should e-mail and suggest an update" should,
in my opinion, already be monitoring this list.

Alan Feldstein
Cosmic Horizon
http://www.alanfeldstein.com/




 Original Message 
Subject: gEDA-user: Subscribing to this list
From: "Ian Chapman" <[EMAIL PROTECTED]>
Date: Thu, December 06, 2007 8:56 am
To: 

If I follow the subscribe instructions on
http://archives.seul.org/geda/user/ it returns 
 subscribe geda-user
 subscribe: unknown list 'geda-user'.
 
 Help for [EMAIL PROTECTED]
 :

I went into one of the posts hack about and picked up
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

followed my nose and managed to subscribe. I wonder who I should I should
e-mail and suggest an update?

Regards Ian.



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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[John Griessen]

Steve Meier wrote:
> John Doty wrote:
>> The interesting idea so far in this discussion has been to let the  
>> BOM be source rather than product.
>>
>>   
> Dang, That was the idea I intentionally left out of my last diatribe.
> And you cut right to it. I agree, that the world being bom specific as
> opposed to schematic specific is interesting even if i havn't got a
> clear vission oh what being bom specific means. I was going to ask, that
> does being bom specific mean that we build new designs with an a
> bias to the components we already have?

That we do engineering always conscious of cost vs. performance is all 
it means to me.


> 
> Seems like the purchasing department/ inventory management groups might
> like the idea?

Sure.

> 
> I would rather find a way to describe a problem economically... The cost
> of using one component over another as long as the availability and
> capability of the componet doesn't become an issue,  should determine
> the selection of the component.
> 
> Or, should the potential future cost of a component be includded in the
> selection of what goes into the new design?

don't forget the incremental cost of making a change of any kind...


John G

-- 
Ecosensory


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Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such

[John Griessen]

al davis wrote:
> On Thursday 06 December 2007, Steve Meier wrote:
>

> Steve also said this in private mail (I hope you don't mind my 
> repeating it in public):
>> I actually think that one of the rather remarkable things
>> about geda is the use of a macro language to generate the
>> output.
>   repeated because I agree with it, strongly.
> 
> On Thursday 06 December 2007, John Doty wrote:
>>  I have no strong preference as  
>> long as the result retains gEDA's flexibility.
> ... also repeated because I agree with it, strongly.
> 
> Those last two points are so strong that if the format fails to 
> meet either, it must be rejected.
>

So, guile/scheme has macro capability enough, but isn't much like m4...
That's not a problem, is it?

John Griessen

-- 
Ecosensory


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gEDA-user: ElementArc

[Ian Chapman]

Hi,

I am making a base for a toroid transformer and I am using an
element footprint as the basis for the design.  I have used a spread sheet
to calculate the mounting holes base on 120 degree spacing.  I have three
arcs between the tabs to define the outline between the tabs.  Using the
information from footprint creation last updated by Stuart D. Brorson
01/29/2005 it looks like the arc starts at 0 degree = 9pm and goes ACW not
CW.  I can live with that.  Where I have a problem is starting the arc
between about 330 and 359 degrees.  It seems to be quite erratic.  I have
attached my footprint and a test footprint that I hope highlights the
problem so that I can be helped.

 

Regards Ian.

 

FOOTPRINT.

Element(0x0 "NanoCrystal Xf base" "" "" 0 0 -30 -80 0 100 0x0)

(

   Pin(0 1104 142 200 162 170 "" "1" 0x0008)

   Pin(956 -552 142 200 162 170 "" "2" 0x0008)

   Pin(-956 -552 -55 200 162 170 "" "3" 0x0008)

 

   Pin(0 1360 142 200 162 170 "" "4" 0x0008)

   Pin(1178 -680 142 200 162 170 "" "5" 0x0008)

   Pin(-1178 -680 142 200 162 170 "" "7" 0x0008)

 

   Pin(0 1940 142 200 162 170 "" "7" 0x0008)

   Pin(1680 -970 142 200 162 170 "" "8" 0x0008)

   Pin(-1680 -970 142 200 162 170 "" "9" 0x0008)

 

   ElementArc(0 0 1934 1934 0 360 5)

   ElementArc(0 0 804 804 0 360 50)

   ElementArc(0 0 1104 1104 0 360 5)

   ElementArc(0 0 1360 1360 0 360 5)

   ElementArc(0 0 2184 2184 0 360 5)

 

   ElementArc(0 0 1660 1660 97 106 75)

   ElementArc(0 0 1660 1660 217 106 50)

   ElementArc(0 0 1660 1660 337 106 100)

 

   ElementLine(236 2171 -236 2171 50)

   ElementLine(1762 -1290 1998 -881 50)

   ElementLine(-1998 -881 -1762 -1290 50)

 

   ElementLine(236 2171 202 1648 50)

   ElementLine(1762   -1290 1326 -999 50)

   ElementLine(-1998 -881 -1528 -649 50)

 

   ElementLine(-236 2171 -202  1648 50)

   ElementLine(1998 -881 1528 -649 50)

   ElementLine(-1762 -1290 -1326 -999 50)

 

   ElementLine(166 1350 -166 1350 5)

   ElementLine(1086 -818 1252 -531 5)

   ElementLine(-1251 -531 -1086 -818 5)

)

 

TEST

Element(0x0 "Test" "" "" 0 0 -30 -80 0 100 0x0)

(

   Pin(0 1104 142 200 162 170 "" "1" 0x0008)

   Pin(956 -552 142 200 162 170 "" "2" 0x0008)

   Pin(-956 -552 -55 200 162 170 "" "3" 0x0008)

 

   Pin(0 1360 142 200 162 170 "" "4" 0x0008)

   Pin(1178 -680 142 200 162 170 "" "5" 0x0008)

   Pin(-1178 -680 142 200 162 170 "" "7" 0x0008)

 

   Pin(0 1940 142 200 162 170 "" "7" 0x0008)

   Pin(1680 -970 142 200 162 170 "" "8" 0x0008)

   Pin(-1680 -970 142 200 162 170 "" "9" 0x0008)

 

   

   ElementArc(0 0 1000 1000 0 45 150)

   ElementArc(0 0 500 500 320 10 25)

   ElementArc(0 0 600 600 330 20 50)

   ElementArc(0 0 700 700 340 30 75)

   ElementArc(0 0 800 800 350 40 100)

)

 



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Re: gEDA-user: how to add a rat to a via?

[Peter Clifton]

On Fri, 2007-12-07 at 00:01 -0800, Steve Meier wrote:
> ahhh a rat in my mind is a potential trace between two points of a
> netlist. If you want to draw a trace that isn't part of the netlist then
> a rat has no meaning.
> 
> at least in my mind.

You can actually build a rats-nest in PCB, in very limited
circumstances. (Select the rats layer, and line tool), It doesn't like
you joining two objects which are already parts of different nets, which
is (I expect) why the OP's having difficulties.

The more useful answer..

Its best to wire everything up in gschem, as "back annotation" which
might allow you to wire up in PCB, then fix the schematic to match isn't
really possible yet.

If you turn off DRC checks, then wire things together in PCB which
aren't connected in the schematic, you will find it difficult to keep
track of any mistakes for the design in general.

Best wishes,

Peter C.




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Re: gEDA-user: updating your OS, was: Re: Export gerber crash

[Ian Chapman]

Hi Peter and many thanks.  This partial upgrade stuff, not too sure but
I sent your e-mail, closed all windows and found the last widow telling
me to click okay to finish the download.  It took about 2.5 hours at
70kB/s and now I have a new PCB.  I will start a new thread from work as
I think I have found a bug with ElementArc.  So I am almost up to all
the other people.  Thanks again Ian.

 This is PCB, an interactive
printed circuit board editor
version 20070208

Compiled on Jul 20 2007 at 19:19:50



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Re: gEDA-user: Subscribing to this list

[alan]

And when I tried to modify my subscription from receiving individual emails to receiving a daily digest, the instructions at http://www.seul.org/cgi-bin/mailman/listinfo/geda-user were not as clear as they could have been about how to do that. The page claims that it allows me to "change your existing
	subscription". That capability is actually under "geda-user Subscribers" (a logical place), but that section begins with "The subscribers list is only available to the list administrator", leading me to the false conclusion that there was nothing in that section for me. Simply moving that message under the subscribers list feature would make the page clearer. My false conclusion caused me to try to subscribe again, selecting daily digest, but that failed because of my existing subscription.By the way, Ian, whomever you "should e-mail and suggest an update" should, in my opinion, already be monitoring this list.Alan FeldsteinCosmic Horizonhttp://www.alanfeldstein.com/

 Original Message 
Subject: gEDA-user: Subscribing to this list
From: "Ian Chapman" <[EMAIL PROTECTED]>
Date: Thu, December 06, 2007 8:56 am
To: 

If I follow the subscribe instructions on
http://archives.seul.org/geda/user/ it returns 
 subscribe geda-user
 subscribe: unknown list 'geda-user'.
 
 Help for majordomo@seul.org:

I went into one of the posts hack about and picked up
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

followed my nose and managed to subscribe.  I wonder who I should I should
e-mail and suggest an update?

		Regards Ian.



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Re: gEDA-user: updating your OS, was: Re: Export gerber crash

[Peter Clifton]

On Thu, 2007-12-06 at 22:28 -0500, Ian Chapman wrote:

> > After this, try the upgrade again.
> Oh no. support for gnome cups manager has ended.  I'll sort out the
> printer if necessary.  Other than that and a few not supported libs that
> I do not understand it seems to be okay.  Upgrades available but not all
> can be installed due to previous upgrade incomplete.  Can upgrades and
> figure it out after maybe a restart?

A "partial" upgrade can sometimes help here. These are used if some
conflicts must be broken before continuing.

I didn't notice gnome-cups-manager had gone... I just thought it had got
better. Turns out, the new functionality is in the package
"system-config-printer".

If you still have problems with the upgrade, try from a terminal:

sudo apt-get update
sudo apt-get upgrade
and
sudo apt-get dist-upgrade

(If it complains of any conflicts, or tries to remove hundreds of
packages, post which here).

Hope the upgrade goes smoothly!

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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Re: gEDA-user: [pcb] "first board" docs

[John Luciani]

On Dec 7, 2007 1:27 AM, DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> > Third: 555 SMT blinky.  Same thing, but mostly SMT, with a ground
> > plane on the back.  This introduces SMT, vias, and thermals.
>
> I'm thinking of something that uses two chips, like a USB to RS232
> converter, so I can put stuff on both sides, force vias, etc.  Too
> much?

I think your original idea was pretty good. It seems like a natural
progression for learning PCB layout or evaluating the tool.

1. Very simple board with old technology
2. Simple board with old technology
3. Update of simple board to modern technology

(* jcl *)

-- 
http://www.luciani.org


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Re: gEDA-user: how to add a rat to a via?

[Dave N6NZ]

Lope De Vega wrote:
> Hello,
> 
> I've got a chip on my layout. In gscheme I didn't bind
> some of it's pins, though I'd like to, once in pcb,
> add a via and connect the pin to it, How do you use to
> do this?

Are you trying to add "break out" pads so that you can get to the pins 
in a prototyping area?  The cleanest solution to that problem that I've 
come up with is to insert a very simple symbol into the schematic, and 
assign it a footprint that is just a pin with an appropriate drill and 
annulus.  That way everything appears in the netlist and all tools are 
happy.  You can turn off DRC and force the trace, but I'd rather not try 
to outsmart DRC.

This symbol consists of one pin and a circle.  The refdes is in under 
sized text to keep clutter off the schematic, but you could easily tweak 
that.

$ more protopad-1.sym
v 20060123 1
T 300   0 5  5 1 1 0 1 1
refdes=P?
T 300 600 5 10 0 0 0 0 1
device=PROTOPAD
T 300 800 5 10 0 0 0 0 1
uselicense=unlimited
T 300 1000 5 10 0 0 0 0 1
distlicense=GPL
T 300 1200 5 10 0 0 0 0 1
description=Prototyping pad
T 300 1400 5 10 0 0 0 0 1
numslots=0
T 300 1600 5 10 0 0 0 0 1
footprint=proto22pad
T 300 1800 5 10 0 0 0 0 1
author=DB Curtis [EMAIL PROTECTED]
T 300 2000 5 10 0 0 0 0 1
copyright=(C) 2006 David B. Curtis
P 0 0 125 0 1 0 0
{
T 100 20 5 8 0 1 0 3 1
pinnumber=1
T -200 320 5 8 0 0 0 6 1
pinseq=1
T -1100 320 5 8 0 0 0 6 1
pintype=pas
}
V 200 0 75 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1


Here's a pad to go with it, I have several:

Element(0x10 "Prototyping pad, #22 wire" "" "" 200 200 0 100 0 100 
0x)
(
 # 11-Jun-2007
 # hand generated
 # clearance 8 mil
 # mask relief 4 mil
 # Slightly oversize pad for easier soldering, but
 # should allow two 8 mil tracks between pads on 100 mil ctrs.
 Pin(0 0 58 16 66 35 "" "1" 0x0001)
)

-dave


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Re: gEDA-user: how to add a rat to a via?

[Steve Meier]

ahhh a rat in my mind is a potential trace between two points of a
netlist. If you want to draw a trace that isn't part of the netlist then
a rat has no meaning.

at least in my mind.

Steve M.

Lope De Vega wrote:
>> Check me if I am wrong... you have a pin that isn't
>> part of a net and
>> you are trying to route a trace from that pin to a
>> via. And it won't
>> physically connect to the via?
>> 
>
> That's exactly what I was trying to say, sorry my
> english. As you say, if I turn off "autoenforce DRC
> clearance" I can then draw a line (not a rat) from the
> pin to the via, perhaps this is the way of doing it.
>
> I've only checked this with a unfinished layout, so
> perhaps going this way could have side effects I don't
> know about,  or maybe it should just leave this step
> to the end of process so it won't break anything.
>
> Thanks.
>
>
>   
>>  Steve M.
>>
>> Lope De Vega wrote:
>> 
>>> --- Steve Meier <[EMAIL PROTECTED]>
>>>   
>> wrote:
>> 
>>>   
>>>   
 Dang first though that came through my brain was
 
>> the
>> 
 concept of trying
 to shove a rat down a via.

 When you say it doesn't work are you talking
 
>> about
>> 
 the drc complaining?

 Steve Meier

 
 
>>> Am no, it doesn't complain, but it doesn't work,
>>>   
>> nor
>> 
>>> to a via or to a hole. What I'm doing is selecting
>>>   
>> the
>> 
>>> pin with the line tool trying to draw a line from
>>>   
>> it
>> 
>>> to via, though it doesn't stick to it.
>>>
>>>   
>>>   
 Lope De Vega wrote:
 
 
> Hello,
>
> I've got a chip on my layout. In gscheme I
>   
>> didn't
>> 
>   
>   
 bind
 
 
> some of it's pins, though I'd like to, once in
>   
>   
 pcb,
 
 
> add a via and connect the pin to it, How do you
>   
>   
 use to
 
 
> do this?
>
> I've tried connecting it to a terminal in
>   
>> gscheme
>> 
>   
>   
 and
 
 
> just leaving it like that, though I'm curious. 
>
> In pcb, I can add rat lines from such a chip's
>   
>   
 pins to
 
 
> existing layout components but if I create a via
>   
>   
 and
 
 
> try to link it to it, it doesn't work.
>
> Regards.
>
>
>
>
>  
>   
>   
> 
>   
>>>   
>>>   
> Looking for last minute shopping deals?  
> Find them fast with Yahoo! Search. 
>   
>   
> http://tools.search.yahoo.com/newsearch/category.php?category=shopping
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