Re: gEDA-user: Thanks a million, and few small questions for a new user
> If I were to see if I were able to make thermals automatic, where would > I start looking, and in which file? The best time to do net-related work is in the 'o' key functions, since that's when we tag everything. Other times, the individual items in pcb don't just "know" what they're supposed to be connected to. PCB does often know when a pad should be connected to a polygon, though, and uses a small circle to denote that. > Are thermals objects, or are they just a "Yes/No" (and size,layer) flag > for every pin? They're flags, one per layer per pin/via. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thanks a million, and few small questions for a new user
Thank you all very much for the quick and helpful answers! As I suspected, it was mostly user error on my part! All of my questions to date have been answered! (I was trying to use :DRC() to check for shorts -- but the "o" key does that, as it should!) (Once I knew that DRC makes sure that objects, regardless of net, are either touching or not too close, and that the net-based rules are enforced via the o key, then DRC works perfectly!) You guys have done a great job on this! If I were to see if I were able to make thermals automatic, where would I start looking, and in which file? Can I currently assign a net to a poly, or does a poly automatically assign itself a net as soon as it is physically wired to a net? (For example, if the user had to just put in a single thermal such that PCB knew what net it was, then thermals could be "turned on" for each puncturing pin of the same net.) I'm not a great programmer, but I'd be delighted to give it a try! Are thermals objects, or are they just a "Yes/No" (and size,layer) flag for every pin? Having not yet looked into the code enough to understand the whole-system mode of operation, I don't know for sure, but I can imagine a simple routine which is run for each screen update which checks to see if any pins go through a polygon which is set to their net, and then turning on the thermal for that pin and that layer, otherwise turning off the thermal for that pin and layer. Tell me if I have all the wrong idea. Thank you all very much, Jesse DJ Delorie wrote: I can't figure out how to make it automatically place thermals when a pin goes through a floodfill(polygon) of the same net. PCB doesn't do this automatically, but if you wanted an easy project to get involved in, adding it would be easy :-) I can't figure out how to make a second silkscreen layer (for the other side) (The layer I created seems to route like copper.) "Tab" to flip the board over. There are two silk layers, but it always draws to the one on "top". but it always says this even when I have a trace cutting across other traces and parts, and when I have installed thermals where they should not be. Sample board? You do have a netlist loaded, visible, and optimized, yes? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem, howto make all pinnumbers invisible
Hello, most non trivial symbols have visible pin numbers, i.e. symbols generated with tragesym. This is fine. We can make these pinnumbers invisible by modifying the symbol -- pin for pin. It may be useful to make all pinnumbers invisible for a whole symbol in a schematic, i.e. when making publications. Is this possible? If not, i would suggest a new attribute like "showpinnumbers=0" for gschem-symbols. Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thanks a million, and few small questions for a new user
> I can't figure out how to make it automatically place thermals when a > pin goes through a floodfill(polygon) of the same net. PCB doesn't do this automatically, but if you wanted an easy project to get involved in, adding it would be easy :-) > I can't figure out how to make a second silkscreen layer (for the other > side) (The layer I created seems to route like copper.) "Tab" to flip the board over. There are two silk layers, but it always draws to the one on "top". > but it always says this even when I have a trace cutting across > other traces and parts, and when I have installed thermals where > they should not be. Sample board? You do have a netlist loaded, visible, and optimized, yes? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thanks a million, and few small questions for a new user
On Sat, 22 Mar 2008 09:27:54 -0700, Jesse Gordon wrote: > I can't figure out how to make a second silkscreen layer (for the other > side) (The layer I created seems to route like copper.) Silkscreen layers for both sides of the board are configured by default. To place text or lines on solder silk you have to flip the board with the tab key (or shift-tab if you prefer a left-right flip). This is like physically turning the board to the other side. Imageine, the solder layer is on top, and component layer is bottom. Objects on component silk layer will be greyed out. If you draw to silk, lines will always go to the current top silk layer, which is solder now. The same happens to components and their silk screen. ---<(kaimartin)>--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thanks a million, and few small questions for a new user
>I just downloaded the ISO and compiled/installed pcb version 20070208 >today and let me say that I am very impressed! >Thanks very much for the automated installer process. You don't know how >nice that was. I use slackware, and, well, Note, this ISO installer is getting a bit dated. I have a new version (0.0.2) of my binary suite w/ installer in the works. I just need to finish off the last few bits of testing and then I'll release it (hopefully within a week or so). There have been lots of improvements in pcb since 20070208 (the current version of pcb is 20080202). -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thanks a million, and few small questions for a new user
Jesse Gordon wrote: > I can't figure out how to make a second silkscreen layer (for the other > side) (The layer I created seems to route like copper.) Try using the s or s key to change sizes. Use s on a via to make smaller then you'll see the min annular ring criterion. Use s on a trace until it gets near another and you'll see the space criterion. Perhaps your default rules were set to draw with DRCs on all the time. That way you would not have any, but would be limited in some choices. > > After routing up my layout, I typed :DRC() and the log window just said > "Rules are minspace 8.01, minoverlap 8.0 minwidth 8.00, minsilk 6.00 > min drill 15.00, min annular ring 10.00 > No DRC problems found." > but it always says this even when I have a trace cutting across other > traces and parts, That may not be a bug. pcb doesn't have much inference reasoning going on. No AI. > Where would I look to learn how to use it or how to fix it? Try the above tests, and I will send you an exaple layout with errors to try also. John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Thanks a million, and few small questions for a new user
Dear gEDA developers, I just downloaded the ISO and compiled/installed pcb version 20070208 today and let me say that I am very impressed! Thanks very much for the automated installer process. You don't know how nice that was. I use slackware, and, well, you know slackware needed all of those graphics support (like cairo, etc.) packages to be installed, and it was great! Having gerbv is super handy too! Thanks very much! Anyway, after going through the fine tutorial and making the circuit board and all that, and trying out lots of different things I found myself unable to do a few things and I suspect it's just user error. (And I did skim through the manual and worked on it for several hours today, just so you know I didn't write without really trying.) I can't figure out how to make it automatically place thermals when a pin goes through a floodfill(polygon) of the same net. (So if I had 10 ICs each with 4 grounded pins, I'd have to go place 40 thermals, maybe this is not yet a feature.) I can't figure out how to make a second silkscreen layer (for the other side) (The layer I created seems to route like copper.) After routing up my layout, I typed :DRC() and the log window just said "Rules are minspace 8.01, minoverlap 8.0 minwidth 8.00, minsilk 6.00 min drill 15.00, min annular ring 10.00 No DRC problems found." but it always says this even when I have a trace cutting across other traces and parts, and when I have installed thermals where they should not be. I'm assuming that the DRC() function works for others, since the manual seems to indicate how it works. I've not so far been able to find any error I can introduce to cause the :DRC() command to say anything other then "No DRC problems found." Where would I look to learn how to use it or how to fix it? I've been using linux at the command-line level for years so I'm not afraid to go type commands and look through files or logs and stuff. Anyway, I'm very happy! You guys are doing a wonderful work on this. Thanks very much, -Jesse ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation problem
On Fri, 2008-03-21 at 13:47 +0100, Willem Granjé wrote: > Hello, > > I upgraded geda to 1.4, > > starting gschem revealed that the component-library could not be found > anymore... > > where is it, how do I configure gschem to find it? Let me guess.. Debian testing? Last I checked, not all of gEDA 1.4.0 had migeated to testing. There is an incompatibility between gEDA symbols 1.4.0 (in testing) and the old version of libgeda + gschem (not yet in testing). You could either fetch all the 1.4.0 packages from Unstable (sid), or move the component library config file from its new (1.4.0) location back to its old (pre 1.4.0): mv /usr/share/gEDA/gafrc.d/geda-clib.scm /usr/share/gEDA/scheme/ You may need to revert this once the rest of gEDA is installed. Alternatively, if I guessed wrong, and you do have gschem and libgeda 1.4.0 fully installed (you should be able to see the version strings when starting up gschem from a command line), then perhaps you haven't got geda-symbols 1.4.0 properly installed. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gsch2pcb: Unbound variable error
On Fri, 2008-03-21 at 07:06 -0500, Ken Lauffenburger wrote: > When running gsch2pcb on a simple schematic I get the following error: > > ERROR: Unbound variable: nil > Running command: > gnetlist -g PCB -o antennas.net antennas_v1.sch > > Any ideas on what is causing this? Any reason to be concerned? I suspect that you're using a version of gEDA compiled against guile 1.8, prior to a necessary fix. Guile 1.8 doesn't support "nil" any more. The best plan is to upgrade to the latest gEDA release (1.4.0), as it has _MANY_ bug fixes. How / where did you get gEDA from? (compiled from source / distro package - which distro and version?) Alternatively, find the .scm files in /usr/share/gEDA/scheme, and find occurrences of "nil" using "grep nil *.scm". The substitutions suitable are either "#f" or "'()" (no quotes in either case). I'd use #f unless the comments around that usage suggest the variable is a list. I'd not trust the output netlist to be correct unless this is fixed, since as soon as the ERROR: is emitted, no further processing takes place. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
