Re: gEDA-user: Power (and other non-graphical) pins
On Tue, Jan 13, 2009 at 7:57 PM, DJ Delorie <[1...@delorie.com> wrote: > "It only has to live a couple of hours" I've made circuits like that. Not always intentionally, though. You can buy parts from Vishay that do "rapid spontaneous disassembly" by design: "Exploding/Magic Smoke Resistors now available off-the-shelf", [2]http://blog.obscureresearch.net/epic and long ago from National Semi: [3]http://www.national.com/an/AN/AN-761.pdf -- [4]http://www.wearablesmartsensors.com/ [5]http://www.softwaresafety.net/ [6]http://www.designer-iii.com/ [7]http://www.unusualresearch.com/ References 1. mailto:d...@delorie.com 2. http://blog.obscureresearch.net/epic 3. http://www.national.com/an/AN/AN-761.pdf 4. http://www.wearablesmartsensors.com/ 5. http://www.softwaresafety.net/ 6. http://www.designer-iii.com/ 7. http://www.unusualresearch.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Wed, Jan 14, 2009 at 12:53 AM, Joerg wrote: > > Yes, because you guys don't have to pay 2-3c for each additional > transistor or 5c per FET :-) At least not for those working. :-) > "But it'll electromigrate itself to death in less than a year" ... "It > only has to live a couple of hours" ... "Oh". Lucky you! In some of our circuits (mostly in RF blocks) getting the layout electromigration clean was really painful. It's not only because of the layout (although this stuff can grow pretty big) but also performance - adding several fat connections with their parasitics can kill otherwise carefully crafted circuit. The verification method is also a major pain in ass. We have learned the hard way to anticipate these problems early, and to employ various sometimes non-obvious tricks to work them around. And that's only one problem, what about decoupling, multiple power domains (for noise filtering and for power-down functions), well biasing, voltage drops, ringing and ESD protection? Regards, -r ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
> "It only has to live a couple of hours" I've made circuits like that. Not always intentionally, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
r wrote: > On Tue, Jan 13, 2009 at 8:47 PM, Joerg wrote: >> The backplanes in our ultrasound systems are >> usually north of 4000 pins and I have never seen a case where there was >> not a schematic for that. > > In analog IC design it's fairly easy to get schematics even bigger > than this - that's what you get when you extract the layout. Sure, > transistor level netlist would do fine for simulation but it is simply > convenient to have an extracted schematic of the cell (if only for > netlisting, DRC checks, manually finding some internal devices/nodes). > Yes, because you guys don't have to pay 2-3c for each additional transistor or 5c per FET :-) >> Ok, if gEDA is geared towards ASIC/FPGA that's different. Then it sure >> won't be my kind of tool, just like BAE isn't (had tried it out lately). > > Believe it or not, gEDA actually strongly focuses on the PCB flow. > Just look at the symbol attributes - pin numbers, footprints, even > reference designators come in PCB flavor. There is only partial > support for the design hierarchy, partial support for libraries, > partial support for other types of design data (RTL, netlists), no > functional netlisters, no DRC checks on the design. These issues can > often be "fixed" using external tools (makefiles, own netlisters and > rule checkers) but they are enough to discourage most designers from > even trying the tool. To be honest, looking at the traffic on this > list, I thought the PCB flow support is fairly decent (or the only one > that works, for that matter). > > BTW, analog IC guys long since have given up using implicit power > connections and multi-slot symbols. People simply draw all the power > lines just like any other wires (sometimes even explicitly modeling > them with L/R/C circuits). Same with the cells (symbols in the PCB > world) - the closer the symbol is to its > schematic/RTL/layout/extracted view, the better, if only for LVS-ing > the design or juggling with schematic/extracted views in simulations - > multiple slots only add unnecessary complexity to the design. Such > schematics are perhaps a bit more difficult to understand but easier > to work with. > Same with us discrete circuit and RF designers. We rarely use inherent supply pins. Now that RF and digital heads for the GHz ranges that area will soon face similar challenges. In a chip you are right, inherent would be almost impossible because every connection is a resistor/inductor. Even the substrate is. On one of the HV chips I designed we drove it so far that the fab guys said "But it'll electromigrate itself to death in less than a year" ... "It only has to live a couple of hours" ... "Oh". -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Dan McMahill wrote: > Joerg wrote: >> I started out with Futurenet Dash-2 in 1986, then Dash-4, then >> self-employed with Orcad as my tool, later through several versions of >> that and a few years ago switched to Eagle. That's what I am using right >> now until I find something better. Eagle won't handle hierarchies, other >> than that it is nearly ideal. > > then you'll be glad to know that gnetlist contains a backend for > producing futurenet2 netlists from your gschem schematics! > Wow! Now that's really retro. I wonder if it could also output for Rubylith :-) -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Joerg wrote: > I started out with Futurenet Dash-2 in 1986, then Dash-4, then > self-employed with Orcad as my tool, later through several versions of > that and a few years ago switched to Eagle. That's what I am using right > now until I find something better. Eagle won't handle hierarchies, other > than that it is nearly ideal. then you'll be glad to know that gnetlist contains a backend for producing futurenet2 netlists from your gschem schematics! -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Tue, Jan 13, 2009 at 8:47 PM, Joerg wrote: > The backplanes in our ultrasound systems are > usually north of 4000 pins and I have never seen a case where there was > not a schematic for that. In analog IC design it's fairly easy to get schematics even bigger than this - that's what you get when you extract the layout. Sure, transistor level netlist would do fine for simulation but it is simply convenient to have an extracted schematic of the cell (if only for netlisting, DRC checks, manually finding some internal devices/nodes). > Ok, if gEDA is geared towards ASIC/FPGA that's different. Then it sure > won't be my kind of tool, just like BAE isn't (had tried it out lately). Believe it or not, gEDA actually strongly focuses on the PCB flow. Just look at the symbol attributes - pin numbers, footprints, even reference designators come in PCB flavor. There is only partial support for the design hierarchy, partial support for libraries, partial support for other types of design data (RTL, netlists), no functional netlisters, no DRC checks on the design. These issues can often be "fixed" using external tools (makefiles, own netlisters and rule checkers) but they are enough to discourage most designers from even trying the tool. To be honest, looking at the traffic on this list, I thought the PCB flow support is fairly decent (or the only one that works, for that matter). BTW, analog IC guys long since have given up using implicit power connections and multi-slot symbols. People simply draw all the power lines just like any other wires (sometimes even explicitly modeling them with L/R/C circuits). Same with the cells (symbols in the PCB world) - the closer the symbol is to its schematic/RTL/layout/extracted view, the better, if only for LVS-ing the design or juggling with schematic/extracted views in simulations - multiple slots only add unnecessary complexity to the design. Such schematics are perhaps a bit more difficult to understand but easier to work with. Regards, -r ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 13, 2009, at 2:00 PM, DJ Delorie wrote: > Each geda user is going to > have a preferred way of doing things, "*A* preferred way". Actually, I have several. Depends on the project and customer. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
> Well ~25 years ago, you didn't need no stinkin layout program you > just wire wrapped from the net list which was hand generated. I > still have holes in my fingers from those bloody pins. I still have my wire wrapping tool. Still use it too, especially the wire stripper - handy for wire fixing a board. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Well ~25 years ago, you didn't need no stinkin layout program you just wire wrapped from the net list which was hand generated. I still have holes in my fingers from those bloody pins. On Tue, 2009-01-13 at 16:00 -0500, DJ Delorie wrote: > > Sure, but I don't think that's what gEDA was meant to do. > > But geda *was* meant to be able to hook in other sources of data. > > > Ok, if gEDA is geared towards ASIC/FPGA that's different. > > It's not - *his* work is geared towards it, and he had a way to make > geda work smoothly with his data needs. Each geda user is going to > have a preferred way of doing things, and geda needs to be amenable to > all of those. *Some* will be defaults, but others may need some > custom geda setups to flow smoothly. > > > Wow. With CAD? My first CAD exposure was Racal-Redac on a VAX but being > > Oh crap, now we're reminiscing. 20 years ago I started with Data > General's internal CAD system on D470C terminals. A few years later > we switched to Cadstar, and a long hiatus later, I'm using gEDA. > > > young I could only get after-midnight time slots so I resorted to vellum > > and ink pens. > > mmm... pens, stickers, and FeCl from Radio Shack. That was about 30 > years ago for me. I still have some of the stickers, too. > > > Again, I don't want it to cater to me. I might never use gschem, > > just wanted to give feedback. > > What about PCB, though? That runs on Linux/Mac/Windows too. > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
DJ Delorie wrote: >> Sure, but I don't think that's what gEDA was meant to do. > > But geda *was* meant to be able to hook in other sources of data. > >> Ok, if gEDA is geared towards ASIC/FPGA that's different. > > It's not - *his* work is geared towards it, and he had a way to make > geda work smoothly with his data needs. Each geda user is going to > have a preferred way of doing things, and geda needs to be amenable to > all of those. *Some* will be defaults, but others may need some > custom geda setups to flow smoothly. > >> Wow. With CAD? My first CAD exposure was Racal-Redac on a VAX but being > > Oh crap, now we're reminiscing. 20 years ago I started with Data > General's internal CAD system on D470C terminals. A few years later > we switched to Cadstar, and a long hiatus later, I'm using gEDA. > I started out with Futurenet Dash-2 in 1986, then Dash-4, then self-employed with Orcad as my tool, later through several versions of that and a few years ago switched to Eagle. That's what I am using right now until I find something better. Eagle won't handle hierarchies, other than that it is nearly ideal. >> young I could only get after-midnight time slots so I resorted to vellum >> and ink pens. > > mmm... pens, stickers, and FeCl from Radio Shack. That was about 30 > years ago for me. I still have some of the stickers, too. > I always keep a stash of large vellum pads. Clearprint 1000HP, the good stuff from California. >> Again, I don't want it to cater to me. I might never use gschem, >> just wanted to give feedback. > > What about PCB, though? That runs on Linux/Mac/Windows too. > In my case nearly all layouts are done by a layouter. The lone exception would be a super-critical RF or switcher designs where I lay out the hot stuff and send that to the layouter to tell him how I want that area done. Currently he uses PADS. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
> Sure, but I don't think that's what gEDA was meant to do. But geda *was* meant to be able to hook in other sources of data. > Ok, if gEDA is geared towards ASIC/FPGA that's different. It's not - *his* work is geared towards it, and he had a way to make geda work smoothly with his data needs. Each geda user is going to have a preferred way of doing things, and geda needs to be amenable to all of those. *Some* will be defaults, but others may need some custom geda setups to flow smoothly. > Wow. With CAD? My first CAD exposure was Racal-Redac on a VAX but being Oh crap, now we're reminiscing. 20 years ago I started with Data General's internal CAD system on D470C terminals. A few years later we switched to Cadstar, and a long hiatus later, I'm using gEDA. > young I could only get after-midnight time slots so I resorted to vellum > and ink pens. mmm... pens, stickers, and FeCl from Radio Shack. That was about 30 years ago for me. I still have some of the stickers, too. > Again, I don't want it to cater to me. I might never use gschem, > just wanted to give feedback. What about PCB, though? That runs on Linux/Mac/Windows too. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Mental note of bug on MINGW port
Seems the mingw (tested under wine) c library's sscanf is mistreating the format strings in Peter B's new colour processing, and trampling more memory than it ought to. %02hhx is not being correctly treated. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John Doty wrote: > On Jan 12, 2009, at 4:05 PM, Joerg wrote: > >> John Doty wrote: Take a device with multiple parts in there such as the 74HC14 and handle it like Eagle and Orcad do: None of them has power symbols. Then if you must connect it to some special power net you can "invoke" the power symbols along with correct pin numbers on only the first instantation. So U1A then has power symbols but U1B, U1C and so forth don't. The power pins absolutely must show up in the schematic where you want them and not show up at the instantation where you don't want them. >>> Sounds miserably complex and inflexible. While with gEDA, you break >>> the physical device up however you choose, into as many symbols as >>> you want, and there's nothing magical about power pins. >>> >> It isn't complex and inflexible. It's how scores of engineers work ;-) > > But others of us *don't* work that way. It doesn't scale well to > complex heterogeneous modules. > >> If they only show up in the netlist that doesn't work because the schematic will be hard to understand. >>> The pinlists for power and connectors show up in the documentation. I >>> think that's *easier* to understand than graphics. >>> >> Sorry, but I must disagree here. The schematic is generally the only >> document accepted to understand a circuit. > > In your world, maybe. In mine, schematics are only a modest part of > the documentation. > Then we are working in different worlds. But at least we both worked with CCD imagers :-) >> In design reviews, > > The schematics are only part of the story. In a NASA design review, > the majority of the reviewers won't even look at them. > Last one I saw was mostly schematics and mechanical CAD. >> for the >> TUEV inspector, and so on. They do not want to have to thumb through >> reams of paper to find which net something invisible is connected to. > > A schematic of a 2000 pin backplane is pretty useless, while the same > data in a human-friendly tabular form makes it really easy to find > where to put the scope probe. > Sure, but I don't think that's what gEDA was meant to do. That's what Excel or OpenOffice is for. The backplanes in our ultrasound systems are usually north of 4000 pins and I have never seen a case where there was not a schematic for that. >> In the end it's important that a decent power pin handling is >> inside the >> program itself, > Why? > Because IMHO it's basic schematic capture functionality, used all the time. >>> Yes, and I do it all the time. But I use the toolkit's flexibility >>> rather than fighting against it. >>> >> Ok, I don't want to diss the "Linux way" of doing things here, just >> want >> let you guys know how most circuit design engineers out there work. > > Most? You mean *you*. The landscape here is vast, and we both work on > small, specialized subsets of of the big picture. > Not really small. I work in medical, aeronautics, automotive, oil/gas, alternative energies etc. Kind of comes with being self-employed. >> Can't say much about digital ASIC/FPGA designing > > But those are relevant. My biggest use of gEDA is mixed-signal ASIC > design. > Ok, if gEDA is geared towards ASIC/FPGA that's different. Then it sure won't be my kind of tool, just like BAE isn't (had tried it out lately). >> but I've got over 20 >> years of analog and fast digital under the belt. > > 40 years here. > Wow. With CAD? My first CAD exposure was Racal-Redac on a VAX but being young I could only get after-midnight time slots so I resorted to vellum and ink pens. >> Most of that as a >> consultant so I get to see how it's done at clients. > > Your clients are not my clients. > >> They all work the >> same way I do, in the graphical domain all the way up to the end when >> the netlist for the layouter is generated. > > That approach doesn't scale efficiently to big projects. Graphics are > superb for expressing circuit topology at moderate scales. But nobody > will ever comprehend how a Pentium works from schematics. > True. That would be ASIC type work. > The Veriog-AMS fans think they can eliminate schematics completely, > design analog in code, and have the computer synthesize the netlist > from that. That's also a nutty position, but they have a good reason: > code scales better than graphics. So, if you want to do really big > mixed-signal systems efficiently, you're going to need to do the > higher levels with code. The nuttiness comes from thinking one kind > of tool should work on all scales. > > So, a correlated double sampler circuit is best expressed as a > schematic, but the higher levels of a system containing 96 such > circuits along with a bunch of other stuff is not. At some point, > your eyes can't take it all in, so you might as well start making lists. > That's where the hierarchy
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 13, 2009, at 1:01 PM, Larry Doolittle wrote: > John - > > On Tue, Jan 13, 2009 at 12:54:21PM -0700, John Doty wrote: >> It seems you want gEDA to cater to your unwillingness to master new >> skills, learn better ways to do things. But gEDA's power is that it >> frees you to use the better way, not constraining you to inefficient >> ways of doing things. > > John, we've heard this all before. My ideas about an ideal > work flow even parallel yours completely! > > But gEDA's flexibility should _include_ the ability to deal > with people who don't think like us. But it does! You want to put everything in schematics, you can do that. > So please stop telling > people how to do their work. Do make sure gEDA maintains > its ability to use "the better way", and don't discourage > others from using it in "inefficient ways", and even improving > its ability to work so inefficiently (?). As long as it doesn't *enforce* inefficiency, that's great. But it seems to me that Joerg wants precisely that. The "handle power pins the way I want automatically" thing is a complex can of worms, as Peter has pointed out. If implemented, it *will* get in the way of other flows, trust me. > > The expert modes will then be on their desk, ready for them > when _they_ are ready to adapt. "A program should do one thing well." One of the reasons Kernighan said that is that adding features to a program beyond the "one thing" tends strongly to take away flexibility from the user, generally in ways that those promoting the features are blind to. An example in gEDA is the change in attribute promotion defaults that happened a while back. This was apparently intended to make the attribute system easier to understand (I'm skeptical), but the collateral damage to me was that schematics I drew before I understood this change are encrusted with attributes that are a barrier to reuse. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA on windows
On Jan 13, 2009, at 10:51 AM, Joerg wrote: >> >> Sometimes I make up my mind on footprints later. Anything but a >> single >> place to change this information is an invitation to err. Yes, indeed! >> > > That is why I am forcing myself never to switch a package in hindsight > (which would be possible in Eagle). When I find I need to change a > footprint, for example because the chosen one turns out to be a > purchasing nightmare, I delete all those parts, check in the library > whether there is another more available one and that its attributes > are > kosher, and then place it everywhere. Saves a lot of grief when the > netlist is generated. This common problem is one good reason to keep a directory of custom symbols (which may start out as copies of library symbols) for each project in gEDA. So, in a flow that uses a project symbol directory, select an instance in gschem, "Hs", edit the necessary attributes, "fs", and you're done. All instances inherit the change unless you've overridden the symbol attributes with promoted/attached attributes. Of course, you have to suppress the default "promote everything imaginable" with your gafrc before you draw, but again, that's the genius of gEDA: you can do that easily. > > -- > Regards, Joerg > > http://www.analogconsultants.com/ > > "gmail" domain blocked because of excessive spam. > Use another domain or send PM. > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John - On Tue, Jan 13, 2009 at 12:54:21PM -0700, John Doty wrote: > It seems you want gEDA to cater to your unwillingness to master new > skills, learn better ways to do things. But gEDA's power is that it > frees you to use the better way, not constraining you to inefficient > ways of doing things. John, we've heard this all before. My ideas about an ideal work flow even parallel yours completely! But gEDA's flexibility should _include_ the ability to deal with people who don't think like us. So please stop telling people how to do their work. Do make sure gEDA maintains its ability to use "the better way", and don't discourage others from using it in "inefficient ways", and even improving its ability to work so inefficiently (?). The expert modes will then be on their desk, ready for them when _they_ are ready to adapt. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 12, 2009, at 4:05 PM, Joerg wrote: > John Doty wrote: >>> >>> Take a device with multiple parts in there such as the 74HC14 and >>> handle >>> it like Eagle and Orcad do: None of them has power symbols. Then if >>> you >>> must connect it to some special power net you can "invoke" the power >>> symbols along with correct pin numbers on only the first >>> instantation. >>> So U1A then has power symbols but U1B, U1C and so forth don't. The >>> power >>> pins absolutely must show up in the schematic where you want them >>> and >>> not show up at the instantation where you don't want them. >> >> Sounds miserably complex and inflexible. While with gEDA, you break >> the physical device up however you choose, into as many symbols as >> you want, and there's nothing magical about power pins. >> > > It isn't complex and inflexible. It's how scores of engineers work ;-) But others of us *don't* work that way. It doesn't scale well to complex heterogeneous modules. > > >>> If they only >>> show up in the netlist that doesn't work because the schematic >>> will be >>> hard to understand. >> >> The pinlists for power and connectors show up in the documentation. I >> think that's *easier* to understand than graphics. >> > > Sorry, but I must disagree here. The schematic is generally the only > document accepted to understand a circuit. In your world, maybe. In mine, schematics are only a modest part of the documentation. > In design reviews, The schematics are only part of the story. In a NASA design review, the majority of the reviewers won't even look at them. > for the > TUEV inspector, and so on. They do not want to have to thumb through > reams of paper to find which net something invisible is connected to. A schematic of a 2000 pin backplane is pretty useless, while the same data in a human-friendly tabular form makes it really easy to find where to put the scope probe. > >>> > In the end it's important that a decent power pin handling is > inside the > program itself, Why? >>> Because IMHO it's basic schematic capture functionality, used all >>> the >>> time. >> >> Yes, and I do it all the time. But I use the toolkit's flexibility >> rather than fighting against it. >> > > Ok, I don't want to diss the "Linux way" of doing things here, just > want > let you guys know how most circuit design engineers out there work. Most? You mean *you*. The landscape here is vast, and we both work on small, specialized subsets of of the big picture. > Can't say much about digital ASIC/FPGA designing But those are relevant. My biggest use of gEDA is mixed-signal ASIC design. > but I've got over 20 > years of analog and fast digital under the belt. 40 years here. > Most of that as a > consultant so I get to see how it's done at clients. Your clients are not my clients. > They all work the > same way I do, in the graphical domain all the way up to the end when > the netlist for the layouter is generated. That approach doesn't scale efficiently to big projects. Graphics are superb for expressing circuit topology at moderate scales. But nobody will ever comprehend how a Pentium works from schematics. The Veriog-AMS fans think they can eliminate schematics completely, design analog in code, and have the computer synthesize the netlist from that. That's also a nutty position, but they have a good reason: code scales better than graphics. So, if you want to do really big mixed-signal systems efficiently, you're going to need to do the higher levels with code. The nuttiness comes from thinking one kind of tool should work on all scales. So, a correlated double sampler circuit is best expressed as a schematic, but the higher levels of a system containing 96 such circuits along with a bunch of other stuff is not. At some point, your eyes can't take it all in, so you might as well start making lists. > After that it's mostly off to > the next project. > > This may also be the reason why the EDA world is so OrCad-centric. I don't think anyone I work with uses OrCAD. The landscape here is much wider than you know. > Similar reasons why some fine open source programs such as > OpenOffice do > not make it into mainstream. Saying VBA is "for sissies" and thus > unimportant defies reality. Yesterday we had a family over for dinner > and the husband runs a major engineering firm. He hates Office 2007 > but > when I suggested OO he said it can't be done because none of the VBA > stuff would run anymore. > > >>> It's not something that is rarely used and where a patch file may >>> work. >>> >>> > not something that must be handled by letting a command > line routine run over some files. Monolithic programs are inflexible. gEDA's strength is radical flexibility. >>> Well, true, but having to remember which patch files must be run to >>> massage a certain schematic and which don't is a serious source of >>> error >>> for the
Re: gEDA-user: Bug report for renaming slots [Was: Re: gEDA on windows]
Peter Clifton wrote: >> Most CAD systems use such routines and they can be called from within >> the application. Eagle calls them user language programs (ULP). > > It just hooks in with a couple of lines in a config file (currently the > "gEDA" way), then it executes the script action every time I copy a > component. gEDA just doesn't have a huge API at the moment. > That would be perfectly fine since it auto-executes upon each copy. The only thing people might have to get used to is to copy and not place a part of same type as new. All CAD systems have some peculiarities to them (for example in Eagle "cut" really means "copy"). >>> I'd like to put the discussion in context by seeing how a real schematic >>> looks using the styles we discussed, rather than just my mental pictures >>> so far, which just cover a symbol and its visible pins. >>> >> A bit problematic because most of my stuff is client designs. But I'll >> find something suitable. On the web I found your pcjc2 email address at >> Cambridge, let me know in case that isn't correct anymore. I am reading >> this group through gmane which hides people's web identities. > > That is correct. I'm pcjc2, and my email address is @cam.ac.uk > Thanks. You've got mail :-) -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA on windows
Kai-Martin Knaak wrote: > On Tue, 13 Jan 2009 08:02:50 -0800, Joerg wrote: > >>> I don't know what might happen in the case where two slots had >>> conflicting attributes. Perhaps this is something for a design rule >>> checker to highlight. >>> >>> >> The risk of running afoul in that direction is pretty low. The reason is >> that most designers I know do it the same way I do > > Sometimes I make up my mind on footprints later. Anything but a single > place to change this information is an invitation to err. > That is why I am forcing myself never to switch a package in hindsight (which would be possible in Eagle). When I find I need to change a footprint, for example because the chosen one turns out to be a purchasing nightmare, I delete all those parts, check in the library whether there is another more available one and that its attributes are kosher, and then place it everywhere. Saves a lot of grief when the netlist is generated. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John Griessen wrote: > Joerg wrote: > >> Thanks, Stuart, that's all I really wanted to do, bringing some feedback >> based on what I see in industry. As a consultant I get around a lot, >> seeing all kinds of CAD systems and habits of people. Some of this is >> very different from what many in this group (and also in the EDA >> industry) think. For example, only three of my clients do their own >> layouts, all the others and myself farm that out. So to design engineers >> (in industry/consulting) the layout tool isn't too important, schematic >> capture is what they use all the time. And they abhor dual-boot systems. > > Sure, that's the typical design engineer employee's attitude -- faster > faster, don't bug me with the details > that aren't critical. Doesn't help niche market engineers or moonlight > engineers as much. I work a lot with those as well. Sometimes there are half a dozen freelancers and only very few employees collaborating on a project. IME those freelancers (I am one of them ...) work in a similar way. Time is money :-) > The openness of non-locked data plus ability to create custom work flows > is why we work on free code. We want it to be super easy and intuitive, > and run on any platform, it just takes time and effort. We probably want > about the same things you do...but averages are not all... EE designers are > very individual and often make their own styles of work different from others > at their > same company. > Yes, there will be other styles. That's why many of us should give feedback. I work mostly in med electronics and there we place a huge emphasis on the feedback from surgeons, cardiologists and so on. They are only interested in the end product and they tell us exactly how it should be. This is also why we often stand alongside them in the cardio lab, getting a back pain from the lead vests. Just to understand why they want the product a certain way. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA on windows
On Tue, 13 Jan 2009 08:02:50 -0800, Joerg wrote: >> I don't know what might happen in the case where two slots had >> conflicting attributes. Perhaps this is something for a design rule >> checker to highlight. >> >> > The risk of running afoul in that direction is pretty low. The reason is > that most designers I know do it the same way I do Sometimes I make up my mind on footprints later. Anything but a single place to change this information is an invitation to err. ---<(kaimartin)>--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Helping the gEDA Project... was: Re: Power (and other non-graphical) pins
Stuart Brorson wrote: [...] >> Here is another suggestion: Can you guys post a typical project that >> some kid has done? Or at least a "mock project" if it's a first? That >> way people like me can tell kids "Hey, take a look at this link and see >> if you'd be interested and capable to do something like that". > > Yes, our project list for 2009 will be posted shortly. The lists for > 2007 and 2008 are here: > > http://geda.seul.org/wiki/gsoc2007_projects > http://geda.seul.org/wiki/gsoc2008_projects > Great. In addition I suggest to ask one kid or maybe a few who already participated to tell their story in a short write-up. Takes the barriers down a notch. It could start out like "When I took my assignment, at first I almost wetted my pants. But then ...", followed by the success story. This is one method churches use to encourage people for mission work. Most destinations are a bit hostile so there is some fear factor to overcome. Same with projects like this that look daunting to younger people. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Helping the gEDA Project... was: Re: Power (and other non-graphical) pins
Hi -- >> Paying developers to write code is a time-honored way of making features >> get added to any software project. Don't hesitate to use it! ;-) > > Yes, I've read that. It is the other reason why I think feedback "from > the trenches" is important. The really big donation pots are with > organizations. True enough. We are trying to reach out to organizations, but it's a hard sell, as you might imagine. Perhaps you know some people who know some people who might be interested, if you know what I mean? And -- hey! -- you're a businessman. That's an orgnization, right? A good way to (literally) buy some goodwill with developers is to donate to the Linux Fund's PCB project. OK, I've done enough shilling for our Linux Fund project. But I hope you have gotten the message: "Feedback from the trenches" is useful, but you'll get real leverage for your favorite project by contributing in more powerful ways (i.e. contribute code, business networking, or financial support). And yes, I read your point that EEs will be turned off by this or that small buglet, and so won't be interested in contributing. But if the whole project was already finished, then who would need to contribute? It's a chicken and egg problem. The right approach is to get ahead of the development and help lead it, rather than say "I can't contribute until it's perfect". >> Maybe you know somebody who could implement your desired feature over >> the summer? Wouldn't that be a win-win if they got involved with the >> gEDA Project? > > We don't have kids, wanted to but couldn't :-( Sorry to hear that. :-( > But I'll look around if there are smart student who have a knack for > programming. Only problem is that we live in a fairly rural area so > there aren't too many. Then again, Intel is only 10 miles from here. Great idea! It's quite likely that the smart engineers at Intel have kids who are computer saavy, and would love to geek out on a project like gEDA. If you have contacts at Intel, please *do* point them to us. You'll be doing us a great help if you assist us in getting the word out about gEDA and the Google Summer of Code. And if you have other contacts, please contact them too. Think about ham radio clubs, computer clubs, other technology companies, etc. Your contact list is invaluable for this. > Here is another suggestion: Can you guys post a typical project that > some kid has done? Or at least a "mock project" if it's a first? That > way people like me can tell kids "Hey, take a look at this link and see > if you'd be interested and capable to do something like that". Yes, our project list for 2009 will be posted shortly. The lists for 2007 and 2008 are here: http://geda.seul.org/wiki/gsoc2007_projects http://geda.seul.org/wiki/gsoc2008_projects Cheers, Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bug report for renaming slots [Was: Re: gEDA on windows]
> Most CAD systems use such routines and they can be called from within > the application. Eagle calls them user language programs (ULP). It just hooks in with a couple of lines in a config file (currently the "gEDA" way), then it executes the script action every time I copy a component. gEDA just doesn't have a huge API at the moment. > > I'd like to put the discussion in context by seeing how a real schematic > > looks using the styles we discussed, rather than just my mental pictures > > so far, which just cover a symbol and its visible pins. > > > > A bit problematic because most of my stuff is client designs. But I'll > find something suitable. On the web I found your pcjc2 email address at > Cambridge, let me know in case that isn't correct anymore. I am reading > this group through gmane which hides people's web identities. That is correct. I'm pcjc2, and my email address is @cam.ac.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA on windows
Peter Clifton wrote: [...] > I don't know what might happen in the case where two slots had > conflicting attributes. Perhaps this is something for a design rule > checker to highlight. > The risk of running afoul in that direction is pretty low. The reason is that most designers I know do it the same way I do: Either they hit Add -> Component -> place one instantation after the other until they think they've got enough parts of same type to design this section. Or they find out "Oops, I need three more" and then copy and paste from what they've already got on the page. So their chance of messing up attributes is quite low. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bug report for renaming slots [Was: Re: gEDA on windows]
Peter Clifton wrote: > On Mon, 2009-01-12 at 18:53 -0800, Joerg wrote: >> Peter Clifton wrote: > >>> Actually, your idea has got me thinking more about how we handle >>> attributes on slotted parts, and the possibility that they could in some >>> way be treated as an aggregate component for the purposes of attributes >>> other than "slot=". >>> >> Not 100% sure if I understand correctly but yes, treating all slots as >> one component would be feasible. Even if you don't use all you must >> usually place all slots anyhow and, for example, connect inputs to GND. >> Exception being transistor arrays but even they should also be grounded >> and be on the schematic so folks can see what's available for cut/jumper >> style rework purposes. > > Sorry for typing before thinking that through fully. Treating all slots > as one component (for adding attributes) isn't actually possible with > gEDA's architecture. Attributes can only be added to symbols. > > I can imagine the GUI glossing over that fact, and perhaps offering to > help keep attributes in sync when renaming a single slot, it would be > difficult (perhaps impossible) to cater for the case where you have some > slots on one schematic page, and others elsewhere. > Most of the time engineers could live with the restriction that all slots must be on the same page. Not perfect, but should be quite acceptable. >> That would be a serious one. I can't recall a single company I dealt >> with not using A, B, and so on (upper case). Most CAD programs >> auto-assign those when you place until you run out of slots. So if you >> place eight slots of a six-slot 74HC14 it bumps the refdes number for >> the last two you place. They don't all do it perfectly. OrCad usually >> does but I've had Eagle "forget" when I began placing some more slots >> later. gschem just places all as first slots with U? right now. > > Tricky to figure out how to do this flexibly. gEDA's flexibility means > special casing behaviours like this is hard (and often undesired). Some > kind of script or plugin hook might be a possible way to do this, but > again.. I'm just thinking "aloud". > > (I'm not suggesting users would have to write these scripts, more that > they shouldn't form part of gschem's hard-coded behaviour.) > > As an example I wrote for someone (and I ended up using it myself), I > have a script hook here which renames any component I copy back to > "U?" (removes the numbering), so that I don't end up accidentally naming > two components the same due to a copy-paste in my schematics. > Most CAD systems use such routines and they can be called from within the application. Eagle calls them user language programs (ULP). > > Joerg: I think I have some understanding now of the kind of visual > appearance of schematics you're thinking of, but I'm curious to see (if > you have any examples you could share - perhaps by private email), just > what the kind of schematic you're talking about looks like. (Either > slotted logic gates, or slotted op-amps). > > I'd like to put the discussion in context by seeing how a real schematic > looks using the styles we discussed, rather than just my mental pictures > so far, which just cover a symbol and its visible pins. > A bit problematic because most of my stuff is client designs. But I'll find something suitable. On the web I found your pcjc2 email address at Cambridge, let me know in case that isn't correct anymore. I am reading this group through gmane which hides people's web identities. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
> For those who can't / don't want to dual boot, I've been working from > time to time (based on the great efforts of Cesar Strauss), to build > test a Windows port of the gEDA tools. Since there are still more issues > to resolve there (compared to the Unix version), this has not yet been > released. > Another alternative to dual boot- I run gEDA at work on my Windows XP box using a virtualized Ubuntu installation (using VirtualBox); does the job nicely Cheers Gareth ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Tue, 2009-01-13 at 06:56 -0800, Joerg wrote: > Stuart Brorson wrote: > > Hi Joerg -- > > > > It's fun to see that you're back on the geda e-mail lists! Welcome > > back! We thought you had defected to Kicad. :-( > > > > To be honest I don't think I'll switch to gEDA. The refdes and slot > mix-ups are certainly surmountable but I found over the last couple > months that Linux is not my cup of tea. I did leave it all on the PC > though, going back to it on occasion and I think the idea behind all > this is great. That's fair enough. For those who can't / don't want to dual boot, I've been working from time to time (based on the great efforts of Cesar Strauss), to build test a Windows port of the gEDA tools. Since there are still more issues to resolve there (compared to the Unix version), this has not yet been released. At some point in the future, when its polished enough, and we've resolved the potential support / community issues, it may be made available more formally. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Joerg wrote: > Thanks, Stuart, that's all I really wanted to do, bringing some feedback > based on what I see in industry. As a consultant I get around a lot, > seeing all kinds of CAD systems and habits of people. Some of this is > very different from what many in this group (and also in the EDA > industry) think. For example, only three of my clients do their own > layouts, all the others and myself farm that out. So to design engineers > (in industry/consulting) the layout tool isn't too important, schematic > capture is what they use all the time. And they abhor dual-boot systems. Sure, that's the typical design engineer employee's attitude -- faster faster, don't bug me with the details that aren't critical. Doesn't help niche market engineers or moonlight engineers as much. The openness of non-locked data plus ability to create custom work flows is why we work on free code. We want it to be super easy and intuitive, and run on any platform, it just takes time and effort. We probably want about the same things you do...but averages are not all... EE designers are very individual and often make their own styles of work different from others at their same company. John G -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bug report for renaming slots [Was: Re: gEDA on windows]
On Tue, 2009-01-13 at 04:14 +, Kai-Martin Knaak wrote: > On Tue, 13 Jan 2009 03:41:24 +, Peter Clifton wrote: > > > As an example I wrote for someone (and I ended up using it myself), I > > have a script hook here which renames any component I copy back to "U?" > > (removes the numbering), so that I don't end up accidentally naming two > > components the same due to a copy-paste in my schematics. > > I have wished geschem behaved like. Any chance, this script is going to > hit the main distribution of geda? Perhaps when we have a more formal system of enabling various plugins. Fow now, it is attached. You need to hook it in with: (load-from-path "/path/to/unnumber-refdes.scm") (add-hook! copy-component-hook unnumber-refdes) in your gschemrc file. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ;; Copyright (C) 2008 Peter Clifton ;; ;; This program is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2 of the License, or ;; (at your option) any later version. ;; ;; This program is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; ;; You should have received a copy of the GNU General Public License ;; along with this program; if not, write to the Free Software ;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA (use-modules (srfi srfi-13) (srfi srfi-14)) (define (unnumber-refdes attribs) ;; Function to strip digit suffixes (define (strip-digit-suffix string) (string-trim-right string char-set:digit) ) (define (unnumbered-refdes oldrefdes) (if (string-suffix? "?" oldrefdes) oldrefdes (string-append (strip-digit-suffix oldrefdes) "?") ) ) (for-each (lambda (attrib) (let* ((name-value (get-attribute-name-value attrib)) (name (car name-value)) (value (cdr name-value))) (if (string=? name "refdes") (set-attribute-value! attrib (unnumbered-refdes value))) ) ) attribs ) ) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Stuart Brorson wrote: > Hi Joerg -- > > It's fun to see that you're back on the geda e-mail lists! Welcome > back! We thought you had defected to Kicad. :-( > To be honest I don't think I'll switch to gEDA. The refdes and slot mix-ups are certainly surmountable but I found over the last couple months that Linux is not my cup of tea. I did leave it all on the PC though, going back to it on occasion and I think the idea behind all this is great. >> Ok, I don't want to diss the "Linux way" of doing things here, just want >> let you guys know how most circuit design engineers out there work. > > *snip!* > > I think that the perspective you bring -- with your long experience -- > is invaluable. Therefore, please don't be dissuaded from explaining > on geda-user how you think an EDA tool should work, since it's quite > educational. Your e-mails always generate a lot of traffic on the > lists; please don't be put off by the amount of debate you produce > since it's all healthy. > Thanks, Stuart, that's all I really wanted to do, bringing some feedback based on what I see in industry. As a consultant I get around a lot, seeing all kinds of CAD systems and habits of people. Some of this is very different from what many in this group (and also in the EDA industry) think. For example, only three of my clients do their own layouts, all the others and myself farm that out. So to design engineers (in industry/consulting) the layout tool isn't too important, schematic capture is what they use all the time. And they abhor dual-boot systems. > I don't know if you have been following the gEDA Project's recent > history, but we have some interesting developments underway. > > First, gEDA has partnered with the Linux Fund to push developemnt of > PCB further along. People and organizations can donate money to the > Linux Fund which will be used to pay our resident PCB guru DJ Delorie > to add significant improvements to PCB, making it easier to use for > novice and advanced layout engineers. He'll also add important > features for professional level use. > > Before this work can happen, enough donations must accumulate at the > Linux Fund that work can begin on the project. If you really are > interested in helping gEDA along (and also adding to your own > credibility amongst the developers), you might consider donating some > money to the Linux Fund's PCB project: > > http://www.linuxfund.org/projects/pcb/ > > Paying developers to write code is a time-honored way of making features > get added to any software project. Don't hesitate to use it! ;-) > Yes, I've read that. It is the other reason why I think feedback "from the trenches" is important. The really big donation pots are with organizations. But their engineers will waive off when they get stuck early on in a "kicking the tires" pilot design, for example because the multi-slot stuff doesn't work well. They'll also want at least a chance to give all this a "windowsy" feel. Meaning no "you do not have permission to write to this file" and such. I know this will go against the grain of many but I can only tell you guys how it is. Since this is earmarked for PCB maybe you could suggest some kind of tithing scheme. IOW where layouters or engineers who use PCB for revenue and feeding their family donate a percent or so of their fees/income. Like our church you will probably not just have to meet these set budget items but need donations on an ongoing basis. Not just for coding but at some point the world needs to know and that only works through ads or bought articles. Case in point: In December I suggested gEDA to an engineer who uses Kubuntu at home. He did not know gschema existed ... > Second, gEDA will participate in the Google Summer of Code project > again in 2009. In this project, Google will pay university students > to work on one or another of the gEDA tools, usually implementing new > features. If you know of any smart university students (maybe you > have kids?) who would like to get paid to hack gEDA over the summer, > feel free to point them in our direction. We are currently beginning > the search for quality participants. > > Maybe you know somebody who could implement your desired feature over > the summer? Wouldn't that be a win-win if they got involved with the > gEDA Project? > We don't have kids, wanted to but couldn't :-( But I'll look around if there are smart student who have a knack for programming. Only problem is that we live in a fairly rural area so there aren't too many. Then again, Intel is only 10 miles from here. Here is another suggestion: Can you guys post a typical project that some kid has done? Or at least a "mock project" if it's a first? That way people like me can tell kids "Hey, take a look at this link and see if you'd be interested and capable to do something like that". Otherwise kids easily become scared, thinking they'd need to be rocket scientists to do
