Re: gEDA-user: sd-card connector sym and fp needed
Hallo DJ, > > This project has microsd: > > http://www.delorie.com/electronics/sdram/ Thank you! Micro SD might work, I'll just have to find this connector. Digikey has pretty expensive shipping here. Best regards Michael ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LVS and other pcb related questions
Anthony Shanks wrote: > Hi all, > > 3. Right now, I am running gnetlist -g PCB on my schematics to > generate the pcb netlist file. The problem is I have multiple > schematics that I am generating a netlist from and I am manually > appending the refdes to indicate which schematic the netlist comes > from so all my refdes will be unqiue. (for example, instead of U1, it > will be U1.A1). Has anybody developed some kind of script or flow to > solve this problem? I would like to get away from doing this manually > eventually. What you can do is create a top schematic with symbols created for the A1 A2 etc. schematics and attach attribs for doing hierarchic names to flat netlist. On each symbol for a sub schematic put attrib source=A1.sch or source=A2.sch as needed. then your netlist output will have names like: SENVDDB S6/R4-1 S6/C4-1 S5/R4-1 S5/C4-1 S4/R4-1 S4/C4-1 S3/R4-1 S3/C4-1 S2/R4-1 S2/C4-1 S1/R4-1 S1/C4-1 Q5-3 U4-5 Q2-3 SENVDDA S6/R2-1 S6/C2-2 S5/R2-1 S5/C2-2 S4/R2-1 S4/C2-2 S3/R2-1 S3/C2-2 S2/R2-1 S2/C2-2 S1/R2-1 S1/C2-2 Q4-3 U4-3 Q1-3 SENSIGS1R2 S1/C3-2 S1/R3-1 U2-13 where a wire named SENVDDB connects to 6 places with the same component name, but prefixed with the sub schematic name. For making repeated layout zones, I made a script version from one of John Luciani's. See http://www.gedasymbols.org/user/john_griessen/tools/pcb-hier-cells John -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LVS and other pcb related questions
DJ Delorie wrote: > Ah. In PCB, what we do is have (1) the netlist, which is from the > schematic and knows "what should be", and (2) the rats nest and DRC, > which come from the PCB and know "what is". The "o" key compares the > two. DRC will find multiple placements, one of which is not connected to nets and flag those, so netlist to ratlist comparison is good for LVS purpose if and only if your footprints are correctly associated with your symbols. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LVS and other pcb related questions
> I think he means LVS as in Logic vs Schematic - a form of layout > checking commonly found in ASIC design, not LVDS as in Low-Voltage > Differential Signaling. Ah. In PCB, what we do is have (1) the netlist, which is from the schematic and knows "what should be", and (2) the rats nest and DRC, which come from the PCB and know "what is". The "o" key compares the two. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LVS and other pcb related questions
On 12/01/2009 11:57 AM, DJ Delorie wrote: > >> However, from what I can tell, there still isn't any concept of lvs >> in pcb, or am I missing that? > > PCB doesn't know about LVS, stripline, differential pairs, or any of > that. I think he means LVS as in Logic vs Schematic - a form of layout checking commonly found in ASIC design, not LVDS as in Low-Voltage Differential Signaling. In the ASIC world, LVS is a fairly complex problem that usually involves re-creating the netlist from the layout, then comparing that to the original netlist. This requires fairly detailed understanding of device structures to infer higher-level functionality. For PCB it may be more trivial, since all that need be re-created is the netlist itself, not the devices. Nonetheless it's not simple. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LVS and other pcb related questions
> However, from what I can tell, there still isn't any concept of lvs > in pcb, or am I missing that? PCB doesn't know about LVS, stripline, differential pairs, or any of that. > If not, is there at least a way to make sure that your netlist and > pcb have exactly the same number of components with the proper > refdes indicated in your netlist (as in, there are no missing > components, duplicate components, or misnamed components)? The "o" (optimize rats) does a bunch of these checks. > 2. I looked at the way pcb instantiates a component into the drawing No, there's no way to reference an external footprint like that. I'm working on a way to automatically replace footprints if you select a different footprint, but it doesn't autodetect (nor should it :) when a footprint file is edited (same file name). > 3. Right now, I am running gnetlist -g PCB on my schematics to > generate the pcb netlist file. The problem is I have multiple > schematics that I am generating a netlist from and I am manually > appending the refdes to indicate which schematic the netlist comes > from so all my refdes will be unqiue. (for example, instead of U1, it > will be U1.A1). Has anybody developed some kind of script or flow to > solve this problem? I would like to get away from doing this manually > eventually. Use gsch2pcb and a "project file" (I name mine .prj) like this: m4-pcbdir /envy/dj/geda/share/pcb/m4 elements-dir /envy/dj/geda/gedasymbols/www/user/dj_delorie/footprints schematics power.sch furnace.sch gumstix.sch zone1.sch zone2.sch zone3.sch zone4.sch driver1.sch driver2.sch driver3.sch driver4.sch output-name board Then just "gsch2pcb board.prj" > 4. Why doesn't pcb play nice with pins that aren't numerical? For > example, if I have a netlist that references U1-vcc, and a pin named > as U1-vcc, pcb will complain and won't highlight the pin/net. What > property of the symbol in gschem is gnetlist using to determine what > the pin number is? The rule is: don't end a pin/refdes with a lower case letter. Those are historically reserved for slot IDs. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: LVS and other pcb related questions
Hi all, I have some questions about pcb. 1. I have the concept down of how pcb interacts with the components you place on the board and the netlist you load and I have them working properly, as I can properly highlight nets and components with the netlist browser. However, from what I can tell, there still isn't any concept of lvs in pcb, or am I missing that? Of course you can manually highlight and check every net as a manual type of lvs, but is there no automatic tool for this? If not, is there at least a way to make sure that your netlist and pcb have exactly the same number of components with the proper refdes indicated in your netlist (as in, there are no missing components, duplicate components, or misnamed components)? 2. I looked at the way pcb instantiates a component into the drawing area and it looks like instead of just referencing the footprint (as gschem does with symbols), it actually just copies the contents of the footprint file to the pcb, so if you edit the footprint it doesn't get updated. I can see why some might like this, as editing a footprint doesn't break the layout, but is there an option to just reference the footprint instead for people who want this? For example, if I have 100 footprints of 0805's and I want to change the mask clearance for all of these footprints it would seem as if I would have to do this one by one. 3. Right now, I am running gnetlist -g PCB on my schematics to generate the pcb netlist file. The problem is I have multiple schematics that I am generating a netlist from and I am manually appending the refdes to indicate which schematic the netlist comes from so all my refdes will be unqiue. (for example, instead of U1, it will be U1.A1). Has anybody developed some kind of script or flow to solve this problem? I would like to get away from doing this manually eventually. 4. Why doesn't pcb play nice with pins that aren't numerical? For example, if I have a netlist that references U1-vcc, and a pin named as U1-vcc, pcb will complain and won't highlight the pin/net. What property of the symbol in gschem is gnetlist using to determine what the pin number is? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Calculating component area verses available board area?
Can't help on the direct question, but... On Tue, Dec 01, 2009 at 10:06:56AM -0500, Bob Paddock wrote: > In PCB is there a way to get a sum of all of the component > footprint/silk areas, so that the sum can be compared to the available > board surface area? > > Board surface needs to account for any keep-outs where components > can not be place. May or may not want to count both sides of the board. > > Boss is telling me to put 230 parts on a board that I think > I can put 175. That is not even accounting for space for actual > traces and vias. I'm looking for object numbers to inflict on him. Tell him that if he thinks he can do better, then he's welcome to demonstrate how to do it... :-) > This happens often enough that I want it to be an automated process. I would worry that the utilisation (as we call it in the digital ASIC industry) would be too blunt a measure, and that you'd potentially be setting yourself up for future problems. "You did the last board at 80% utilisation, so why can't you do this one which is only 70%?" -- David SmithWork Email: dave.sm...@st.com STMicroelectronics Home Email: david.sm...@ds-electronics.co.uk Bristol, England GPG Key: 0xF13192F2 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Calculating component area verses available board area?
> In PCB is there a way to get a sum of all of the component > footprint/silk areas, so that the sum can be compared to the > available board surface area? Not that I know of. Bounding boxes might be better to count, though. They're simple pre-calculated rectangles. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Calculating component area verses available board area?
In PCB is there a way to get a sum of all of the component footprint/silk areas, so that the sum can be compared to the available board surface area? Board surface needs to account for any keep-outs where components can not be place. May or may not want to count both sides of the board. Boss is telling me to put 230 parts on a board that I think I can put 175. That is not even accounting for space for actual traces and vias. I'm looking for object numbers to inflict on him. This happens often enough that I want it to be an automated process. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT diode reverse saturation current
Hi Gene, The usually quoted formula is: IS = A*exp(-Eg/(k*T) Where IS = saturation current, A is nearly constant independent of temperature and dependent on diffusion coefficients of electrons and holes. k is the Boltzmann constant. ν is a constant; 1 for germanium and 2 for silicon; and T is the absolute temperature (deg Kelvin). Eg is the band gap of the semiconductor. The band gap of silicon is 1.12eV and that of germanium 0.66eV. According to this formula, IS doubles for approx 5degC rise in temperature for silicon and 8degC for germanium. However, the reality is somewhat different and a better approximation(i) is this: IS = A*T^m*exp(-Eg/(n*k*T)) Where IS = saturation current, A is a constant independent of temperature and dependent on diffusion coefficients of electrons and holes. k is the Boltzmann constant. T is the absolute temperature (deg Kelvin). m is a constant; 1.5 for silicon and 2 for germanium. n is a constant; 1 for germanium and 2 for silicon Eg is the band gap of the semiconductor. The band gap of silicon is 1.12eV and that of germanium 0.66eV. I think the formula holds for GaAs and other semiconductor junction diodes but the various constant will be different. I'm not sure how IS varies for schottky (metal-semiconductor junction) diodes. This also assumes that the reverse bias is not high enough to cause any zener or avalanche breakdown effects that contribute to the reverse leakage current. Cheers, Andy. www.signality.co.uk (i) Integrated Electronics. Millman and Halkias (International Student Edition) 1972 Lib Cong Cat Card # 79-172657 p752 sect 19.11 2009/12/1 gene glick : > I'm trying to find some info on the temperature variation of the reverse > saturation current of a diode. Anyone know about this? > > gene > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: OT diode reverse saturation current
I'm trying to find some info on the temperature variation of the reverse saturation current of a diode. Anyone know about this? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
