Re: gEDA-user: Net of Selected Common Pins Enroutes Shortest Path Through All Intervening Pins
Done. Thank you gentlemen. I understand queries such as mine are "clutter" in high quality list traffic, such as found here. Other such lists have mercilessly sent me to /dev/null in the past. I appreciate your kindness in responding. On Wed, Jan 6, 2010 at 12:15 AM, John Griessen <[1]j...@ecosensory.com> wrote: Stan Katz wrote: No matter >how I draw the nets in gschem, the final rats nest runs produced in >pcb is one trace, across all the pins on each side of the SOIC, as >long as any of them are in the star end-run to the header pin. In >other words, if I want to tie pins 1,3,5, of the transceiver, to pin >1 in the header, a rat route runs across pins 1,2,3,4,5, of the >transceiver, shorting all of them together, and then routes to header >pin 1. How can I separate these nets? Just add some copper running out from the pads a ways and then do "optimize rats" and you will see a ratnest more like you were expecting. Like DJ said, ratlines don't conduct. John -- Ecosensory Austin TX ___ geda-user mailing list [2]geda-u...@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:j...@ecosensory.com 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [ig...@igor2.repo.hu: Re: Net of Selected Common Pins Enroutes Shortest Path Through All Intervening Pins]
On Tue, Jan 05, 2010 at 10:08:15PM -0500, Stan Katz wrote: > >I use gEDA for small projects. One, and two sided boards only. It's >been fine up until now. I now have a transceiver chip with some pins, >a number of which I need to run to pin 1 on an IDE header. No matter >how I draw the nets in gschem, the final rats nest runs produced in >pcb is one trace, across all the pins on each side of the SOIC, as >long as any of them are in the star end-run to the header pin. In >other words, if I want to tie pins 1,3,5, of the transceiver, to pin >1 in the header, a rat route runs across pins 1,2,3,4,5, of the >transceiver, shorting all of them together, and then routes to header >pin 1. How can I separate these nets? Where do I do it? (gschem, >gsch2pcb, just gnetlist, or pcb) My only solution, so far, has been to >plant small terminals in each run in gschem, with a very small via >footprint. This forces separate routes to pin 1 on the header in pcb. It's only the graphical representation that may seem to be like that. Take it as rat lines are arcs connecting 1-3-5 above 2 and 4, but as you are looking at them from the top, they look like lines. When I have a similar situation I usually press 'f' over the rat or over the header pin, so the whole net is highlighted - this would make the header pin, the rat lines and pins 1-3-5 highlighted green while leaving 2 and 4 alone. Regards, Tibor Palinkas - End forwarded message - ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Net of Selected Common Pins Enroutes Shortest Path Through All Intervening Pins
Stan Katz wrote: No matter >how I draw the nets in gschem, the final rats nest runs produced in >pcb is one trace, across all the pins on each side of the SOIC, as >long as any of them are in the star end-run to the header pin. In >other words, if I want to tie pins 1,3,5, of the transceiver, to pin >1 in the header, a rat route runs across pins 1,2,3,4,5, of the >transceiver, shorting all of them together, and then routes to header >pin 1. How can I separate these nets? Just add some copper running out from the pads a ways and then do "optimize rats" and you will see a ratnest more like you were expecting. Like DJ said, ratlines don't conduct. John -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Net of Selected Common Pins Enroutes Shortest Path Through All Intervening Pins
Rats don't short copper they travel across; they only electrically connect their endpoints. It's up to you - the layout person - to put copper (not rats) in the right places. PCB has some settings to help with this, like auto-enforce DRC clearance which highlights pins in the same net when you start a trace, so you know what pins should and shouldn't be connected. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Net of Selected Common Pins Enroutes Shortest Path Through All Intervening Pins
I use gEDA for small projects. One, and two sided boards only. It's been fine up until now. I now have a transceiver chip with some pins, a number of which I need to run to pin 1 on an IDE header. No matter how I draw the nets in gschem, the final rats nest runs produced in pcb is one trace, across all the pins on each side of the SOIC, as long as any of them are in the star end-run to the header pin. In other words, if I want to tie pins 1,3,5, of the transceiver, to pin 1 in the header, a rat route runs across pins 1,2,3,4,5, of the transceiver, shorting all of them together, and then routes to header pin 1. How can I separate these nets? Where do I do it? (gschem, gsch2pcb, just gnetlist, or pcb) My only solution, so far, has been to plant small terminals in each run in gschem, with a very small via footprint. This forces separate routes to pin 1 on the header in pcb. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: teardrop compiling installation,
Hi Vincent,
As DJ already mentioned, keep the source trees on a correct level.
Clues to be found at :
http://github.com/bert/pcb-plugins/commit/3ef110ba3ec428c67111f19ece4de89d51
b5f418
Kind regards,
Bert Timmerman.
-Oorspronkelijk bericht-
Van: geda-user-boun...@moria.seul.org
[mailto:geda-user-boun...@moria.seul.org] Namens Vincent Onelli
Verzonden: donderdag 31 december 2009 17:44
Aan: geda-user@moria.seul.org
Onderwerp: gEDA-user: teardrop compiling installation,
Hello,
I download compressed file "bert-pcb-plogins-17755b2.tar.gz"
decompressed generate a directory "bert-pcb-plugins-17755b2". I cd to
bert-pcb-plugins-17755b2/src which is where I found teardrops.c file then
entered the suggested command gcc ... the follow is the result:
[vi...@laptop src]$ gcc -I$HOME/geda/pcb-cvs/src -I$HOME/geda/pcb-cvs
-02 -shared teardrops.c -o teardrops.so
gcc: unrecognized option '-02'
teardrops.c:13:20: error: global.h: No such file or directory
teardrops.c:14:18: error: data.h: No such file or directory
teardrops.c:15:17: error: hid.h: No such file or directory
teardrops.c:16:18: error: misc.h: No such file or directory
teardrops.c:17:20: error: create.h: No such file or directory
teardrops.c:18:19: error: rtree.h: No such file or directory
teardrops.c:19:18: error: undo.h: No such file or directory
teardrops.c:21: error: expected '=', ',', ';', 'asm' or '__attribute__'
before 'pin'
teardrops.c:24: error: expected '=', ',', ';', 'asm' or '__attribute__'
before 'silk'
teardrops.c:29: error: expected ';', ',' or ')' before '*' token
teardrops.c:151: error: expected ')' before '_pin'
teardrops.c: In function 'teardrops':
teardrops.c:175: error: 'silk' undeclared (first use in this function)
teardrops.c:175: error: (Each undeclared identifier is reported only once
teardrops.c:175: error: for each function it appears in.)
teardrops.c:175: error: 'PCB' undeclared (first use in this function)
teardrops.c:181: error: 'via' undeclared (first use in this function)
teardrops.c:183: error: 'END_LOOP' undeclared (first use in this
function)
teardrops.c:187: error: 'pin' undeclared (first use in this function)
teardrops.c:189: error: 'ENDALL_LOOP' undeclared (first use in this
function)
teardrops.c:191: error: 'gui' undeclared (first use in this function)
teardrops.c: At top level:
teardrops.c:199: error: expected '=', ',', ';', 'asm' or '__attribute__'
before 'teardrops_action_list'
teardrops.c: In function 'REGISTER_ACTIONS':
teardrops.c:208: error: expected '=', ',', ';', 'asm' or '__attribute__'
before '{' token
teardrops.c:210: error: expected '{' at end of input [vi...@laptop src]$
Obviously, I am doing some thing wrong. I am stuck, help.
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Re: gEDA-user: blue sky ideas - written down finally
On Tuesday 05 January 2010 18:31:49 DJ Delorie wrote: > > Can't wait to have that one implemented as it's the one point i > > tripped over with about every software i tried. > > Just to be clear - by writing down my ideas, I do not mean to imply > that I (or anyone else) will actually implement them. > Sure. But at least the idea is out there, and people can think about it. Who knows, maybe someone will make an attempt and try to improve on it. Or point out a different idea that'll get similar results. And i'd figure anything that gets implemented will inevitably need some thought. On top of that, some might consider donating a buck or two towards that feature. I myself can't spend much money, but i'd consider it anyways. Greetings, Florian signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Jan 5, 2010, at 9:31 AM, DJ Delorie wrote: > >> Can't wait to have that one implemented as it's the one point i >> tripped over with about every software i tried. > > Just to be clear - by writing down my ideas, I do not mean to imply > that I (or anyone else) will actually implement them. But without being written down, it is guaranteed not to be implemented. Now there is a reference document, people can agree (or not), work can be scoped, transition methodologies/plans designed. At some point, someone might even code a patch or three. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
> Can't wait to have that one implemented as it's the one point i > tripped over with about every software i tried. Just to be clear - by writing down my ideas, I do not mean to imply that I (or anyone else) will actually implement them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Tuesday 05 January 2010 17:45:17 DJ Delorie wrote: > > Maybe i missed it, but I haven't seen a reference to something I'd > > call global gate swapping. > > Assigning gates to packages is one of the things left up to the > netlister (choosing) and pcb (swapping) now. > > > So, is there a sensible way to leave decision actual packages and > > relations between symbols and packages open until some later time? > > Yes, that's the general idea. > > > As i see it, such a way would be somewhat conflicting with the > > current way of slotting symbols and providing refdeses based on > > order of entry > > Yes, the old slotting mechanism would have to be changed or removed to > work with this blue-sky idea. > > Very cool. Can't wait to have that one implemented as it's the one point i tripped over with about every software i tried. Greetings, Florian signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
> Maybe i missed it, but I haven't seen a reference to something I'd > call global gate swapping. Assigning gates to packages is one of the things left up to the netlister (choosing) and pcb (swapping) now. > So, is there a sensible way to leave decision actual packages and > relations between symbols and packages open until some later time? Yes, that's the general idea. > As i see it, such a way would be somewhat conflicting with the > current way of slotting symbols and providing refdeses based on > order of entry Yes, the old slotting mechanism would have to be changed or removed to work with this blue-sky idea. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB line limit of 255 in pcb
On Sun, 27 Dec 2009 21:46:07 -0800, Anthony Shanks wrote: > This worked! Thanks Did you write a bug report on this? IMHO, this needs to be fixed. The work-flow should not break if the project grows beyond some reasonable size. --<(kaimartin)>--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: looking to hire a geda expert
I am starting a small electronics company and I need to hire a geda expert to help make some pcb designs. I already have a few ideas lined up and I am willing to pay well. Please email me back if anyone is interested. Jason from shenzhen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Sunday 27 December 2009 04:11:57 DJ Delorie wrote: > I took the time to document my ideas about heavy vs light symbols and > the pin mapping problem: > > http://www.delorie.com/pcb/component-dbs.html > http://www.delorie.com/pcb/pin-mapping.html > At first, let me thank DJ for writing it all down. I just wonder, how flexible this pin mapping could be. Maybe i missed it, but I haven't seen a reference to something I'd call global gate swapping. I better describe what I mean by that term for lack of better words: Especially with OpAmp designs I often end up with dropping a bunch of generic OpAmps first and replace them later in the design process with parts better suited to the job. Something along the lines of "just throw a couple 741s in" and later saying "hmm, this high impedance mic input would call for an OpAmp with JFET input stage" plus replacing with some TL074. Some time later still, one might say "oh well, I better decouple those four OpAmps, let's switch to 2x TL072", again replacing some symbols. Somewhere in between when replacing four 741s with one TL074, there were two power pins left orphaned and two missing by accident and desaster is ready to strike. So, is there a sensible way to leave decision actual packages and relations between symbols and packages open until some later time? I'd imagine something like a generic and extensible symbol "OpAmp" (might be extended with dedicated power pins, compensation capacitors, offset trimming, remarks on needed capabilities like JFET input, precision, low noise, chopper, younameit) and a part providing a set of, say, two Opamps with compensation in a 14-pin SOIC and another part providing four OpAmps in a 14-pin DIP plus some clever way to determine what OpAmp to put into which package (clearly to be overridden by the user). As i see it, such a way would be somewhat conflicting with the current way of slotting symbols and providing refdeses based on order of entry because later changes of mapping between symbols and actual parts, those refdeses will inevitabely be mixed up really bad. Wuould something like that be possible?? Greetings, Florian signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
