Re: gEDA-user: Remove solder mask from polygons
On Wed, 29 Jun 2011 23:41:06 +0200 Kai-Martin Knaak wrote: > George Boudreau wrote: > > > I am working on a micro-stripline layout and the presence of the > > soldermask on portions of the board will cause problems. With > > gEDA/pcb micro-stripline work is a drafting task consisting of > > numerous polygons. Is there a method/switch that will allow me to > > remove blocks of the solder mask. This exposed copper will be gold > > plated. > > Two hacks: > > 1) Select the tracks to be gold plated. > > 2) Cut the selection to buffer > > 3) Do convert_buffer_to_element from the buffer menu > > 4) Paste the result. This is formally a footprint. Tracks will > behave like SMD tracks. That is, they will be cleared from solder > mask > > 5) You can increase solder mask clearance as needed with the [k] > key when soldermask is active. Alternatively, you can use the > ChangeClearSize() action. See > http://pcb.gpleda.org/pcb-cvs/pcb.html#index-ChangeClearSize_0028_0029-548 > > Drawback number one: gsch2pcb will remove the footprint on its next > run. This can be fixed, if you make the micro-strip a real footprint > and add a micro-strip symbol to the to the schematic. Actually gsch2pcb won't remove a footprint that has no name, so this drawback does not apply: just don't name the micro-strip "element" on the board. > Drawback number two: This works only with tracks vias and rectangles. > No arcs, no text, no arbitrary polygons. > > > The second hack can uncover any object: > > 1) Draw a line (with "new_lines_clear_polygons" activated). > > 2) Cover th track with a polygon. > > 3) Convert to footprint and paste as before > > 4) Save. > > 5) Open the file with a text editor > > 6) Locate the pad definition. It will be the last line in its layer > section. > > 7) Set the thickness to zero (third parameter). > > 8) Reload the layout. The zero thickness pad will stand out in the > polygon. > > 9) Set mask clearance as before. > > 10) Export gerbers. > Make sure, your fab does not barf on zero thickness lines. I put > a comment in the README that tells them, this is no error and they > can safely remove zero thickness lines. If you want to be double > sure, you can use the edit abilities of gerbv to remove the line > yourself. > > I use this second hack to achieve text with exposed copper. The shiny > HAL surface makes for good readability. That's an interesting trick; I'll have to try it sometime. Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
The transformer allows a DC path to exist on the secondary side, but you still have the capacitor on the primary side of the circuit. If the positive and negative pulse currents are not equal, you will still have a problem on the primary side. You need to remove the cap C1. I still can't tell exactly what is going on in your circuit because you don't provide any labels on the o'scope diagrams. It would also be useful to see current waveforms from the simulations and waveforms from the loads. As was asked for previously, we still have not seen your requirements so I can't tell exactly what you are trying to do with this circuit. How large is the DC offset in the source? Why don't you include that in your simulation model? What voltage do you need out of this supply? I really can't tell what is needed in your design and what is just wrong. Rick On 6/24/2011 7:10 AM, myken wrote: This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? On 22/06/11 22:39, Andy Fierman wrote: Sorry Robert, Both Wojciech and I are wrong. His suggestion about adding a choke is basically the same as mine of using a transformer. The idea of both is to add a dc path to ground at the rectifier inputs. The difference is that the transformer adds DC isolation - which if you include your bandpass filter - you do not need. Sounds like the thing to do but sadly, the simulations show the reality! A choke does not do what you want and neither does a simple 1:1 transformer. However, if you use a 1:1:1 transformer then it all comes together. You can use a transformer with a 1:2 turns ratio, centre tapped and keep to the original half wave rectifier scheme. If you use a three winding transformer of 1:1:1 then you can use two bridge rectifiers. Using bridge rectifiers doubles the ripple frequency so allows lower smoothing C for the same ripple voltage. The attached (not very good quality) pdf shows the non-working choke and 1:1 transformer ideas and the working 1:1:1 transformer versions. Note the 1u smoothing capacitor values. These were reduced to make the simulation reach a steady state sooner than with the original 100uF values. Andy. signality.co.uk On 22 June 2011 01:12, Wojciech Kazubski [1][1] wrote: Hello all, I would appreciate some expert advice. I have a system which rectifies a sine wave input signal of 20Khz after a LC filter (see Rectifier_sim.jpeg) Everything works fine if LOAD_1 and LOAD_2 are equal. Vx is then (almost) the same as Vin. And Vcc and Vss are equal to the positive or negative part of the sine wave (less the DC losses) (Vss = -Vin_top and Vcc = Vin_top). BUT if LOAD_1 and LOAD_2 are not equal (like in Rectifier_sim.jpeg) it seems that Vx is lifted (DC component added) and Vss moves to the 0V and Vcc is lifted to twice the value I would expect (Vss = 0 and Vcc = Vin_toptop) (see rectifiersmp.eps). Our real life prototype shows the same behaviour as the simulation. I need this set-up for my system to work and I can not guarantee that the two loads always will be equal. Vin can be anything between 10Vtt and 90Vtt. I have tried adding a resistor from Vx to ground and that seems to help but increases the current drawn from the source (V1) to a unacceptable level. It should be a low power solution. If I short-circuit C1 everything works fine again (V1 has a low resistance output) but of course will disable the filter, which we don't what. Is there anyone here who can explain to me how and why this is happening and if available can anyone suggest a solution to me. I have been wrestling with this problem for a couple of days now, so any help will be very much appreciated. Many thanks, Robert There is no DC patch from Vx to ground. If both loads are equal, both rectified curreant are equal and cancel one another. If the loads are different, the imbalance current charges Vx node until both output currents become equal again. To avoid this place a choke between Vx and ground. Wojciech Kazubski ___ geda-user mailing list [[2]2]geda-user@moria.seul.org [3][3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [[4]4]geda-user@moria.seul.org [5][5]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. [6]mailto:w...@o2.pl 2. [7]mailto:geda-user@moria.seul.org 3. [8]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 4. [9]mailto:geda-user@moria.seul.org 5. [10]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user __
gEDA-user: Open GL
I'm having trouble building the latest PCB from git on the Mac (10.6.8), here is the output from the build: checking If the compiler accepts -rdynamic... yes checking ./src/hid/batch/hid.conf checking ./src/hid/bom/hid.conf checking ./src/hid/gcode/hid.conf checking ./src/hid/gerber/hid.conf checking ./src/hid/gtk/hid.conf checking ./src/hid/lesstif/hid.conf checking ./src/hid/lpr/hid.conf checking ./src/hid/nelma/hid.conf checking ./src/hid/png/hid.conf checking ./src/hid/ps/hid.conf checking for which gui to use... gtk checking whether to enable toporouter... yes checking whether to enable toporouter output... no checking for pkg-config... /opt/local/bin/pkg-config checking pkg-config is at least version 0.9.0... yes checking for whether to use DBUS... yes checking for DBUS... yes checking for dbus_watch_get_unix_fd... yes checking for whether to use GL drawing... yes checking GL/gl.h usability... no checking GL/gl.h presence... no checking for GL/gl.h... no configure: error: You don't seem to have the GL library headers installed. It seems that it things that there are GL librarys, but they are built in on the Mac. I found this with Google: Porting to/from OS X OpenGL == cross-platform, right? Almost. Porting an existing OpenGL application to or from OS X is largely a matter of headers (I think...). For some unknown reason, OS X puts the headers in a different location in the include path than Windows and Linux (and probably a bunch of other *n?x OSes). Here's the skinny: Header Description Mac OS X The Rest of the World GL - OpenGL Base#include #include GLU - OpenGL Utility#include #include GLUT - OpenGL Utility Toolkit #include #include The question is how do I get the configure to find these includes when they have different names? TIA Ed ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Remove solder mask from polygons
George Boudreau wrote: > I am working on a micro-stripline layout and the presence of the soldermask > on portions of the board will cause problems. With gEDA/pcb micro-stripline > work is a drafting task consisting of numerous polygons. Is there a > method/switch that will allow me to remove blocks of the solder mask. This > exposed copper will be gold plated. Two hacks: 1) Select the tracks to be gold plated. 2) Cut the selection to buffer 3) Do convert_buffer_to_element from the buffer menu 4) Paste the result. This is formally a footprint. Tracks will behave like SMD tracks. That is, they will be cleared from solder mask 5) You can increase solder mask clearance as needed with the [k] key when soldermask is active. Alternatively, you can use the ChangeClearSize() action. See http://pcb.gpleda.org/pcb-cvs/pcb.html#index-ChangeClearSize_0028_0029-548 Drawback number one: gsch2pcb will remove the footprint on its next run. This can be fixed, if you make the micro-strip a real footprint and add a micro-strip symbol to the to the schematic. Drawback number two: This works only with tracks vias and rectangles. No arcs, no text, no arbitrary polygons. The second hack can uncover any object: 1) Draw a line (with "new_lines_clear_polygons" activated). 2) Cover th track with a polygon. 3) Convert to footprint and paste as before 4) Save. 5) Open the file with a text editor 6) Locate the pad definition. It will be the last line in its layer section. 7) Set the thickness to zero (third parameter). 8) Reload the layout. The zero thickness pad will stand out in the polygon. 9) Set mask clearance as before. 10) Export gerbers. Make sure, your fab does not barf on zero thickness lines. I put a comment in the README that tells them, this is no error and they can safely remove zero thickness lines. If you want to be double sure, you can use the edit abilities of gerbv to remove the line yourself. I use this second hack to achieve text with exposed copper. The shiny HAL surface makes for good readability. ---<)kaimartin(>--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: A Short History of Electronic Data Formats
Thought this might be of interest to the devs: Printed Circuit Design & Fab Magazine http://pcdandf.com/cms/designnews/8107-a-short-history-of-electronic-data-formats ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Remove solder mask from polygons
On Thu, Jun 30, 2011 at 2:23 AM, George Boudreau wrote: > Hi. > I am working on a micro-stripline layout and the presence of the > soldermask on portions of the board will cause problems. With gEDA/pcb > micro-stripline work is a drafting task consisting of numerous > polygons. Is there a method/switch that will allow me to remove blocks > of the solder mask. This exposed copper will be gold plated. > Regards, > George gEDA/pcb has no easy way to do this task. If I were doing it, I'd use this approach: 1. create a new layer, let's call it "mask openings" 2. place polygons in the new layer that correspond to the extra mask openings that you want 3. when you're done, export gerbers 4. hack the gerbers - a. Remove the drill holes from "mask openings" gerber (PCB will have assumed it's a copper layer and added all through holes) b. Merge the "mask openings" gerber with the standard mask gerber To do the gerber hacking I'd use gerbv to find out which apertures are used for what and then a text editor to remove the through holes and merger the gerbers. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Remove solder mask from polygons
On 6/29/2011 9:23 AM, George Boudreau wrote: I am working on a micro-stripline layout and the presence of the soldermask on portions of the board will cause problems. With gEDA/pcb micro-stripline work is a drafting task consisting of numerous polygons. Is there a method/switch that will allow me to remove blocks of the solder mask. You could create footprints in your text editor of copper free pads with the appropriate mask clearance to suit your needs. A small set of rectangular parts ought to work. I've done this for other parts, but thinking about it there has always been some copper there to grab onto in PCB. So I'm not sure you'll have anything to select in PCB if there is no copper but the approach has worked for me in other similar situations. Phil Taylor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Remove solder mask from polygons
Hi. I am working on a micro-stripline layout and the presence of the soldermask on portions of the board will cause problems. With gEDA/pcb micro-stripline work is a drafting task consisting of numerous polygons. Is there a method/switch that will allow me to remove blocks of the solder mask. This exposed copper will be gold plated. Regards, George ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Crash in gschem
Eivind Kvedalen writes: > Using head (dad94bf12c2ef120fae7a45a0020107815b84ef0), gschem crashes > when double-clicking on an object. Fixed. Peter -- Peter Brett Remote Sensing Research Group Surrey Space Centre pgpiRoKiRZuYB.pgp Description: PGP signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
