Re: gEDA-user: autocrop.c vs. pcb (git head)
On Thu, May 12, 2011 at 03:03:20AM +0200, Levente Kovacs wrote: > > What I get is this: > > dl_error: /home/leva/.pcb/plugins/autocrop.so: undefined symbol: > ClearAndRedrawOutput > > Is there any way to tweak pcb and/or autocrop.c to work together? If someone who has been hacking on the GUI can tell me what the functional replacement is (or if it's simply unnecessary now) I can fix the plugin. Levente: You could simply delete that line from the source and recompile. The worst that might happen is that you have to force the screen to redraw somehow after autocropping. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
On Mon, Apr 11, 2011 at 04:55:15PM +0200, Kovacs Levente wrote: > > I am selecting capacitors for the low pass harmonic filter bank at the output. > My question is what kind of capacitors should I use? I apply not more then > 100V of say 30MHz maximum. The classic cap in this application is silver mica. High voltage capacity, super tolerance compared to other types (to 0.25%! but commonly 1% or 2%). The only ones I have are enormous bulky things with "dot" style marking. A quick search on Mouser turns up only SMT ones... > My best bet is to use X7R capacitors with as much DC voltage rating as I can > get. I don't know if there's any connection between the DC and AC losses. Not X7R. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Modding Nintendo 3DS controllers for accessability
On Sun, Apr 03, 2011 at 05:54:36PM +0100, Peter Clifton wrote: > " > i recently got a nintendo 3ds, and really enjoying the 3d of the games > but my issue is because i can only use my right hand, using the > controller is difficult. i'm not sure whether it can be done but can you > think of an idea where i can convert or modify or attach something to > the 3DS to make the analogue + 3 buttons operable with my singlee right > hand? > " The guy you want is Ben Heck. http://benheck.com/ He has done tons of game machine mods (eg laptop style xbox, portable N64) and accessibility hacks (single handed controllers included). -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb plugin smartdisperse fails on load
On Thu, Feb 24, 2011 at 03:28:10PM +, Peter Clifton wrote: > > I think if we continue with plugins the way we do, we need some API to > advertise an API version, and means for plugins to load (or fail to > load) based upon compatibility with a given version. It's funny that those plugins broke due to missing "malloc" wrappers. That's the least of what they know about the internals of PCB. A big attraction to me of keeping plugins bundled with the PCB source (for "known" plugins of general utility) is the possibility that someone making a source mod might find and update the plugin dependencies. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb plugin smartdisperse fails on load
On Thu, Feb 24, 2011 at 05:01:33AM +0100, Kai-Martin Knaak wrote: > Mark Rages wrote: > > > License allowing, can you please post the fixed plugins somewhere? > > The necessary modifications are simple one-liners. > Both are plugins are GPL, so here you go: > http://lilalaser.de/tmp/smartdisperse.c Thanks for fixing that. You got to it before I even saw the first message about the breakage. I updated the copy I link from gedasymbols. I was dismayed to see I have that source under RCS (!) control. Time to upgrade! I'll made the change to distalign.c too. I still think that's a plugin worthy of being plumbed into the UI. Earlier discussions of arcs made me think that "distribute along arc" wouldn't be a bad idea. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb commands to automatically select, cut, rotate, and paste elements
On Wed, Feb 23, 2011 at 04:18:48PM -0500, DJ Delorie wrote: > > > A MoveComponent() action would be a major step toward general > > scriptability. IMHO, this should be part of the core, not as a > > volatile plugin. > > If you'd like to do the patch, go for it. Otherwise, a plugin gets > him a solution faster, and it can be merged into the core later. The bulk of the solution may be in my autocrop plugin: It knows how to move everything. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any place that fabs custom project boxes?
On Fri, Feb 18, 2011 at 03:08:27PM -0600, John Griessen wrote: > > HeeksCAD is very usable 3D. With it you can quickly do booleans > to create ports, slots, etc. It uses a 2D layer called sketch > frequently to transfer a shape into 3D. If you want to warp ahead a few years worth of development and you have $200, Alibre Design works the same way. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB fab with <= $5 with 50 qty order?
On Thu, Feb 17, 2011 at 07:41:51AM +1100, Stephen Ecob wrote: > > > > The closest I could find was 150 boards with $4.47 per board cost at > > Advanced Circuits. Their 50 qty order is $9.94 :( > > Try: > > http://custompcb.com/ I would not recommend CustomPCB (aka Silver Circuits) for a 50 board run. I've used them before and the individual boards have required too much attention to imagine using them for 50+. I got one batch where most of the vias did not conduct (my board easily exceeded the DRC requirements). They were happy to replace my order but they screwed up the drill sizes for some connectors (which I worked around by mangling the connectors). Some of my 8mil traces were barly 3mil wide in places. I will note that I have ordered from them knowing full well what I'll get for the price, but for qty 50 I'd want more "plug and play". I would never use them for a PCB going in a kit! -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fluky Fluky layout printing problem!
On Tue, Jan 25, 2011 at 04:54:53PM -0500, DJ Delorie wrote: > > I saw that, but that's perfectly valid... > > square pads would have a length of zero. Square pads do get special treatment in a few places, so it wouldn't go amiss to try barely rectangular (even by 1/100th mil) to see if a clearance or printing problem goes away. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB bug: invisibly select pads from deactivated far side
On Wed, Jan 05, 2011 at 11:05:06PM +0100, Stephan Boettcher wrote: > DJ Delorie writes: > > > > If an element is on the front side, but has pads on both sides, and the > > back side is hidden, when you select the element, should the hidden pads > > be selected too? > > No. Not for operations that operate on selected pads. This was an olld bug in de-selection. It worked like an anti-selection of a rectangle covering everything. Unfortunately it honored visibility and if you hid a selected item it stayed selected until you made it visible again! -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gRX OS board
On Mon, Nov 08, 2010 at 05:05:37PM -0500, DJ Delorie wrote: > > For my second RX project, I was thinking of a board with an ethernet > switch chip (the RX has MII) Broadcom makes some really nice, fully integrated switch chips which would be perfect for this application. You can (optionally) hang off the slow speed "admin" port and divert packets there for fancy stuff. The switch itself is almost fully automated, including configuring phys and implementing all kinds of policies (like VLAN) with only SPI config. Unfortunately I doubt a one-man shop can get the time of day from BCM and they keep their docs locked up like a virgin princess. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: icarus, fork, and recursive tasks
On Mon, Nov 08, 2010 at 02:32:08PM -0500, DJ Delorie wrote: > > In theory, the 3AN can drive the DVI at 1024x768x24 but we'll see how > much logic I can actually cram into it. Does the 3AN really meet the DVI spec without a cable driver? -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL notes on VBOs
On Fri, Nov 05, 2010 at 09:46:00AM +, Peter Clifton wrote: > > Other than this, I don't know why glMapBuffer() doesn't "just work" > performantly I would expect it to map GPU memory directly via PCI, which is going to have much higher overhead than writing to a host buffer and letting the card DMA via subdata. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: More OpenGL ideas
On Thu, Oct 28, 2010 at 06:52:16PM +0100, Peter Clifton wrote: > > The layer textures could be A8 textures, rather then ARGB textures. > (Saving 4x memory). This would require the combining to be done in a > pixel shader which can colour each layer. The fixed pipeline already multiplies the front color by the texture. Typically you set the color to 1,1,1 so you get the texture unmodified, but you could set it to a color and use a white texture. > I'm not yet sure how to do colouring of selected components (will > probably require the geometry to be re-spat-out with flags on selected > parts, or selected parts drawn separately). If you remember where each component is in the VBO you can just draw the sub-array corresponding to selected component. You could use the same information to avoid drawing it "plain" or something like glPolygonOffset to overdraw the highlighted version. > For "finding" connected tracks, I thought if might be nice to tag the > vertices we emit with a netID number. I don't know how quickly we'd run > out of IDs, but it shouldn't be a real issue. Every uniform and attribute is a float. If you use whole float numbers you'd only have 24 bits. If you carefully pack the data into the whole 32-bit float you could probably manage to use the exponent bits too. But you can always use a 2, 3 or 4 float attribute as well. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: multiple monitors
On Fri, Oct 01, 2010 at 08:31:37PM +0100, Peter TB Brett wrote: > > I couldn't live without multiple monitors. I decided I could live with one monitor... It's an LG 30" LCD 2560x1600. At work I use 2x20" (total 3200x1200, just slightly fewer pixels). The one big display is much more flexible and requires less head turning. It did cost $1000, though, and 20" LCDs are given away in cereal boxes these days. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb minor release, C++ and Gtk cleanup
On Sat, Sep 25, 2010 at 11:37:12AM -0700, Andrew Poelstra wrote: > > The list has quieted down these last couple weeks. Last I heard, any > significant work on pcb is essentially blocked, pending a migration > to C++. And before that can happen: Hey, cool. I have been mostly skimming so I must have missed this in one of those threads that wandered wayy off topic (you know that the 100th message titled "TO92 land pattern" has probably covered everything from polygons to XML). Anyway, if there's a code sprint to convert the core of PCB to C++ I'm in. I've almost done it a few times myself. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: sch2csv and csv2sch
On Thu, Sep 16, 2010 at 01:53:09PM -0400, DJ Delorie wrote: > > Note: if you import these CSV into OpenOffice, make sure to select the > whole sample spreadsheet in the import dialog (click the upper left > empty box), and specify "Text" for the format. Otherwise, things like > 0805 get turned into 805 since they're considered numbers. You might be able to get around this with quoting. Or hey, output ODF directly! :) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: wishful UI
On Fri, Aug 13, 2010 at 07:28:10PM -0400, DJ Delorie wrote: > > > I guess it would be no great deal for smart (but very busy) people > > like Peter C. and DJ, to implement the basic concept. For people not > > familiar with the internals of gschem and PCB like me it may take > > very long... > > I'm quite willing to teach people PCB internals, if it means having > more PCB developers. I'll answer internals questions on geda-dev from anyone who wants to ask. Of course I don't spend much time in PCB any more, but I've been around the block. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: need polygon expert again
On Wed, Aug 11, 2010 at 06:26:06PM -0400, DJ Delorie wrote: > > Is this the same glitch we've seen before, or a new one? I'm sure it's related to previous glitches in the sense that clearing oddly angled/shaped regions sometimes results in problems. I'd have to single step through the clearance to find the bad poly-sub operation and then go back and single-step through that one. Maybe we need a debug HID. ;-) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: need polygon expert again
On Wed, Aug 11, 2010 at 05:42:10PM -0400, DJ Delorie wrote: > > I put screenshots of pcb, png, and gerbers on the page. > > http://www.delorie.com/electronics/hdd_clock/ > > pcb 1.99z as of June 14th The area around C2 is a second-order effect. The glitch is where the "pulled" traces go around the IC pins just below C2. The rectangular hole is the result of the dicer cutting through the middle of a pin (could have been any of the pins at that grid point) vertically. That slice got messed up because of the glitch by the IC. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: need polygon expert again
On Tue, Aug 10, 2010 at 09:33:30PM -0400, DJ Delorie wrote: > > http://www.delorie.com/electronics/hdd_clock/ > > Note that the top layer is missing a chunk near C2. It seems to have > placed it rotated 180 degrees around that pin. Ahh it would have been nice if you'd mentioned the PNGs aren't showing that problem on the web page! > It's OK in postscript and gui > > It's BAD in gerber and png That's an odd combo. PS, most flavors of GUI and gerber use the dicer to draw polygons, while PNG can use erasure, which might explain something. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Diode pin numbers reversed?
On Sun, Jun 13, 2010 at 10:57:50PM -0700, Matthew Lai wrote: > Am I having a brain fart or does the stock diode-1 symbol have opposite > pin numbers as the ALF300 footprint? > > What would be the best way to go about fixing that? As I recall there are two different diode symbols with opposite pin numbering (diode-1, diode-2). The nice thing about standards is that there are so many to choose from. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: git HEAD PCB now supports user-defined holes in polygons
On Tue, Jun 08, 2010 at 09:25:44PM +0100, Peter Clifton wrote: > > I think you might be on my "local_customisation_before_pours" branch, > rather than my "before_pours" branch. If your public repository is also your working copy, users who clone it will start on whatever branch you are in when they happen to clone. If the public repo is separate (typically bare) and you push to it, users will not have this issue. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: I am such a troll for posting to slashdot
On Sat, Feb 27, 2010 at 05:31:58PM +0900, timecop wrote: > > standard parts library. ?And if you're making footprints and symbols, > > text files generated by scripts are FAR superior to any GUI. ?I'd never > > get 100-1000 pins right if I had to use a GUI. > lol, every altium user disagrees. > if you ever seen their IPC pattern / component wizard, you wouldn't be > saying this. Not OT. Put up a video showing it in action. Mabye geda hackers will be inspired. I really think one thing holding back geda is that the users and developers don't have much experience with high-end tools. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: I am such a troll for posting to slashdot
On Fri, Feb 26, 2010 at 11:15:13PM -0700, Eric Brombaugh wrote: > > Don't know what they're complaining about - When I started using gschem > & pcb a few years ago I just committed to doing it, ran through the > tutorials and got on with it. I started using gschem+PCB because I needed to make a big 4 layer board, and there was no way I was going to pay to put up with the quirks of Eagle. So instead I used gschem+PCB and hacked on the quirks. I remember thinking that it was a bummer that there wasn't a great standard parts library. I also remember when I realized how crazy it was to rely on ANY standard parts library. And if you're making footprints and symbols, text files generated by scripts are FAR superior to any GUI. I'd never get 100-1000 pins right if I had to use a GUI. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Another way to make homemade vias?
I hadn't seen this one: http://charliex2.wordpress.com/2010/01/08/lpkf-easycontac-test/ -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Wed, Feb 24, 2010 at 04:41:35PM -0500, Bob Paddock wrote: > > I would have just ensured that my AVR image didn't contain any sequences > > that trigger the problem. > > How? Its a crap shoot as to know if any particular image will > generate the bad sequence. > Then you waste time trying to figure out how to get around it. You can "waste time" spinning the board or "waste time" working around the programming issue. If it's just part of your normal board spins, obviously you just change the board. If you didn't happen to encounter a problem issue until after you have 50,000 made, then you spend time avoiding the problem at the programming stage. I bet it wouldn't be that hard to modify AVRdude to avoid a specific output bit sequence during programming without modifying your image at all. "Worst" case is to find a bootloader that doesn't trigger the problem (or is easily modified to avoid it) and then you control both ends. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Wed, Feb 24, 2010 at 04:07:13PM -0500, Bob Paddock wrote: > > I've learned most of this by working at a large CM, and 'The Hard Way' > of doing it wrong. > > For example the job today is 5,000 boards. When you get into > quantities, you start to do things > differently. See the note at the bottom of my blog > http://blog.designer-iii.com/avr_isp_spi/20081116-10511-Digital-MEMS-Accelerometers-will-not-work-with-AVR-ISP-using-SPI > . > > ""You are supposed to isolated the AVR ISP pins with 1k resistors, as > the Atmel documentation shows". I would have just ensured that my AVR image didn't contain any sequences that trigger the problem. It might be possible to just modify AVRdude to detect such sequences and modify the programming sequence to avoid them. Sort of like bit stuffing with NRZI. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Prototype houses that do 0.031" boards?
On Wed, Feb 17, 2010 at 02:45:22PM -0500, Bob Paddock wrote: > Anyone know of a proto-house that will do 0.031" thick boards? I'm not there to measure it but I think the boards I got back from Sierra Proto Express's "no touch" service were 0.032". Thinner than I expected, anyway! -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: what does "Error while clipping PBO_SUB: 3" mean?
On Wed, Feb 10, 2010 at 11:30:59AM +, Peter Clifton wrote: > > Secondly, (also very important), if the problem is reproducible, take a > copy of the board with the issue, and start removing parts until the > problem goes away. Distilling a minimum test-case for the polygon code > is hard though - as it can depend on the exact order of operations. My technique is to delete the polygon and then try creating small ones over likely problem regions, or simply binary search (left half, right half, etc). I even have the polygon hotkey (F5!) memorized from doing this even though I rarely make polygons using the GUI. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb join pad to polygon
On Sun, Feb 07, 2010 at 09:18:35AM -0500, gene glick wrote: > I made a polygon on the top layer, and I want to place a component pad > within the polygon. Is there a way to make it connect without adding a > trace? By default the tool places a clearance gap around the pad - so > it doesn't touch. Are you sure you want 100% connection like the other reply suggested? That can be very hard to solder, especially on a multilayer board where the top is well "stitched" to internal ground layers. I really think pads should have the same "thermal" feature that pins do, but since they don't I just draw lines and set *them* to merge with the poly. If I want low impedence I just make a "+" of wires. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new components
On Fri, Feb 05, 2010 at 03:33:25PM -0600, Mike Crowe wrote: > tools (AT91SAM9G45, Atmel ARM9). The part is a 18 x18 =324 ball device > ... > Has anyone been making BGA parts with multiple symbol files? I've used PQ208 with one symbol per bank, one for general power (not IO-bank specific) and one for config and strap pins. All you have to do is give them the same refdes and it's all one part as far as the tools are concerned (actually I think you can suffix a lower case letter if you like and it will be ignored, eg U1a, U1b, but I didn't do that). > Can Alpha-number designators be used at all? I think so. Like others I wrote my own boxsym program so I don't know if DJ's is trying to enforce numeric pins. Here's an example of a BGA on gedasymbols: http://www.gedasymbols.org/user/darrell_harmon/symbols/xilinx/index.html They have alphanumeric pin names. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new components
On Tue, Feb 02, 2010 at 06:11:44PM -0500, resea...@ottomaneng.com wrote: > I'm also creating symbols for an FPGA and a DSP which naturally has alot > of pins. I've once heard of using multiple files for the symbols so you For a really simple example look at http://ad7gd.net/xc9536/ where I split the power and IO. The symbols are also at http://gedasymbols.org/user/ben_jackson/ I could upload an Altera EP2C8 set of symbols if that would help. One symbol per IO bank, power, and config, iirc. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: more kvetch re: pcb Arcs
On Tue, Feb 02, 2010 at 10:17:01PM +0100, Stephan Boettcher wrote: > > With qcad, I use the grid to place the first object, and then turn it > off. With PCB I place the objects and then use snap-to-pin to draw lines. With auto-DRC you can get offsets of a bus pretty quickly. But a dedicated feature that worked across multiple segments would be nice. I should try to clean up jostle.c, too. I was surprised not to get much response to it. Maybe it was lack of pretty pictures! -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Taking advantage of internally connected pins
I need to make a key matrix. I'm considering selecting a switch which has 4 leads (two leads per internal net): o--+--o ' / | o--+--o This appears to be a boon for the grid-style routing I need for the switch matrix. The rows can hop the columns inside the part, making everything fit on a single layer. (obviously I wouldn't do this with an IC, but it seems harmless for a switch) Anyway, if I give all pins different numbers, PCB doesn't know about the internal structure. If I give the electrically connected pins the SAME numbers then PCB thinks it needs to connect them with copper itself. If I connect them on a 'fake' layer then the autorouter works but the toporouter spins and I have to kill pcb. Any better ideas? -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Pick-And-Place Extract
On Mon, Jan 25, 2010 at 07:47:48PM +0100, Thomas Weber wrote: > Unfortunately the pick and place data extractor of pcb has some problems > with SMD footprints with 3, 5, 7 ... pads. The appended example of a > SOT23 is centered but after exporting the xy file the center position is > shifted a little bit to the pins 1 and 2. Of course the xy position is > the mathematical mean value of the three vectors and in this sense > correct. But this differ from the real body center imho. Use center of the bounding box instead? The code is in src/hid/bom/bom.c PrintBOM. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Sat, Jan 23, 2010 at 03:51:50PM -0800, Windell H. Oskay wrote: > We have an Epilog. Low-power lasers of this type cannot cut (or even > etch) copper foil, nor can they cut FR4. Even the new one Techshop Portland just got (cuts 1.25" acrylic in one pass) can't make PCBs directly. But it did cost about the same as Epilog's lowest-end machine (the "zing"). http://www.rabbitlaser.com/products/laserse.htm -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Wed, Jan 20, 2010 at 10:55:51PM -0800, Dave N6NZ wrote: > > No, I was concerned about the shape of the pad w.r.t. correct solder reflow. I guess I was assuming that if you were milling a PCB you were prototyping and thus hand assembling. Of course you could still mill individual outlines if you wanted -- I was just looking at options to speed it up. It's an interesting geometry problem! > > The polygon code is fully generic. It can do what you describe (in fact, > > it does, it just probably doesn't output in the format you want). > > Hmmm well, point me at the code, and I'll have a look at seeing > what it would take to sew in Ribbonsoft's dxflib as a writer. All I > really want to do is convert the edges of pads into lines and arcs. This > sounds like an exercise in pulling X's and Y's out of pcb and stuffing > them into dxflib objects. Assuming I can get arcs for the ends of rounded > pads polygon1.c is "PCB code" that knows how to render PCB objects (like pads and lines) as polygons. polygon.c is a polygon library of sorts. Someone pasted in a long explanation I wrote into one of those (polygon1, I think). It knows how to make arcs, but it makes them out of straight segments. > Not me, that was the *other* Dave who was using inkscape, the Dave that > started this thread. I'm just thread-jacking to talk about paste stencils :) I can only handle one Dave at a time! -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Wed, Jan 20, 2010 at 09:20:34PM -0800, Dave N6NZ wrote: > On Jan 20, 2010, at 1:01 PM, Ben Jackson wrote: > > > > I have been thinking about how to do improved isolation routing. > > How do you differentiate between pads that must be a certain shape, like for > an SMT capacitor, and islands that simply need to be separated? We're talking about issues of parasitic capacitance here? I wasn't worrying about those issues. A SMT part would connect to two different nets and thus the two pads would be isolated. The way I envision it there would be a line cut halfway between the two pads (width somewhat out of our control because it is due to the depth of cut and the V-profile bit). > > If you want to save something like that directly from > > PCB, though, the polygon code could do all of your Inkscape steps > > internally. > > Ahhh so... does that mean the polygon code could be easily tweaked to > produce the vector outlines of all the pads on the paste layer? That would be > 95% of what I need for laser cutting solder stencils. The polygon code is fully generic. It can do what you describe (in fact, it does, it just probably doesn't output in the format you want). But it can also do the things you did in Inkscape (union areas, etc) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Tue, Jan 19, 2010 at 11:56:25PM -0500, d...@umich.edu wrote: > > I just created a thread on cnczone.com, which I want to bring to your > attention. I titled it, "Schematic Capture to dxf File - using gEDA, > Inkscape, and pstoedit": I have been thinking about how to do improved isolation routing. Someone mailed the list a picture where the only cuts were the ones necessary to cut the board into islands congruent with the copper. So imagine you have just two pads on your board. The 'outlines' would cut two boxes. The 'isolation' would just be a line bisecting the board between the two pads. Anyway, I'm surprised by your 'stroke to path' step. That turns every line into a rectangle. Then when you union them all you actually have a bunch of polygons with area, not 'hairlines' that you would chain cut in a CAM program. If you want to save something like that directly from PCB, though, the polygon code could do all of your Inkscape steps internally. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: soldermask clearance
On Sat, Jan 16, 2010 at 03:46:33PM -0500, gene glick wrote: > What's the right amount of clearance? Seems like .003" is good, but I > don't know. That has worked for me. Far better than leaving the random component defaults (often 10mil) which are far too large. What it really boils down to is how accurately your fab can register the mask. Keep in mind that if you go even to 4mil clearance on the mask because they can only hit +/-4, your mask could extend clear across an 8mil gap with the worst case misregistration. So to put it another way: Any decent fab can hit 8/8 rules and your mask clearance better be less than half the minimum gap, or <4mil, so 3mil seems good. > A google search found one article that said for fine > pitched parts, it's better to have the entire row blocked. That is, > instead of individual clearances around each pad, the soldermask exposes > the entire row at once. They claim the very thin webs in between pads > are too thin to cure correctly, and will smudge later onto the pads. A good fab will modify the mask in that case even if you specify it. > If there's no soldermask in between pads, isn't is more likely to get a > solder bridge? I've done .050mm QFP (about 0.020") with and without mask between the pads and I didn't find a big difference. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: little slivers from pours
On Sat, Jan 09, 2010 at 05:41:05PM -0800, Ben Jackson wrote: > > I meant automatic solutions which would enforce the normal DRC rules on > the slivers, eliminating any smaller than the minimum trace width. (replying to myself) Actually, I think I just figured out how to fix it AND do it live. I'll look into it. If I don't post back to the list in a few days someone pester me. ;-) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: little slivers
On Sun, Jan 10, 2010 at 05:28:05PM -0800, David Griffith wrote: > > This sounds like the solution. Do you have any sample code or pseudocode > on how to do it? Something like http://en.wikipedia.org/wiki/Rotating_calipers or one of the references from that article is probably on point. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: little slivers from pours
On Sat, Jan 09, 2010 at 05:14:31PM -0800, David Griffith wrote: > On Sat, 9 Jan 2010, Ben Jackson wrote: > > On Sat, Jan 09, 2010 at 03:24:27PM -0800, David Griffith wrote: > >> > >> Is there some way I can easily get rid of the little slivers of copper > >> left between traces when doing pours? > > > > Not without adjusting the clearance on the adjacent lines to squeeze out > > the slivers. I've considered several times how to fix this, and I can > > see options for doing in in a post-processing step, but that's not really > > in line with PCB's other polygon updates, which are all done live. > > Then go over with some sort of erasing tool (which doesn't seem to exist > yet) and erase the the slivers. How are you considering this as a > post-processing step? I meant automatic solutions which would enforce the normal DRC rules on the slivers, eliminating any smaller than the minimum trace width. If you're willing to go manual anyway you could just hit the keybinding for 'increase clearance by 1 mil' a few times on the objects causing the slivers. Of course it helps to tune your parts -- if you have an smt footprint with just enough space between the pads to allow a sliver, tweak it! Those are the ones likely to cause shorts, too. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: little slivers from pours
On Sat, Jan 09, 2010 at 03:24:27PM -0800, David Griffith wrote: > > Is there some way I can easily get rid of the little slivers of copper > left between traces when doing pours? Not without adjusting the clearance on the adjacent lines to squeeze out the slivers. I've considered several times how to fix this, and I can see options for doing in in a post-processing step, but that's not really in line with PCB's other polygon updates, which are all done live. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: large (29 inch) boards?
On Tue, Dec 22, 2009 at 02:52:47PM -0800, phil wrote: > Kyle Bassett wrote: > >why so long? if you don't mind me asking... > > They are a replacement board for this machine: > > http://plastitar.com/flickinger/ak_flick_3JAN2007/front_3.JPG If you can live with <= 16x16 modules I think your cost will go way down... -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I fill?
On Thu, Dec 03, 2009 at 03:34:02PM +, Ineiev wrote: > > Try polygons. Maybe the documentation should include a snippet of a board which is a clickable image map. Then each region can link to a 'howto'. Now we just need an imagemap HID to export it... -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Reducing the amount of jumpers
On Sun, Nov 29, 2009 at 10:15:21PM +0100, Stephan Boettcher wrote: > > Most connections were > later added with wires, the kind of wire used in transformers, I do not > know how it is called in English. That would be enammeled wire or "magnet wire". I can't find the page now, but I saw a guy who did amazing things with bare copper boards and magnet wire for prototyping. He used the copper as a ground plane and a combination of "dead bug" (glued ICs upside down) and other techniques to put the parts down. He did some high density stuff by isolating the non-ground legs of the SMT parts with kapton tape so it could be soldered flat to the board. Magnet wire is so small it didn't bunch up when taking off busses and stuff. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: More strange ideas: Start PCB layout from symbols view
On Wed, Nov 25, 2009 at 08:49:16PM +0100, Stefan Salewski wrote: > Currently we start new layouts in PCB with a bunch of footprints auto > dispersed. I wrote a 'smart disperse' plugin: http://www.gedasymbols.org/user/ben_jackson/geda-user/smartdisperse.txt You could try to improve the placement algorithm it uses, but it is at least smart enough to do things like put current limiting resistors by their connected components. After I wrote that I realized that what I really wanted was a 'tetris' plugin which uses the ordering hints like smartdisperse. Instead of just spreading the parts out everywhere it would give you the opportunity to click to place each component in order, with buttons to resort the list using various criteria (centered around a selected part, or whatever). The main advantage there is that you could place each component by clicking *once* rather than the more laborioius 1) find, 2) click & drag. > Of course this is fully incompatible with gEDAs current design. Not at all. The netlister that makes PCBs could place the components somewhere other than 0,0. It just doesn't... -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new ethernet chip...
On Tue, Nov 24, 2009 at 01:55:16PM -0500, DJ Delorie wrote: > > Digikey has the new KSZ8851 series... multiple bus options > (spi/8/16/32), built-in PHY, only 85 milliamps, under $10: > > http://www.micrel.com/page.do?page=product-info/embedded_control.jsp Neat. I was just thinking about a project where I could use something like this. Too bad they want to generate a sales lead in return for giving you a link to the datasheets. Luckily they're not bright enough to obscure the link: http://www.micrel.com/_PDF/Ethernet/ethernet_datasheet/ -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Black background on pcb
On Wed, Nov 18, 2009 at 03:37:47PM -0800, Anthony Shanks wrote: > Yes GTK. I thought I looked in that menu but only saw you can change > the colors of the pcb layers, I didn't see an option for background. I > guess I must have missed it. I'll check when I get home from work and > I'll give your colors a try, thanks. There was a bug that I fixed semi-recently that required a restart after changing some of the colors (such as background). Try that (or an upgrade ;-) if you don't get immediate results. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cheaper right angle component video terminal?
On Mon, Nov 16, 2009 at 02:21:16PM -0800, Anthony Shanks wrote:
> Wow, that is a very similar project I am working on myself (although
> our goals are different),
That reminds me that every time I see a "cheat at guitar hero" hack I
consider that my board would be ideal for making such a thing.
> did you do all the work yourself and how long did it take?
I did do everything myself. I had to reverse engineer the original board,
identify and source all of the board-to-panel connectors, choose the parts,
design the board (which involved moving to geda/PCB and making many
improvements to PCB itself!), code the FPGA and the microcontroller. I
even made a remote control for it eventually.
If you don't count the part where I worked on the original embedded PC
(fixing bugs in their board, adding audio support, reverse-engineering
a few kernel drivers so I could port to newer Linux, performance
enhancements to the ATI Mach64 driver...) the part where I worked toward
the hardware solution took about a year and a half.
> What ADC/DAC are you using and what processor are
> you using for the data processing?
The ADC is an Analog ADV7183B. It's a really awesome part. The output
of that goes to a Cyclone II FPGA which does the data processing. It
has two SSRAMs for framebuffering (DRAM would be cheaper but I had the
SSRAMs for free) Both are on an I2C bus and get parameter configuration
from an atmega8.
> What opamps are you using to drive
> the video? Max resolution? Did you consider a HDMI interface instead
> of component?
The output is 24 bit parallel RGB driven directly by the FPGA, so there
are no video output stages. That was the purpose of the board -- without
it you can't display anything at all on the plasma panel. It has no
other inputs. When it was driven by the embedded PC it was connected
to a FPD-link demux (takes a 4-wire high-speed-serial link directly from
the graphics chipset, typically used to cross the hinge of a laptop).
The display's resolution is 852x480 ("EDTV"). That's the size (with
square pixels) that you scale anamorphic squeezed input to for 16:9.
A lonng way into the project I realized I could probably make a very
simple board that would include a DVI demux and a EEPROM and make it look
like a DVI monitor, but that wasn't really my goal and I didn't pursue
it. I might have put HD input on it, but the Analog chips slightly upscale
from the one I picked (which include HD and VGA inputs) don't have docs
online.
--
Ben Jackson AD7GD
http://www.ben.com/
___
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Re: gEDA-user: Cheaper right angle component video terminal?
On Mon, Nov 16, 2009 at 01:47:48PM -0800, Anthony Shanks wrote: > I see, I actually like the black frame, I was just interested if any > company sold them for cheaper. I'll just use the digikey part. I'm sure they'd be cheaper in bulk from CUI. Usually Mouser is a good place to check for connectors -- often they beat Digikey's prices. I checked when I replied originally and they don't carry them. > May I ask what that project was in your screenshots? It takes in analog video, deinterlaces it, converts it to RGB, gamma corrects it, scales it and displays it on a 42" plasma panel. I got the panels free with an ancient embedded PC driving them. Watched Monday Night Football on it last night! :) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cheaper right angle component video terminal?
On Mon, Nov 16, 2009 at 10:51:20AM -0800, Anthony Shanks wrote:
> Hi all,
>
> Does anybody know of a cheaper right angle component video terminal?
> The only one I found on digikey was this one:
>
> http://search.digikey.com/scripts/DkSearch/dksus.dll?WT.z_header=search_go&lang=en&site=us&keywords=CP-1446-ND&x=0&y=0
I used that connector. The individual connectors are the same as the
RCJ-04x series, so you could buy them without the black 'frame', although
I'm not 100% sure how they intend you to mount without the frame (they
only have front 'feet' and if you want them to sit at uniform height
with and without frame you have to keep the feet). Also, that part does
not have the colors in the standard order. I popped them out of the
frame and rearranged them:
http://ad7gd.net/geda/panelfull-sm.jpg
The colors are specified by the trailing 3 digits, so CUI will make them
correctly, I just think digikey stocks the wrong part.
I've attached my footprints and symbols, which you can see in action here:
http://ad7gd.net/geda/panelusb-sm.jpg
The 'blade' shaped post is snug on my footprint because of the seating
issue I described.
--
Ben Jackson AD7GD
http://www.ben.com/
Element[0x0 "CUI Mini-DIN (SVideo)" "" "" 0 0 0 0 0 100 0x0]
(
Pin[-13400 33500 6500 2000 8500 3500 "" "1" 0x0101]
Pin[13400 33500 6500 2000 8500 3500 "" "2" 0x01]
Pin[-13400 43300 6500 2000 8500 3500 "" "3" 0x01]
Pin[13400 43300 6500 2000 8500 3500 "" "4" 0x01]
Pin[26550 21700 11500 2000 13500 8500 "" "5" 0x01]
Pin[-26550 21700 11500 2000 13500 8500 "" "6" 0x01]
Pin[0 18500 11500 2000 13500 8500 "" "7" 0x01]
ElementLine[-27250 5 -27250 0 1000]
ElementLine[-27250 0 27250 0 1000]
ElementLine[27250 0 27250 5 1000]
ElementLine[27250 5 -27250 5 1000]
)
Element[0x0 "CUI Triple Horizontal RCA Jack" "" "" 0 0 0 0 0 100 0x0]
(
Pin[-33500 59100 12500 2000 14500 9500 "" "2" 0x01]
Pin[-15700 59100 12000 2000 14000 9000 "" "1" 0x01]
Pin[-33500 0 12500 2000 14500 9500 "" "4" 0x01]
Pin[-15700 0 12000 2000 14000 9000 "" "3" 0x01]
Pin[-33500 -59100 12500 2000 14500 9500 "" "6" 0x01]
Pin[-15700 -59100 12000 2000 14000 9000 "" "5" 0x01]
Pin[-15700 80800 12000 2000 12000 11000 "" "8" 0x01]
Pin[-15700 -80800 12000 2000 12000 11000 "" "9" 0x01]
ElementLine[5000 75100 5000 43100 1000]
ElementLine[5000 43100 37000 43100 1000]
ElementLine[37000 43100 37000 75100 1000]
ElementLine[37000 75100 5000 75100 1000]
ElementLine[5000 16000 5000 -16000 1000]
ElementLine[5000 -16000 37000 -16000 1000]
ElementLine[37000 -16000 37000 16000 1000]
ElementLine[37000 16000 5000 16000 1000]
ElementLine[5000 -43100 5000 -75100 1000]
ElementLine[5000 -75100 37000 -75100 1000]
ElementLine[37000 -75100 37000 -43100 1000]
ElementLine[37000 -43100 5000 -43100 1000]
ElementLine[-38000 88600 -38000 -88600 1000]
ElementLine[-38000 -88600 5000 -88600 1000]
ElementLine[5000 -88600 5000 88600 1000]
ElementLine[5000 88600 -38000 88600 1000]
)
Element[0x0 "CUI RCA Jack" "" "" 0 0 0 0 0 100 0x0]
(
Pin[-33500 0 12500 2000 14500 9500 "" "2" 0x01]
Pin[-15700 0 12000 2000 14000 9000 "" "1" 0x01]
ElementLine[0 16000 0 -16000 1000]
ElementLine[0 -16000 37000 -16000 1000]
ElementLine[37000 -16000 37000 16000 1000]
ElementLine[37000 16000 0 16000 1000]
ElementLine[-38000 19000 -38000 -19000 1000]
ElementLine[-38000 -19000 0 -19000 1000]
ElementLine[0 -19000 0 19000 1000]
ElementLine[0 19000 -38000 19000 1000]
)
v 20070526 1
P 1000 400 600 400 1 0 0
{
T 1000 400 5 10 0 0 0 0 1
pintype=pas
T 695 445 5 10 1 1 0 0 1
pinnumber=1
T 1000 400 5 10 0 0 0 0 1
pinseq=1
}
P 1000 0 600 0 1 0 0
{
T 1000 0 5 10 0 0 0 0 1
pintype=pas
T 695 45 5 10 1 1 0 0 1
pinnumber=2
T 1000 0 5 10 0 0 0 0 1
pinseq=2
}
L 600 0 400 0 3 0 0 0 -1 -1
L 400 0 300 100 3 0 0 0 -1 -1
L 300 100 200 0 3 0 0 0 -1 -1
B 0 0 100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 50 300 50 400 3 0 0 0 -1 -1
L 50 400 600 400 3 0 0 0 -1 -1
T 75 425 8 10 1 1 0 0 1
refdes=J?
v 20070526 1
P 1000 2000 600 2000 1 0 0
{
T 1000 2000 5 10 0 0 0 0 1
pintype=pas
T 695 2045 5 10 1 1 0 0 1
pinnumber=1
T 1000 2000 5 10 0 0 0 0 1
pinseq=1
}
P 1000 1600 600 1600 1 0 0
{
T 1000 1600 5 10 0 0 0 0 1
pintype=pas
T 695 1645 5 10 1 1 0 0 1
pinnumber=2
T 1000 1600 5 10 0 0 0 0 1
pinseq=2
}
L 600 1600 400 1600 3 0 0 0 -1 -1
L 400 1600 300 1700 3 0 0 0 -1 -1
L 300 1700 200 1600 3 0 0 0 -1 -1
B 0 1600 100 300 3 0 0 0 -1 -1
Re: gEDA-user: PCB GIT: tracking inter-file moves
On Mon, Nov 16, 2009 at 09:23:48AM +, Ineiev wrote: > I've noticed that some functions moved yesterday > from src/hid/gtk/gtkhid-main.c to src/hid/gtkhid-gdk.c, > and learnt that GIT does not track the changes > when the content is moved between files (not by default). > > Is there any means to automate such tracking? Git stores entire files and trees. It doesn't record diffs at all. Anything finer grained than 'this file disappeared and this similar, same-named file appeared' is presented at the time the change is observed, not when it is committed. That's why all of the options like '-M' (detect renames) are on commands like 'log', 'show', etc. So what you'd really want as a feature is not 'tracking' but the ability for merge to track functions across files just like it currently can across renames. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Information on PCB
On Wed, Oct 21, 2009 at 05:06:35PM -0400, DJ Delorie wrote: > > I do try to go through the patch database on occasion. It's usually > what I do at code sprints. See, if I didn't live on the other side of the country from DJ I'd probably go to the code sprints and commit PCB patches too. Maybe we should use donated funds to fly us all to a central party^H^H^H^H^H location. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eliminate separate Vcc planes?
On Mon, Oct 19, 2009 at 08:35:33AM -0400, Bob Paddock wrote: > > To me running Vcc traces all over the board is the surest way to raise > inductance etc., and seems wrong to me. Plus in high current, low voltage designs (like FPGA core power) the tiny series resistance of even a plane can be a problem. I remember a design with a big honking FPGA and a POLA that was a few inches away due to board constraints. Someone in a meeting mentioned that the 20A 1.2V was sagging 50mV at the FPGA. Do the math and that's only 2.5mOhm drop but still meant the *plane* was dissipating a *watt*. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Barred solder mask in PCB
On Tue, Oct 13, 2009 at 01:10:40PM -0400, DJ Delorie wrote: > > Another option is to rebuild pcb without Xrender support, and see if > it's the rendering that's the problem. Or export to Postscript. IIRC > the gerbers use the dicer, so if the dicer is bad, the gerbers should > be bad also. They do, but they operate on the full board. The clue about being zoomed in suggests that it has to do with first cropping the poly to the visible area and then dicing it. That would also explain why the artifacts move around (as the visible objects, many of which seem to be placed on an angle, intersect at different offsets). -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Barred solder mask in PCB
On Tue, 13 Oct 2009 08:48:07 -0400, Ethan Swint wrote: > Fedora 11; PCB 20081128: On this board, the solder mask displays in bars > on my board, which has some components placed at arbitrary angles. When > the image is panned vertically, the bars stay relatively fixed, although > their height varies some. I've attached a small (50k) screen shot. Any > ideas as to the cause/solution? Given that it happens when zoomed but not at full size or in gerbers, it sounds like the dicer is having issues with subsections of your board. It would help if you could send us a copy. If you want to limit the distribution you could send it to geda-dev or just the PCB developers who work on polygons (me, Peter, DJ) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Turning off gerber Poly Fill for square pads
On Thu, Aug 20, 2009 at 05:56:56PM -0400, DJ Delorie wrote: > > > Dude! No one is blaming fault on PCB. It is obviously the other guys > > fault for not implementing all the R274X features properly. > > I think *most* of the fab houses we've heard of PCB being used with, > have had something we've had to work around in pcb. Gah! I wish > they'd get with the program and upgrade their software already. Is it worth adding features to gerbv to warn about known issues? Some kind of "fab DRC" that would warn about known brokenness in other tools. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Turning off gerber Poly Fill for square pads
On Thu, Aug 20, 2009 at 02:28:53PM -0700, Thomas Olson wrote: > > I am using pcb-20081128-4.1. > > All the devices that have square pads on pin 1 when exported > to gerber are using Polygon Fills G36-G37. > > How can I turn off Polygon Fills for square pads and > get back to using Rectangle Aperatures for square pads? I don't know anything about the root of your problem, but the easiest way to avoid a problem with square pads would be to edit the pads to make them 1 wider or longer so they are no longer square (of course they'll only be out of square by .1"). -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB - Disperse all elements don't show anything
On Sat, Aug 15, 2009 at 12:19:26AM +0200, Stefan Salewski wrote: > This is line 259... > > Element(0x00 "" "" "" 20 20 0 100 0x00) > ( > Pin(0 55 30 "1" 0x101) > Pin( 55 30 "2" 0x01) > > > Pin statement looks odd -- please verify that footprint. I noticed in his original mail that he was using m4 footprints. So this is probably the degenerate output of some confused m4 macro. To the OP: Try using 'use-files' to your 'project' file and rerunning gsch2pcb. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Would like to use geda tools to make .dxf file for pcb cnc milling.
On Fri, Aug 14, 2009 at 10:47:13PM +0200, Stefan Salewski wrote: > > CNC milling may be more or less related with this thread > > http://archives.seul.org/geda/user/May-2009/msg00259.html > > especially with the comments of Ben Jackson. BTW this is where I think you could easily spend a proportionally small amount of money to motivate open source work: If a CNC mill capable of making PCBs arrived on my doorstep you'd probably have a g-code exporter by the end of the next weekend. :) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: messed up ratsnest- help me understand
On Sat, Aug 01, 2009 at 03:07:43PM -0700, Josh Jordan wrote: > >Please open this file and suggest what might be going on. Your layer grouping is wrong. Your board has two layers but one of them is marked as both the top AND bottom of the board, causing pads to short to traces on both layers. If you fix the layer grouping (first thing in the settings menu) there's only one rat left and no shorts. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: how close to place components?
On Mon, Jul 27, 2009 at 02:04:13AM +0200, Stefan Salewski wrote: > > Good question. For my DSO board I have placed the 0805 parts very close, > silk outline nearly touch. For 0603 with hand assembly I place parts such that the silkscreen overlaps adjacent parts (if I need close spacing). -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: More robust support of multi-part symbols.
On Wed, Jul 08, 2009 at 09:20:54PM -0700, Steve Meier wrote: > Let alone, how at the layout level we can do pin swapping and back > annotation. I've thought about working on that, because I've dealt with that problem in almost every project I've done with geda/pcb. I'd love to know how the big boys handle it. Obviously you can't draw wires in gschem and then swap pins in pcb and expect the wires to be asthetically re-drawn in gschem. So do you only do it with busrippers and netname attributes? -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb wishes
On Tue, Jun 23, 2009 at 08:06:47AM +0200, Bert Timmerman wrote: > > 5) array command. Create an array of the selected objects, either > orthogonal or polar. Would be a handy feature for creating/editing > footprints. You could extend my distalign plugin to do simultaneous x/y distribution. Of course for footprints I just generate directly with John Luciani's library. And for someting more complex than that I used the perl module SVG::Parser to map Inkscape-placed objects into subcircuits in PCB: http://ad7gd.net/geda/gamepad-partial.jpg > Ad 4) Hmm, something like "AutoDRC" comes to mind. Could become a > constant pour of DRC dialog warnings and lead to frustrated newbies. It used to be worse to make a board and THEN drc. The interface was hopeless. At least with the fancy new one they can work through the problems if they make a bunch. Oh, and if you get yourself into trouble with vias you could try my "jostle" plugin which I wrote expressly for moving wires out of the way to place vias. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Investigating gEDA for commercial use
On Mon, Jun 15, 2009 at 11:21:36AM +0100, Chris Smith wrote: > > 3. use CadStar/Altium in a VMWare/VirtualBox session. My primary desktop is a Windows XP box. I started out using gschem and PCB with the Cygwin X server. It worked, but running them "directly" under Ubuntu on a VMWare Player is muuuch faster. VNC was significantly worse than both (at least for PCB, which is where I spend the bulk of my time). If you want to use VMWare, try http://www.easyvmx.com/ (free website that will make VMs) + VMWare Player (free download). -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Soldering supplies
On Wed, Jun 10, 2009 at 03:44:26PM -0400, Dave McGuire wrote: > >I've been soldering for 33 years now, no inexperienced hands > here. The Pb-free stuff I've tried has just plain sucked. I will > try the stuff Philipp mentioned though. If you've got a nice Metcal you may find that their Sn/Pb compatible tips suck for lead free. They make special (hotter) tips for lead free, which I find suck for leaded solder (can't seem to keep them wetted). -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Soldering supplies
On Wed, Jun 10, 2009 at 02:35:01PM -0400, John Luciani wrote: > On Wed, Jun 10, 2009 at 11:24 AM, Frank Miles wrote: > > Since DJ mentioned impedance level concerns associated with different kinds > > of flux: please note that the flux pen shown in John Luciani's generally > > excellent recommendations leads to seriously low electrical conductivity. > > It is definitely aggressive. You really need to clean the board often with hot > water and a brush. I also keep isopropyl alcohol and a brush on my bench. > > I have had a few circuits come back to life after a good cleaning. Now I > take a break every hour or so and clean. Also gives my eyes and back > a break ;) I'll second (third?) everything that was said. Every time I've tried to skimp on washing after using a Kester flux pen I've regretted it. I use hot water, dish soap and a toothbrush, followed by compressed air to speed the drying. Where I used to work we had a can of some kind of solvent that worked faster and dried faster but I never bought any myself. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pin numbering for wob package
On Wed, Jun 10, 2009 at 01:11:49PM +0200, Cyril Hrubis wrote: > The problem is pin numbering, All I'll say is that the 4 pin ones are the hardest. I made a board with several hundred+ pin packages where I made the symbols and footprints. And I made a fancy 4-pad footprint that would accept multiple sizes of SMT can oscillators. And I accidentally numbered the pins clockwise. At least the extra pad area helped me blue-wire the power... -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Can we fix the HTML stripping on this list?
In a multipart/alternative MIME document, the *last* alternative is
the one with "highest fidelity". That means that a typical message sent
in both text/plain and text/html will have the text/html second in the
multipart/alternative. The list software is filtering and replacing the
HTML with text/plain, generally producing a much worse plaintext than
the original mailer. The result is multipart/alternative with TWO
text/plain sections, the second ("preferred") one being the mangled HTML.
Personally I advocate going back to NOT mangling the HTML, and I will
go on reading the list in my text only mailer which prefers the text/plain
section. If we must keep mangling HTML, either remove it (if a text/plain
already exists) or properly order the sections so that the original
mailer's text/plain is preferred instead of the illegible output of the
list's filter.
--
Ben Jackson AD7GD
http://www.ben.com/
___
geda-user mailing list
geda-user@moria.seul.org
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Re: gEDA-user: PCB: Moving selected group of grid unintentionally
On Tue, Jun 09, 2009 at 01:55:46AM +0200, Stefan Salewski wrote: > > Maybe it would be better if snapping to pins and pads does not work when > multiple elements are moved. I don't like that idea. I've definitely used paste to repeatedly place groups (such as a short wire and a decoupling cap with via to gnd plane) where I rely on snapping to pins (because I carefully set the mark of the group on the end of the wire). If you want "back on grid" and aren't fussy about which way you move, you could probably make a binding with my distalign plugin. The default (unless you pass 'gridless') is to leave the affected objects on a grid. So a Align(X) on a single item will put it back on the X grid. So a key binding to Align(X); Align(Y) would put one selected item back on the grid. (Of course it would take a multi-selection and smash it all on top of each other...) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB build changes
On Tue, Jun 02, 2009 at 12:13:12AM +0100, Peter Clifton wrote: > wanted to see a more stable PCB release out the door before that > happened though - since there are many important bug fixes in PCB GIT > HEAD, which aren't in the last release. (Also, PCB GIT is pretty stable > code at the moment). You could push it to the repo as a branch so that other people still only had one public repo to deal with. Then after we tag and release from "master" you can merge it down. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: How to make a set of traces wider
On Mon, Jun 01, 2009 at 09:52:54PM +0200, Stefan Salewski wrote: > I have drawn some copper areas for my DC/DC-converters with traces 1 mm > width with 1 mm grid, so the traces touch, but do not really overlap. > Now I want to ensure that there is no minimal gap in the gerbers. I think you should be okay. Polygons are sliced by the "dicer" which cuts them vertically through each hole until the results are outlines with no inner cutouts. The gerber export uses that dicer, so any gerber with a polygon already contains copper areas that exactly touch but don't overlap. You can see it if you look at a gerber with a plane with holes (eg from pins) in 'outline' mode. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: ??Error message PCB??
On Sat, May 23, 2009 at 08:42:48AM +0200, Ernst van Spronsen wrote: > >Ok, How do I disable the M4 libraries? At least for this project? > Thanks. In your project file add: use-files skip-m4 -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Parts!
On Thu, May 14, 2009 at 03:34:31PM -0400, DJ Delorie wrote: > > How do people manage their parts inventories, so they know what > they've got? I have some flat text files of interesting stuff (like microcontrollers and voltage regulators) and things I have vast quantities of (reels of 0603 caps) and then I just try to keep "kits" on hand so that I know I have any value of resistor I want (currently in through-hole and 0805). Connectors I'm really bad about. I tend to go through my collection of connectors every time I need something. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
On Thu, May 14, 2009 at 08:34:17PM +0200, Stefan Salewski wrote: > > http://groups.csail.mit.edu/drl/wiki/index.php/Visolate:_Voronoi_Toolpaths_for_PCB_Mechanical_Etch Voronoi diagrams are a related problem, but I think the correct way to approach it is: 1. Produce the polygon (with holes) of all of the *non copper* areas of the board. PCB can do this easily with existing polygon primitives. 2. Find the "straight skeleton" of the resulting polygon. I believe if the orientation of the PCB polygons was cleared up you could do this with the CGAL library. Or it could be reimplemented for our polygon structure. Skeletonization can be done with a raster method, but I think this would produce suboptimal toolpaths if the intent were really to output Gcode. 3. Delete all of the "stubs" in the resulting skeleton. Holes in the original non-copper polygon (which represent islands of copper) will create loops in the skeleton, which we want to keep. "Peninsulas" of non copper will produce stubs (which do not serve to actually isolate any region -- imagine a P shape simplified to an O). If you use a library like CGAL these should be removed. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: mimedel is annoying (was: collapsing or non-collapsing balls, how can i tell?)
On Thu, May 14, 2009 at 12:00:47PM -0400, John Luciani wrote: > >There is a new version of the naming convention, "IPC-7351B Naming ... >(* jcl *) >-- >You can't create open hardware with closed EDA tools. >[1]http://www.luciani.org > > References > >1. http://www.luciani.org/ I notice 'X-Content-Filtered-By: Mailman/MimeDel 2.1.9' in the headers... Lately I've been having trouble reading John's mail because of odd formatting. It's especially hard to tell which text is his in replies. It turns out that the list seems to be taking his alternative html + plain email and turning it into plain + plain with one oddly formatted by mimedel. My mailer seems to pick the ugly one, unfortunately. Looking at one random old message from John from January I don't see this problem. Is this a switch we can flip back? Or can we make mimedel at least prefer the plaintext as formatted by the original mailer? -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
On Wed, May 13, 2009 at 04:16:26PM +0200, Stefan Salewski wrote: > Someone asked how one can build PCB boards like this: > > http://www.mikrocontroller.net/topic/137821#new > > (Click on the picture too enlarge) > > This layout may have advantages if PCB is made mechanical, i.e. by > milling machines. > > So I asked myself is current PCB can do it -- I guess not, but I may be > wrong. Sure, you just route the board as usual, and in a post-processing step you retain the same net topology but you achieve it by cutting up a plane. PCB would need a new exporter, and you wouldn't have direct control over the output (you'd probably end up drawing some spurious traces to steer it), but it could be done. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On Mon, May 11, 2009 at 01:52:15PM -0700, Eric Brombaugh wrote: > > 1) A task that requires a lot of smart people to complete must suffer > from a lack of adequate tools. > > 2) A task that can be completed with inadequate tools can't be very complex. I don't know that you can decompose my position like that. A task that requires a lot of smart people to complete would take fewer people if the tools were better. > Coming from a background as a wireless systems engineer as well as a > chip designer, I'm here to tell you that there's nothing simple about > the chips I've worked on: the Wifi chipsets I was doing 6 years ago were > complex enough that no one person understood _everything_ that was > happening in them. I would distinguish between "necessary complexity" and "unnecessary complexity". I can write a C program without understanding the instruction set or register architecture of the processor I'm on. Modern compilers will do a very good job of insulating me from the performance implications. But I bet your Wifi chip had guys who were great at DSP and who modelled the whole system in Simulink. Then they had to communicate those ideas to another team who understood the inner workings of the chip process you were working in and who then had to translate the whole system into VHDL or Verilog. > The only way these things are at all possible is with a wide variation > in levels of abstraction. They guy designing the transistors doesn't > know about the circuits they go into, while the architect working on the > memory management can't be bothered with the ESD structures of the I/O > pads. That's all true. I just don't think it goes far enough. I don't know if that's because it's a Hard Problem or if it's because engineers have expectations that are too low. As a software engineer I came to the party with much higher expectations. I would compare the current state of FPGA development tools with my early 8-bit computer experience. On my Commodore 64 I cared about every memory location on the system. I wrote anything remotely important by hand in assembly. Writing Verilog is at the abstraction level of approximately a macro assembler. At the high end it might reach up into the level of BASIC. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On Mon, May 11, 2009 at 11:17:32AM -0700, Eric Brombaugh wrote: > When doing an FPGA design, I can as an individual manage a project that > completely fills the largest FPGA available. Working on a large > commercial IC development project requires the skills of dozens if not > hundreds of experienced engineers. Well, that's basically my point. Working on a large IC requires a huge team of people. I live right by Intel, so I see how many people they have swallowed up to do chip design. My complaint is that the complexities of designing chips or FPGAs is very poorly abstracted as compared to software at large. The only reason it's possible to execute those designs at all is that on an absolute scale they're fairly simple. That's no slight on the people doing the work -- it's just a reflection of how ineffective the tools are. You describe the ASIC tools as being much more sophisticated than the FPGA tools. That's true, but it's only because the ASIC problem is even harder. The better tools don't make it any easier than FPGA work, they just make it possible to design such complex chips at all. > As someone with experience on both sides, what improvements would you > like to see? I would like to be able to express the essence of what I need to do, such as an arithmetic operation, without having to understand how it should be pipelined, how wide the intermediate results need to be, how it should map to the facilities of the FPGA (or hard macros or etc), etc. I would like to be able to take that design and target FPGAs from different families or vendors without having to reevaluate the design tradeoffs. Even if I *did* have to make the choices manually (eg where to register intermediate values), I'd like to control those aspects independently from the core logic, rather than having to mix it in. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On Mon, May 11, 2009 at 09:56:05AM -0700, Joerg wrote: > > C++ for hardware design? Altera has a tool called C2H which works with its NIOS II soft core. You write code targeted at the soft core and then use the C2H tool to convert key inner loops to dma-driven logic blocks. I've never used it, but it sounds interesting. Frankly, having come to FPGAs from a long history of softare development, the FPGA guys are working with stone age tools right now. The only reason FPGA and ASIC projects get done at all is that their scope is vastly simpler than a typical software project. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On Thu, May 07, 2009 at 09:02:57PM +, Frank Bergmann wrote: > > Look in the tracker - there are patches. Not all for raising up newbie-friedly > level but patches. For example: > Kai-Martin reported a bug (#1988982) and Bert did a patch (#2686963). Ready > for > applying but - nothing happend. Mmh, need a "patch integrator" ... Having watched the 'git format-patch + git send-email + git am' workflow in action, I think it's the best way I've seen for people without commit access to channel their work through a committer. Everyone can see and discuss the patch, and if people like it a committer can apply it with almost zero effort. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: solder jumpers
On Sun, May 03, 2009 at 02:44:48PM -0400, DJ Delorie wrote: > > I added something like that to my page... > > http://www.delorie.com/pcb/solderjumpers.html > > That one *can* be done as an element :-) Your solder jumpers are starting to look like PCB inductors: http://lea.hamradio.si/~s53mv/zifssb/sband.html -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: getting along with git
On Wed, Apr 29, 2009 at 11:18:14PM +, Kai-Martin Knaak wrote: > Just did one of my irregular updates of my local versions of geda and pcb > from git. For some reason "git pull" chokes on some misconfiguration. I > ended up recloning (again) and did a successful make. Not sure what happened, but you can recover with 'git reset --hard origin/before_pours'. You can even just do 'git fetch; git reset --hard origin/before_pours' to skip all merging/rebasing. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Change text font size in PCB
On Wed, Apr 29, 2009 at 11:45:47PM +0200, Stefan Salewski wrote: > > Of course: Move mousepointer over the text and press key "S". Unfortunately line thickness is the board minwidth. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Contributing components to gEDA
On Fri, Apr 24, 2009 at 03:10:02PM +0200, Stefan Salewski wrote: > On Thu, 2009-04-23 at 18:45 -0700, jeffrey antony wrote: > > > Is there any one who has done any circuit board using at90usb162? I missed that question in the original. I made a partial keyboard for playing TF2: http://ad7gd.net/geda/gamepad-partial.jpg http://ad7gd.net/geda/gamepad-labels.jpg I used the LUFA library which made it very easy to get the firmware working. The main thing I'd change is to use real pullups instead of relying on the internal pullups. The capacitance of multiple switches on a column cause the internal pullups to take several clocks to rise. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: SystemPerl "Integer overflow in
On Sun, Apr 19, 2009 at 11:23:07PM -0700, John Alfredo wrote: > >I'm installing SystemPerl-1.311 (SystemC perl libs), and when I run >the "make tests" it complains on 6 of the tests with the message >"Integer overflow in hexadecimal number at ...". Has anybody else >run into this? Is this a problem? Perl uses host integer width. Those tests may not fail on a 64 bit perl. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem, alert if symbols in schematic have changed?
On Sun, Apr 12, 2009 at 02:02:15PM -0700, Yamazaki R2 wrote: > Yes gschem just replaces the symbol, no warning or anything. Maybe gschem needs version control integration. A use of a symbol would automatically check a copy into the repository for the current project. Symbols would never come from global sources, only embedded and local directories. I know some people use a similar workflow already, but maybe we should automate it to encourage people. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem building gEDA from git repository
On Fri, Apr 10, 2009 at 10:15:45PM +0100, Chris Smith wrote: > > I'm having problems building gEDA from the git repository, following the > instructions here: http://www.gpleda.org/developer.html. I'm getting > the following error when running 'make install': You need to start by running 'autogen.sh'. It makes configure and Makefile.in (from Makefile.am). Yet another level of automake indirection! > configure: creating ./config.status Maybe someone committed a configure but not a Makefile.in? It should probably be removed from the repo if it exists. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FT232R
On Wed, Apr 08, 2009 at 07:17:06PM -0500, Bill Gatliff wrote: > > Point is, I can't refute either a 100% success or stay-away-at-all-costs > claim for either device. USB-powered devices in general demand good > decoupling and filtering on VCC, and maybe FTDI-based products that fail > to do that will cause problems. But so would just about everything > else. YMMV. My main reservation about FTDI is that outside the "USB serial" mode the devices are very focused on write-only behavior. They don't really give you good tools for doing bulk reads. So if you want to pump data INTO a system (eg the common FTDI based JTAG cable) FTDI is a fine choice. If you want to get bulk data OUT it's another thing entirely. In fact, without the Linux drivers I think my project would have failed (turns out the windows drivers actually start a task which periodically flushes the input even if you don't consume it -- the more debug prints I added the worse things got). These days I'd see if I could get a USB AVR to do what I needed. I just used one to make a gamepad (keyboard device) and it was great with the LUFA library. If I needed bigger guns I'd probably use one of the Cypress micros (I think the GNU radio guys use one of those to pump data to/from a Cyclone FPGA). -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FT232R
On Wed, Apr 08, 2009 at 02:12:10PM -0700, William Estrada wrote:
> Hi group,
>
> Does anyone have a sym file for the FT232RL?
Attached. I used this successfully in a design.
--
Ben Jackson AD7GD
http://www.ben.com/
v 20061020 1
B 300 600 1500 3800 3 0 0 0 0 0 0 -1 -1 -1 -1 -1
T 300 550 5 10 1 1 0 2 1
refdes=U?
T 300 350 5 10 1 1 0 2 1
device=FT232RL
T 200 550 5 10 0 0 0 8 1
copyright=2007 Ben Jackson
T 200 350 5 10 0 0 0 8 1
author=Ben Jackson
T 200 150 5 10 0 0 0 8 1
uselicense=unlimited
T 200 -50 5 10 0 0 0 8 1
distlicense=GPL
T 200 -250 5 10 0 0 0 8 1
description=FTDI FT232R USB UART
T 200 -450 5 10 0 0 0 8 1
footprint=SSOP28.fp
P 1800 4200 2100 4200 1 0 1
{
T 1750 4200 5 8 1 1 0 7 1
pinlabel=TXD
T 1850 4225 5 8 1 1 0 0 1
pinnumber=1
T 1850 4225 5 8 0 1 0 0 1
pinseq=17
}
P 1800 4000 2100 4000 1 0 1
{
T 1750 4000 5 8 1 1 0 7 1
pinlabel=RXD
T 1850 4025 5 8 1 1 0 0 1
pinnumber=5
T 1850 4025 5 8 0 1 0 0 1
pinseq=18
}
P 1800 3800 2100 3800 1 0 1
{
T 1750 3800 5 8 1 1 0 7 1
pinlabel=RTS#
T 1850 3825 5 8 1 1 0 0 1
pinnumber=3
T 1850 3825 5 8 0 1 0 0 1
pinseq=19
}
P 1800 3600 2100 3600 1 0 1
{
T 1750 3600 5 8 1 1 0 7 1
pinlabel=CTS#
T 1850 3625 5 8 1 1 0 0 1
pinnumber=11
T 1850 3625 5 8 0 1 0 0 1
pinseq=20
}
P 1800 3400 2100 3400 1 0 1
{
T 1750 3400 5 8 1 1 0 7 1
pinlabel=DTR#
T 1850 3425 5 8 1 1 0 0 1
pinnumber=2
T 1850 3425 5 8 0 1 0 0 1
pinseq=21
}
P 1800 3200 2100 3200 1 0 1
{
T 1750 3200 5 8 1 1 0 7 1
pinlabel=DSR#
T 1850 3225 5 8 1 1 0 0 1
pinnumber=9
T 1850 3225 5 8 0 1 0 0 1
pinseq=22
}
P 1800 3000 2100 3000 1 0 1
{
T 1750 3000 5 8 1 1 0 7 1
pinlabel=DCD#
T 1850 3025 5 8 1 1 0 0 1
pinnumber=10
T 1850 3025 5 8 0 1 0 0 1
pinseq=23
}
P 1800 2800 2100 2800 1 0 1
{
T 1750 2800 5 8 1 1 0 7 1
pinlabel=RI#
T 1850 2825 5 8 1 1 0 0 1
pinnumber=6
T 1850 2825 5 8 0 1 0 0 1
pinseq=24
}
P 1800 2400 2100 2400 1 0 1
{
T 1750 2400 5 8 1 1 0 7 1
pinlabel=CBUS0
T 1850 2425 5 8 1 1 0 0 1
pinnumber=23
T 1850 2425 5 8 0 1 0 0 1
pinseq=25
}
P 1800 2200 2100 2200 1 0 1
{
T 1750 2200 5 8 1 1 0 7 1
pinlabel=CBUS1
T 1850 2225 5 8 1 1 0 0 1
pinnumber=22
T 1850 2225 5 8 0 1 0 0 1
pinseq=26
}
P 1800 2000 2100 2000 1 0 1
{
T 1750 2000 5 8 1 1 0 7 1
pinlabel=CBUS2
T 1850 2025 5 8 1 1 0 0 1
pinnumber=13
T 1850 2025 5 8 0 1 0 0 1
pinseq=27
}
P 1800 1800 2100 1800 1 0 1
{
T 1750 1800 5 8 1 1 0 7 1
pinlabel=CBUS3
T 1850 1825 5 8 1 1 0 0 1
pinnumber=14
T 1850 1825 5 8 0 1 0 0 1
pinseq=28
}
P 1800 1600 2100 1600 1 0 1
{
T 1750 1600 5 8 1 1 0 7 1
pinlabel=CBUS4
T 1850 1625 5 8 1 1 0 0 1
pinnumber=12
T 1850 1625 5 8 0 1 0 0 1
pinseq=29
}
P 300 4200 0 4200 1 0 1
{
T 350 4200 5 8 1 1 0 1 1
pinlabel=VCCIO
T 250 4225 5 8 1 1 0 6 1
pinnumber=4
T 250 4225 5 8 0 1 0 6 1
pinseq=9
}
P 300 4000 0 4000 1 0 1
{
T 350 4000 5 8 1 1 0 1 1
pinlabel=VCC
T 250 4025 5 8 1 1 0 6 1
pinnumber=20
T 250 4025 5 8 0 1 0 6 1
pinseq=10
}
P 300 3600 0 3600 1 0 1
{
T 350 3600 5 8 1 1 0 1 1
pinlabel=USBDM
T 250 3625 5 8 1 1 0 6 1
pinnumber=16
T 250 3625 5 8 0 1 0 6 1
pinseq=11
}
P 300 3400 0 3400 1 0 1
{
T 350 3400 5 8 1 1 0 1 1
pinlabel=USBDP
T 250 3425 5 8 1 1 0 6 1
pinnumber=15
T 250 3425 5 8 0 1 0 6 1
pinseq=12
}
P 300 3000 0 3000 1 0 1
{
T 350 3000 5 8 1 1 0 1 1
pinlabel=RESET#
T 250 3025 5 8 1 1 0 6 1
pinnumber=19
T 250 3025 5 8 0 1 0 6 1
pinseq=13
}
P 300 2600 0 2600 1 0 1
{
T 350 2600 5 8 1 1 0 1 1
pinlabel=OSCI
T 250 2625 5 8 1 1 0 6 1
pinnumber=27
T 250 2625 5 8 0 1 0 6 1
pinseq=14
}
P 300 2400 0 2400 1 0 1
{
T 350 2400 5 8 1 1 0 1 1
pinlabel=OSCO
T 250 2425 5 8 1 1 0 6 1
pinnumber=28
T 250 2425 5 8 0 1 0 6 1
pinseq=15
}
P 300 2000 0 2000 1 0 1
{
T 350 2000 5 8 1 1 0 1 1
pinlabel=3V3OUT
T 250 2025 5 8 1 1 0 6 1
pinnumber=17
T 250 2025 5 8 0 1 0 6 1
pinseq=16
}
P 300 1600 0 1600 1 0 1
{
T 350 1600 5 8 1 1 0 1 1
pinlabel=AGND
T 250 1625 5 8 1 1 0 6 1
pinnumber=25
T 250 1625 5 8 0 1 0 6 1
pinseq=30
}
P 300 1400 0 1400 1 0 1
{
T 350 1400 5 8 1 1 0 1 1
pinlabel=GND
T 250 1425 5 8 1 1 0 6 1
pinnumber=7
T 250 1425 5 8 0 1 0 6 1
pinseq=31
}
P 300 1200 0 1200 1 0 1
{
T 350 1200 5 8 1 1 0 1 1
pinlabel=GND
T 250 1225 5 8 1 1 0 6 1
pinnumber=18
T 250 1225 5 8 0 1 0 6 1
pinseq=32
}
P 300 1000 0 1000 1 0 1
{
T 350 1000 5 8 1 1 0 1 1
pinlabel=GND
T 250 1025 5 8 1 1 0 6 1
pinnumber=21
T 250 1025 5 8 0 1 0 6 1
pinseq=33
}
P 300 800 0 800 1 0 1
{
T 350 800 5 8 1 1 0 1 1
pinlabel=TEST
T 250 825 5 8 1 1 0 6 1
pinnumber=26
T 250 825 5 8 0 1 0 6 1
pinseq=34
}
___
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Re: gEDA-user: terminators
On Mon, Apr 06, 2009 at 10:03:36PM -0400, DJ Delorie wrote: > > I tried adding serpentines but there isn't enough room to add more Excellent news for PCB, though. If DJ has trouble laying out serpentines or trombones, a plugin is sure to follow. ;-) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Sun, Apr 05, 2009 at 01:19:32AM -0400, DJ Delorie wrote: > > Hmmm... maybe I'm going about this the wrong way. Would it make more > sense to get rid of the LA on that side, move the sdram chip as close > as I can to the FPGA, and use something like chipscope That's what I'd do. At the sort of volumes you and I work with it's a lot cheaper to use a FPGA big enough to include chipscope/signaltap even in the full design than to allow for an LA hookup. If things are going wrong due to external timing or signal issues the LA won't help anyway -- you'll need a good scope. > signals? I've got both SPI and addr/data connections to the MCU on > the other side to get the data out. Why not just use chipscope? I thought you could get that for free these days (although admittedly I use Altera mainly for free Signaltap myself). > > Here's another idea. Instead of the LA, use a scope > > My scope is nowhere near fast enough for that. The LA is 500 ms/s or > can be externally clocked up to 200 mhz. The scope is only 32 ms/s. Hard to believe the LA expects signals that fast without active probes. The probes I've seen have the .1" type headers on the LA end, but the far end have active probes and other connectors (typically mictor) and cost $1500/set. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: outline layer
On Sat, Apr 04, 2009 at 06:50:57PM -0400, gene glick wrote: > > > gamepad.outline.gbr Outline (10 mil line, board edge is > > on-center) > > > And they come close? I'm asking because I have a connector that hangs > over the edge of the board. If the fab house cuts the board too large, > the connector won't go fit. That particular fab (which isn't the greatest!) got those dimensions right. I just measured a sample board and it is -0.003 in one direction and -0.010 in the other. You probably can't rely on milling operations beyond about 0.010" anyway. Something else to consider is panelization: If you are ordering a standard panel size and you want to fill it you will need to know how wide their cutting tool is (unless they just score it for you, or you are a DIY nut like DJ). > while on this subject, how close to the board edge can planes go? 5 > mil? 10 mil? more? Ask your vendor. I've used 0.025" before at a place with 8/8 rules. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: outline layer
On Sat, Apr 04, 2009 at 05:50:24PM -0400, gene glick wrote: > When drawing the outline for a pcb, does the fab house cut right on the > line, inside the line, or outside the line? I always submit a file like this with my gerbers (note outline comment): All .gbr files are Gerber/RS-274X The .cnc is an Excellon Drill File (no zeroes suppressed) All holes plated. Board is 4" x 5.5". I want 2 "standard service" 4x5.5 panels, with soldermask. readme.txtThis file gamepad.back.gbr Back (solder side) copper layer gamepad.backmask.gbr Back (solder side) soldermask gamepad.front.gbr Front (component side) copper layer gamepad.frontmask.gbr Front (component side) soldermask gamepad.plated-drill.cnc Drill file gamepad.outline.gbr Outline (10 mil line, board edge is on-center) -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Sat, Apr 04, 2009 at 03:29:16PM -0400, DJ Delorie wrote: > > The right half of U2, and U2, run at 133MHz. The longest trace is the > CLK line, at just over 3 inches, the shortest is just under an inch. > However, most of those lines are brought out to logic analyzer > connectors, which may add up to another 1.8 inches (DQ11, for example, > has a combined length of 3.9 inches). I think you'd be fine without the stubs going to the header. Even with the stubs your SDRAM will probably work but there will be terrible EMI. I chased down an EMI problem on a board with ONE stub at 125MHz (due to leaving a clock testpoint enabled). You have 20+ stubs. Ideally you'd put the LA connector in the middle of the bus. Just pick a higher density connector. AMP MICTOR connectors are a popular choice. > I'm thinking I have enough space to put in some series terminator > packs (8x 0402 SMT) but where and how big? Does the FPGA you're using have controllable drive strength? That alone is probably enough for your design. Otherwise put the series resistors on the driving side. The value is a bit of a black art, but 27..51R is in the right ballpark. To measure their effectiveness beyond pass/fail you'd need a very fast (6G+) scope. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: rat width
On Thu, Apr 02, 2009 at 05:56:40PM -0500, Mark Rages wrote: > I am working on a design with a lot of small parts and pcb's default > rat width is too wide to see what I'm doing. I don't see a setting > for this. Where should I look? Newer versions will draw the rat lines with partial transparency, which is a big help as well. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Orange pins in PCB
On Wed, Apr 01, 2009 at 03:57:59PM -0400, Rob Butts wrote: > >I have to make some traces on a board .050". In doing this it caused >two pins on a connector to turn orange designating a short. I ripped >up all routes and re-optimized all rats but the two pins on the >connector are still orange. How do I get rid of the orange pins? There was a bug a long time ago where the orange pins would not get reset. If you are using a version more than a year old you should upgrade. If not, you may have a small bit of trace hidden under the pin. Turn off the "pins layer" to check. These happen when your pin is slightly off grid and your line settings cause the tiny makeup angle to be at the end of the line. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
