Re: gEDA-user: Soldering minute smt
On 01/27/2011 08:47 AM, Rob Butts wrote: I'm trying to solder a 10 pin MSOP chip to a home made circuit board. The pitch of this chip is just 0.5 mm. We tried using the slightests of dabs of solder across the pins and then used a heat gun the melt the solder but now I have a chip soldered down with two five pin solder blobs on each side. My next step is to use solder wick to try and wick up the excess but I wanted to see if there is a better way of doing this first. If you've already got blobs wick off excess and use liberal amounts of flux and reflow - this allows the surface tension of the molten solder to separate at the pin/pad breaks and helps prevent bridging. I've gotten pretty good with the 10-pin MSOPs by hand: http://members.cox.net/ebrombaugh1/synth/audiodac/index.html My technique is to apply _no_ solder, plenty of flux gel and just allow the existing solder plating on the PCB to reflow. For the board fab I use this is sufficient to provide a good meniscus and the IC is well attached. I also have a very fine-point iron. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: icarus, fork, and recursive tasks
On 11/08/2010 02:00 PM, DJ Delorie wrote: The RX is Renesas's latest chip offering, and they're trying to make it obsolete a wide range of other chips. So far so good. Interesting. I'm looking for an inexpensive embedded processor with SDRAM and moderate DSP capability. This may bear closer inspection. What size of 3AN are you using on it? Smallest - the XS3S50AN. The 3AN is only available in one configuration per package size That's unfortunate. I've been getting some good mileage out of the XC3S200A-VQ100 parts. Too bad Xilinx hasn't made that size available in the 3AN family. I suppose that you chose the AN variant because you wanted to avoid dealing with the configuration memory. Eric (hoping this isn't too far OT yet) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: icarus, fork, and recursive tasks
On 11/08/2010 12:32 PM, DJ Delorie wrote: Whatcha making? Looks like some sort of FPGA-based video stuff... It is FPGA-based video stuff. http://www.delorie.com/electronics/rx/os-board.html Sweet little board - lots of useful I/O. RX62N processor looks pretty well equipped too. What size of 3AN are you using on it? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: icarus, fork, and recursive tasks
On 11/08/2010 11:56 AM, DJ Delorie wrote: Just for giggles I ran that through my copy of Modelsim. Try the whole thing: http://www.delorie.com/tmp/play2sim.tar.gz http://www.delorie.com/tmp/play2sim.png That worked too. Whatcha making? Looks like some sort of FPGA-based video stuff... Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: icarus, fork, and recursive tasks
On 11/08/2010 11:02 AM, DJ Delorie wrote: $ iverilog -o sim -Wall -g1 tasks.v tasks.v:10: syntax error sh: line 1: 13425 Done/usr/lib/ivl/ivlpp -L -F"/tmp/ivrlg241f26ea8" -f"/tmp/ivrlg41f26ea8" -p"/tmp/ivrli41f26ea8" 13426 Segmentation fault (core dumped) | /usr/lib/ivl/ivl -C"/tmp/ivrlh41f26ea8" -C"/usr/lib/ivl/vvp.conf" -- - `timescale 1ns / 1ps module task_test (); endmodule // task_test Just for giggles I ran that through my copy of Modelsim. http://imagebin.org/122374 Seems to work fine there. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Photo mode to the rescue...
On 09/06/2010 06:51 PM, DJ Delorie wrote: I needed an official photo of a board for a presentation, but the boards aren't back from assembly yet. So I used a photo-mode export of the PCB, and a photograph of a home-etched prototype, and 1-2 hours of GIMP work... http://www.delorie.com/pcb/tmp/photo-mode-plus-plus.html Whenever I post pix from photo mode I always get questions about what tool I used to do them. Surprising that none of the big pro tools out there provide that. Who says OSS apps always follow the lead of the proprietary SW world? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/digital partitioning
On 07/22/2010 09:57 AM, Steven Michalske wrote: Just make sure that if you've got high-speed digital lines that cross into the 'cubicles' they have gnd plane underneath them where they enter - don't let fast signals cross the cuts because then the return currents have to take a different path and that will screw up the signal integrity. The question is "how fast?". Because you loops may not even matter. But just remember to keep them small. :-) Good point - that's left as an exercise for the engineer. In my case these were 16-bit DAC data buses running at 250MHz, so a few extra inches in the return path could cause some noticeable distortion in the higher harmonics and splatter the edges. OTOH, this board has a 5-bit async attenuator control bus that pops about once an hour and we didn't give those any priority. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/digital partitioning
On 07/22/2010 09:37 AM, DJ Delorie wrote: One idea to consider is to start with a solid plane, and cut slots around the sensitive analog parts, like big C shaped moats, squares open on one side. You retain the "big ground plane" conductivity, but you prevent stray currents from using your analog area as a short-cut. Each analog "chunk" can have it's own moat this way, too. If they're near the edge, just cut a thin slot from the edge in. I've used this approach on some relatively high-speed digital/analog/RF boards. Seems to work pretty well. Just make sure that if you've got high-speed digital lines that cross into the 'cubicles' they have gnd plane underneath them where they enter - don't let fast signals cross the cuts because then the return currents have to take a different path and that will screw up the signal integrity. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Strange behavior from Icarus Verilog
On 07/01/2010 06:10 AM, Patrick Doyle wrote:
When I run the following code in Icarus Verilog:
`define Tnom 140e-9
`define Rele 2e3
`define Cele 0.3e-6
`define Vdd1p8 1.7
`define DrvIstep 1e-6
`define ADCScale (1024/`Vdd1p8*`DrvIstep)
module check_this();
integer pulse_dur = 15;
integer delta3 = 1;
integer drvw1 = -20;
initial begin
$display("%f,%f,%f,%0d",
drvw1*(`Rele - (pulse_dur-delta3)*216*`Tnom/`Cele)*`ADCScale,
-drvw1*(`Rele - (pulse_dur-delta3)*216*`Tnom/`Cele)*`ADCScale,
-1.0*drvw1*(`Rele - (pulse_dur-delta3)*216*`Tnom/`Cele)*`ADCScale,
$rtoi(-drvw1*(`Rele - (pulse_dur-delta3)*216*`Tnom/`Cele)*`ADCScale));
$finish;
end
endmodule
get the following output:
-24.094118, 0.00, 24.094118, 7
I think that the 4 numbers should be identical. It is possible that
there is some funny conversion rule, or undefined behavior in the
Verilog spec that might result in the second output being zero, but I
don't understand why I get 24 for the 1st& 3rd output and 7 for the
final output (which is much closer to what I would expect).
So I'm asking for a couple of favors...
1) Can somebody else try this code and see if you get the same sort of results?
I compile and run it with:
$ iverilog -Wall -I.. -y.. -o check_this.vvp check_this.v
$ vvp check_this.vvp
$ iverilog -V
vvp.tgt: Icarus Verilog VVP Code Generator 0.10.0 (devel)
(s20090923-223-g9fbb12d)
$ vvp -V
Icarus Verilog runtime version 0.10.0 (devel) (s20090923-223-g9fbb12d)
I'm running on a Mac(book).
2) If this behavior is to be expected, could somebody explain why?
3) If it's not expected, I'd be glad to take a crack at figuring out
what went wrong where, or at least to post this to the buglist. I'd
like to be able to do more to give back, so I'm willing to poke
around.
I ran this through Modelsim LE and got the following result:
# -7.093308,7.093308,7.093308,7
Running it through my copy of Icarus 0.9.2 gives the same answer you got
above, so I'm guessing that there's something odd going on with the way
Icarus is parsing complex mathematical expressions.
Eric
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Re: gEDA-user: nRF24L01+ symbol
On 05/03/2010 05:29 PM, George M. Gallant wrote: Dave, Attached is a symbol for the NRF24L01. I have not used it because I lack the tools/skills to populate the QFN package and the assembled modules are sufficient for my needs. I've had pretty good luck hand soldering leadless ceramic oscillators whose pins look a lot like those on QFNs. Make sure the pads extend far enough beyond the body to allow good contact with the iron, use lots of flux and it should be fine. Main problem would be soldering to the central ground/thermal pad that most QFNs have though. That might require reflow, but a hotplate might work OK for that. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Audio processing
On 04/14/2010 03:00 PM, Miguel Sánchez de León Peque wrote: Hi all, Does anybody know something about chord processing? What I would like to do is to know which notes are played in a chord, realtime... Don't know if this is even possible. OT for this list, but... Yes, it's possible. Difficult though - the sort of thing that folks get many $$$ for in the commercial software world. For example: http://www.celemony.com/cms/index.php?id=products_editor Suggest you ask this question on another list, for instance http://music.columbia.edu/mailman/listinfo/music-dsp Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: complete project sample?
On Apr 11, 2010, at 2:59 AM, Stephan Boettcher wrote: > John Luciani writes: > >> On Sat, Apr 10, 2010 at 6:58 PM, DJ Delorie wrote: >>> I can think of a few uses for your USB GPIO pod!-Patrick >>> >>> I use it mostly for testing out new components. I have added a >>> micro-sd module for it, and most recently it's wired up to a new >>> ethernet chip from micrel. >> >> Do you have uSD code working? I have tried a couple >> of different cards and have had no luck getting them working on >> the SPI port. I looked at the timing of the CS, MOSI and SCK. >> All look good but I don't get a response on the MISO line. >> I have looked at the spec and I believe I am sending the proper >> command bytes. Any info would be appreciated. > > microSD are not required to support the SPI protocol. Do they usually > do? What brands? Interesting. I've tried a half-dozen different brands and haven't had any trouble with SPI support. Sandisk, Kingston, PQI, no-name from Deal Extreme, etc. If you're interested though, it seems that brand-name doesn't mean much. Even some of the big sellers are often re-branded from whatever's cheapest in China this week: http://www.bunniestudios.com/blog/?page_id=1022 Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: complete project sample?
On Apr 10, 2010, at 8:11 PM, John Luciani wrote: > On Sat, Apr 10, 2010 at 9:48 PM, DJ Delorie wrote: >> >> Yes, I got microsd working. Next time, though, I'm putting a P-MOSFET >> on the power line so I can software power cycle it. >> http://www.delorie.com/tmp/microsd.c > > Excellent. Thanks!!! I will give this a try tomorrow. > > I made the same omission of P-MOSFET omission on my board too ;) I've got a couple of projects that use uSD, both ARM and dsPIC and never needed power cycling. I'm using someone else's libraries for the SD card though. FWIW, I only read the card after power-up and don't hot-swap them so that might be a big factor. http://members.cox.net/ebrombaugh1/synth/armfpga/index.html http://members.cox.net/ebrombaugh1/synth/dsPIC_fpga/index.html Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Magnetic bike operation
On 03/27/2010 01:32 PM, Stefan Salewski wrote: On Sat, 2010-03-27 at 16:28 -0400, Rob Butts wrote: I'm having a debate with an ee friend about how the magnetic resistance works on an excersice bike. May be something like http://de.wikipedia.org/wiki/Wirbelstrombremse http://en.wikipedia.org/wiki/Eddy_current_brake Yes, this. I've had one apart before - they use permanent magnets and a thin aluminum rotor that's usually geared up from the pedals so it spins pretty fast. To adjust the brake tension a pair of laminated iron poles are brought close to the spinning rotor - the narrower the gap between them, the more resistance. Note that the pole pieces don't actually touch the rotor (except in an old bike I had where the rotor warped from resistive heating - then I got a lot of aluminum shavings everywhere). Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for my first fab shop.
On 03/08/2010 12:28 PM, Kai-Martin Knaak wrote: ---<(kaimartin)>---(who gets his prototypes done by http://basista.com ) Odd - that resolves to a furniture store for me. Diversification! Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for my first fab shop.
On 03/08/2010 11:30 AM, Jim wrote: Are there any fab shops that would be gentle with a very new, very inexperienced PCB designer? OH and reasonable for a prototype. Last time I laid up a board I used a drafting table and mylar. I may need a bit of handholding as I go along. If you're in US then try BatchPCB if you can stand to wait 3 weeks. http://batchpcb.com/index.php/Home Pretty straight-forward service, reasonable prices for small quantities. Can't say how much hand-holding they'll give, but I have had a bit of helpful back & forth with them when first getting started. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Need help repairing a damaged FPGA board (GR-PCI-XC2V)
On 03/01/2010 03:00 PM, Timothy Normand Miller wrote: A relatively new professor here at OSU had one of these FPGA boards: http://www.pender.ch/docs/GR-PCI-XC2V_product_sheet.pdf Unfortunately, some students recently fried part of the power regulation circuit. We don't have the expertise to repair it ourselves, and we don't have the budget to buy something new. This board was being shared by multiple students, one of whom was using it for his masters thesis work. So its loss is rather painful and problematic. I was wondering if anyone could advise us on repairing this. Perhaps there is someone whom we could ask to repair it for us? Trying to get the original manufacturer to repair it would probably cost more than it's worth. The damage was done to at least the C12 and D9 components (lower left in the picture). Any suggestions and help would be most appreciated! That's a fairly old board (Spartan 2), looks like a PCI interface, along with some memory, Ethernet and RS-232. Depending on the exact features you need, you could buy up-to-date development boards from Digilent with an academic discount for less than $150 that would replace it. Take up a collection (with some stern looks in the direction of the folks who fried the old one) and you may be able to come up with the cash. Here's more info: http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10 Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: I am such a troll for posting to slashdot
On Feb 26, 2010, at 10:44 PM, Ales Hvezda wrote: > > http://hardware.slashdot.org/comments.pl?sid=1564716&cid=31289534 > > Let me be the first to apologize. :-) Don't! It needed to be said. > Although, a couple people have > posted that gEDA's documentation lacks in places. Don't know what they're complaining about - When I started using gschem & pcb a few years ago I just committed to doing it, ran through the tutorials and got on with it. Took a few days, but any tool has a learning curve. At about the same time I tried Eagle and didn't find it any easier and the closed/crippled aspects of it bugged me so I dropped it. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LVS and other pcb related questions
On 12/01/2009 11:57 AM, DJ Delorie wrote: > >> However, from what I can tell, there still isn't any concept of lvs >> in pcb, or am I missing that? > > PCB doesn't know about LVS, stripline, differential pairs, or any of > that. I think he means LVS as in Logic vs Schematic - a form of layout checking commonly found in ASIC design, not LVDS as in Low-Voltage Differential Signaling. In the ASIC world, LVS is a fairly complex problem that usually involves re-creating the netlist from the layout, then comparing that to the original netlist. This requires fairly detailed understanding of device structures to infer higher-level functionality. For PCB it may be more trivial, since all that need be re-created is the netlist itself, not the devices. Nonetheless it's not simple. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Kudos
On 11/03/2009 12:35 PM, Duncan Drennan wrote: >> * gschem magnetic nets - always seem to snap to the wrong thing for me >> so I end up turning them off always. Need to tweak my config file. > > You can temporarily disable this feature by holding in the CTRL key. I > guess that should be added to the wiki somewhere By golly, it works. Thanks for the tip! Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Goldmine LCD update
A few months back I linked a page with a little gEDA project based on a very inexpensive surplus graphic LCD: http://members.cox.net/ebrombaugh1/synth/dsPIC_lcd/index.html Since then I've managed to get it working and I've posted pix and source on the page. I've had help and encouragement from various sources along the way - thanks to all who contacted me about this. The biggest problem I ran into was getting a reliable electrical connection from the elastomer strip that comes with the LCD. Who knows how long these displays have been sitting around in a bin, probably in a non-air-conditioned warehouse in the Arizona desert. Consequently, I had to swab the strips (both sides) with IPA before getting a good connection. After that though it was pretty smooth sailing. Thanks to the gEDA team for tools & help. Comments, questions, etc welcome. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error building PCB from CVS
Eric Brombaugh wrote: > Kai-Martin Knaak wrote: >> On Thu, 02 Jul 2009 15:42:31 -0700, Eric Brombaugh wrote: >> >>> Probably a dumb question: I'm building PCB from CVS on Fedora 9, >> Just in case you don't already know: pcb recently switched to git. There >> is still a cvs mirror, though. See http://pcb.gpleda.org/obtaining.html > > Ah - so I'm working with old stuff here. I suppose that I haven't been > paying close enough attention to the list. Time to pull the socks up and > start learning git. Building from git worked w/o disabling documentation. FWIW, I was using the CVS at pcb.cvs.sourceforge.net, not the new one recommended by the wiki page at git.gpleda.org. Thanks for the help. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error building PCB from CVS
Kai-Martin Knaak wrote: > On Thu, 02 Jul 2009 15:42:31 -0700, Eric Brombaugh wrote: > >> Probably a dumb question: I'm building PCB from CVS on Fedora 9, > > Just in case you don't already know: pcb recently switched to git. There > is still a cvs mirror, though. See http://pcb.gpleda.org/obtaining.html Ah - so I'm working with old stuff here. I suppose that I haven't been paying close enough attention to the list. Time to pull the socks up and start learning git. >configure --disable-doc > or >configure --enable-maintainer-mode > may help. Yep, ./configure --enable-doc=no got me through the install phase. Who uses the local documentation anyway? :) Now I've got nice alpha images in my photo-mode renders. Thanks for the imagemagick script. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Error building PCB from CVS
Probably a dumb question: I'm building PCB from CVS on Fedora 9, following the steps described in README.cvs and INSTALL. Mostly works until partway through 'make': pcb.texi:4293: @image file `pad.png' (for HTML) not readable: No such file or directory. /home/ericb/build/pcb/pcb/doc//actions.texi:1513: @image file `puller.png' (for HTML) not readable: No such file or directory. pcb.texi:5819: @image file `thermal.png' (for HTML) not readable: No such file or directory. makeinfo: Removing output file `pcb.htp' due to errors; use --force to preserve. make[3]: *** [pcb.html] Error 1 make[3]: Leaving directory `/home/ericb/build/pcb/pcb/doc' make[2]: *** [all] Error 2 make[2]: Leaving directory `/home/ericb/build/pcb/pcb/doc' make[1]: *** [all-recursive] Error 1 make[1]: Leaving directory `/home/ericb/build/pcb/pcb' make: *** [all] Error 2 The PCB executable is actually built at this point and runs but none of the exporters are available. How to get further? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Updates
John Luciani wrote: >On Thu, Jul 2, 2009 at 1:55 PM, Eric Brombaugh ><[1]ebrombau...@cox.net> wrote: > >Anthony Blake wrote: > >> By the way, the LCD project was very cool. Will the board be >available >> at some stage? > > That's my intent. I've got it pretty much ready to go now, but > BatchPCB's DRC Bot seems to be down since yesterday afternoon and > they > still haven't approved the design for purchase. In any case, I'll > definitely let the list know if/when I get the LCD working. > >You should post it to dorkbot Boston too. Tim would enjoy seeing it. I'll do that. I couldn't find Tim's email address anywhere in his blog so I posted a link in the comments to the LCD entry, but that topic is several years old now and he may not be checking it regularly. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Updates
Kai-Martin wrote: > http://lilalaser.de/blog/wp-content/Bilder/Laser/dl-einfach_layout.png Nice rendering - esp. like the white background visible through the holes & the drop shadow. How do you do that? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Updates
Anthony Blake wrote: > Eric Brombaugh wrote: >> BTW - I like the formatting of your web page. Something feels very >> familiar about it. ;) > > Well spotted =) Yes I had your cheap graphic LCD project page open when > I decided to write up the toporouter stuff. I hope you don't mind! Not at all - I'm glad you found it helpful. Years ago (wow - more than 10!) when I started keeping a website for my personal stuff I wanted something with minimal complexity that could easily be maintained with a text editor. I whittled that format down from something I'd spit out of Netscape's old web editor. It's pretty spare, but it works. FWIW the little "W3C HTML 4.01" button on the bottom is mostly for my use in checking that the page is error-free. Handy little thing to add after I put up a page years ago that generated more complaints about the errors than interest in the topic. > By the way, the LCD project was very cool. Will the board be available > at some stage? That's my intent. I've got it pretty much ready to go now, but BatchPCB's DRC Bot seems to be down since yesterday afternoon and they still haven't approved the design for purchase. In any case, I'll definitely let the list know if/when I get the LCD working. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Updates
Anthony Blake wrote: > Hi Everyone, > > I've recently updated the toporouter website with some screenshots > showing the recent changes. > > http://www.wand.net.nz/~amb33/toporouter > > By the way, I could do with some more small to mid sized boards for > testing if anyone wants to send one through. Anthony, Looks great! BTW - I like the formatting of your web page. Something feels very familiar about it. ;) Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Cheap Graphic LCD project
A few weeks ago we discussed an inexpensive graphic LCD that Electronic Goldmine has been selling for a few years. It uses an elastomer contact and the only footprint available was in Eagle. I dumped some gerbers for the device out of Eagle and used the coordinates to build a PCB footprint. I've got a little project underway to test this out: http://members.cox.net/ebrombaugh1/synth/dsPIC_lcd/index.html I've got a bit more checking to do before sending the design off for fab, but hope to have something going soon. Once I've tested it I'll make the design files available for anyone else who is interested. (Yes, I know there are other sources of inexpensive monochrome LCDs. But I've got a bunch of these and want to try them out). Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gsch2pcb hangs in m4 - how to get more info to debug
Eric Brombaugh wrote: > Is there any way I can find out more details about what it was doing > when it hit that bad expression so I can debug? I've tried the -v option > but that doesn't appear to give any more information. Never mind. I created a different linkage to the PCB newlibs without the m4 directory and re-ran gsch2pcb. That appears to have worked OK. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gsch2pcb hangs in m4 - how to get more info to debug
I'm running gsch2pcb from a very recent build (pulled from git within the last few days) along with an older version of PCB & libs. I've put a link to the older PCB share directory into the new geda/share area. When invoked, I get the following output: Using the m4 processor for pcb footprints /usr/bin/m4:stdin:88: bad expression in eval: /2 after which the process hangs with the CPU maxed out. Is there any way I can find out more details about what it was doing when it hit that bad expression so I can debug? I've tried the -v option but that doesn't appear to give any more information. Thanks, Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem's new pretty menus
Peter Clifton wrote: > gschem just got new pretty menus (with some icons). I'd appreciate > people with different GTK+ versions checking that they work, since I've > only had a chance to test with GTK 2.16. (Specifically whether you see > the accelerator text on the right hand side of the menu). Just built it from scratch via 'git clone' on my Fedora 9 system w/ GTK2-2.12. Very nice looking, menus have both icons and accelerator text. Since we're sending screenshots: http://imagebin.org/51755 Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Drills
Rob Butts wrote: >Does anyone have a good source for drill bits that you don't have to >have a tunnel to Fort Knox? I need sizes .020, .025, .030... http://www.goldmine-elec-products.com/ search on 'drill bits' - they've got quite a lot of PC board bits in various sizes for reasonable prices. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: geda cygwin package
al davis wrote: > On Thursday 14 May 2009, Joerg wrote: >> What I bemoan is the utter lack of hands-on experience. Most >> newly minted engineers can't even solder properly. Pathetic. > > So sad. > > I recently saw a post on an email list that did a very good job > at illustrating, by example, why this is such a problem. You > should read it. > > http://tinyurl.com/p7aze6 A! The deadpan meta-irony makes my head asplode! Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
Chris Smith wrote: > Eric Brombaugh wrote: >> I also use Xilinx ISE (both full-blown and Webpack) under Linux with no >> difficulties. > > I've used that too, and it's a great source of irritation and amazement > to me that they manage to produce a 1.4GB install file to program a > device the size of a postage stamp! :( Yes, and that 1.4GB download balloons out to > 4GB after it's decompressed into the final hierarchy. I did manage to strip a whole lot of junk out of it and fit it onto a 2GB SD card for use with an eeePC901 under Ubuntu though. >> or I copy bitstreams to an SD card which is loaded into the FPGA at >> boot time via an on-board MCU. > > Would you mind elaborating a little on this 'bitstream' copying and > loading technique? I've got a home-made board with an NXP LPC2148 ARM processor driving a Xilinx XC3S250E FPGA via one of the SPI ports. At boot time the ARM reads the bitstream out of an SD card via a FAT filesystem, strips off the header and feeds it to the FPGA in slave-serial mode. After the FPGA is configured, the configuration clk/data inputs become a SPI port and that's how the ARM talks to the new FPGA design. More info (and source code) here: http://members.cox.net/ebrombaugh1/synth/armfpga/index.html Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
Stefan Salewski wrote: > On Wed, 2009-05-13 at 12:03 -0700, Eric Brombaugh wrote: >> Since their development >> IDE is Win-only I didn't see much point in pursuing it further. > > Maybe my understanding of your comment is wrong, but to make it clear: > Xilinx FPGA development tools called WebPack are available free of costs > for Windows and Linux. Downloading code to the FPGA may be a problem, I > guess the parport cable for the old Spartan-3 boards works. I have not > already used their WebPack for Linux, but I am sure it works. This was > the reason why I decided using Spartan-3E for my DSO board, not Altera > chips. Altera has tools for Linux too, but you have to buy it (It may > work with Wine under Linux?). The OP wasn't talking about Xilinx tools. He was asking about the Cypress PSoC processor that's also on the Avnet S3A board, and that's what my comments were directed towards. I also use Xilinx ISE (both full-blown and Webpack) under Linux with no difficulties. I don't do Xilinx downloads via JTAG under Linux though - I either use a Xilinx USB/JTAG pod under WinXP, or I copy bitstreams to an SD card which is loaded into the FPGA at boot time via an on-board MCU. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
Tamas Szabo wrote: > > I just recieved an Avnet Spartan-3A Evaluation Kit. It has the above > mentioned interface for downloading configuration. I only found Win > based software for it. > > Has anyone any experience with it under Linux? I did some work with PSoC a few years ago and wasn't able to find any Linux drivers for their USB programming dongle. Since their development IDE is Win-only I didn't see much point in pursuing it further. I believe that their MCU is based on an 8-bit Renesas architecture so there may be a GCC-based toolchain available, but you'll have a tough time finding any open-source software for setting up the analog and digital arrays. Plus, you'd be giving up all the firmware interface routines that their IDE automatically links in when you use the Cypress tools & libraries. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: HW vs SW tools evolution
John Griessen wrote: > How has SW design gotten farther? Probably it's just that the development of > tools is so close to the development > of apps for sale is all I can think of. This is an excellent point. It's a lot easier for someone in their spare time to develop usable software. It's a lot more expensive to develop a usable chip. I can sit in my office and for the cost of a computer and an internet connection code up an embedded software project in my spare time that brings in some cash. I can't build an IC. Imagine how difficult it would be to develop software if every time you wanted to test your code you had to spend thousands of dollars and wait three months. FPGA development tools are just now getting to the point where this isn't such a PITA, but even so the proprietary nature of the bare metal will interfere with open source ethos. The true revolution won't come until someone can build a 3D printer that can print a copy of itself. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
Ben Jackson wrote: >> The only way these things are at all possible is with a wide variation >> in levels of abstraction. They guy designing the transistors doesn't >> know about the circuits they go into, while the architect working on the >> memory management can't be bothered with the ESD structures of the I/O >> pads. > > That's all true. I just don't think it goes far enough. I don't know > if that's because it's a Hard Problem or if it's because engineers have > expectations that are too low. As a software engineer I came to the > party with much higher expectations. I'd argue that's it's a bit of both - it's a hard problem and we don't have the option of holding our breath until someone gives us the high-level tools. And it's not because no one is trying either - if you look at the research that has gone into creating the tools we have today you'd agree that it's not just due to laziness or 'make do'. It's like speech recognition or image processing - things that a trained person can do fairly easily but are very difficult to implement in machines. > I would compare the current state of FPGA development tools with my early > 8-bit computer experience. On my Commodore 64 I cared about every memory > location on the system. I wrote anything remotely important by hand in > assembly. Writing Verilog is at the abstraction level of approximately > a macro assembler. At the high end it might reach up into the level of > BASIC. No arguments here. OTOH, if you actually look at what's going on inside of an HDL synthesis tool as it turns your RTL into gates, I think you'd see that it's at least as complex as what a good optimizing C compiler is doing. It's just that the syntactic difference between the ideal HDL you'd like to use and hardware gates is a lot greater than that between C and machine code (which probably tells you something about C ;) ) Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
Ben Jackson wrote: > Well, that's basically my point. Working on a large IC requires a huge > team of people. I live right by Intel, so I see how many people they have > swallowed up to do chip design. My complaint is that the complexities of > designing chips or FPGAs is very poorly abstracted as compared to software > at large. The only reason it's possible to execute those designs at all > is that on an absolute scale they're fairly simple. That's no slight on > the people doing the work -- it's just a reflection of how ineffective > the tools are. This is an interesting perspective. Essentially I hear you saying two things: 1) A task that requires a lot of smart people to complete must suffer from a lack of adequate tools. 2) A task that can be completed with inadequate tools can't be very complex. From my standpoint there's a bit of a disconnect between these two positions. Coming from a background as a wireless systems engineer as well as a chip designer, I'm here to tell you that there's nothing simple about the chips I've worked on: the Wifi chipsets I was doing 6 years ago were complex enough that no one person understood _everything_ that was happening in them. Move up the food chain to something like a modern multi-core processor and it's amazing that they work at all. The only way these things are at all possible is with a wide variation in levels of abstraction. They guy designing the transistors doesn't know about the circuits they go into, while the architect working on the memory management can't be bothered with the ESD structures of the I/O pads. I have very little knowledge about how modern large-scale software development projects work, but I assume that they're also staffed by large teams, each with their own specialties - UI designers, core coders, build managers, library maintainers, QA & test. I don't see much difference between this and what happens in chip design. > I would like to be able to express the essence of what I need to do, such > as an arithmetic operation, without having to understand how it should be > pipelined, how wide the intermediate results need to be, how it should map > to the facilities of the FPGA (or hard macros or etc), etc. I would like > to be able to take that design and target FPGAs from different families > or vendors without having to reevaluate the design tradeoffs. Even if I > *did* have to make the choices manually (eg where to register intermediate > values), I'd like to control those aspects independently from the core > logic, rather than having to mix it in. Some of these are reasonable goals and a lot of engineers out there would agree with you, myself included. As far as the top-level design of pipelined arithmetic systems, I have actually used some tools that approached this level of flexibility - Synopsys Module Compiler was doing a lot of this 10 years ago on small systems. The big problem is scaling it up to what's normal today. Xilinx has taken some stabs in this direction with System Generator and AccelDSP, but these also have their shortcomings. Very few tools (any?) out there today allow you design complex arithmetic without specifying internal details, although many provide libraries of functions that you don't have to dig into to use effectively. Retargeting FPGAs from different families within one vendor is almost there - I'm able to port designs across Xilinx Spartan3, Virtex2, 4 and 5 families without too much pain. Going across vendors is a bit more of an issue because there aren't _any_ 3rd-party tools that handle the back end PAR processes - the vendors treat that as proprietary and require you to use their own tools. The only interface that works is the top-level HDL, and while it's possible to make retargetable code you give up a lot of performance due to the dissimilar IP structures. Nothing wrong with that - it's competition in action. I'm sure we'll get there. It won't be easy though. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
Ben Jackson wrote: > Frankly, having come to FPGAs from a long history of softare development, > the FPGA guys are working with stone age tools right now. The only reason > FPGA and ASIC projects get done at all is that their scope is vastly > simpler than a typical software project. OOooh! I guess I deserved that, but I can't let it pass without some comment. :) Them's hasty words sir. If your only perspective on modern IC design is from an FPGA perspective then you're not seeing the whole picture. I'll grant you that FPGA tools come up short in many ways, but ASIC tools are much more advanced (and much more expensive). The engineering challenges involved are much more complex - not just synthesis, place & route and timing, but also signal integrity, electromigration, mask development, etc. I'll concur that current software projects have enormous scope and demand some pretty powerful tools. Don't underestimate the challenges of developing a System-on-Chip for high-volume commercial use though. It's orders of magnitude more complex than what happens in the FPGA world. When doing an FPGA design, I can as an individual manage a project that completely fills the largest FPGA available. Working on a large commercial IC development project requires the skills of dozens if not hundreds of experienced engineers. As someone with experience on both sides, what improvements would you like to see? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
Joerg wrote: > Eric Brombaugh wrote: >> John Griessen wrote: >>> How about the code intensive hardware system developers that start >>> a project with FPGA then migrate it to ASIC? What language do they use -- >>> c++? >> Typically they'll use a HDL like Verilog or VHDL. Those are generally >> compatible across FPGAs and ASICs alike. There have been attempts to use >> C++ for hardware design, but they haven't found their way into the >> mainstream. >> > > C++ for hardware design? > > Yep - typically involves building a big class library to support things like clocked processes and basic RTL structures & methods. The results end up looking a lot like most other HDLs and don't really run much faster. And of course this requires a translation shim to get it into any normal ASIC or FPGA synthesis/PAR toolflow. As Stuart notes, you can operate at a higher level than some of the older spec'd HDLs, but a lot of higher functionality has been rolled into Verilog2k in the meantime so it's tough to say how much of an advantage it is. And of course it has the disadvantage of allowing software types think that they can design hardware without any additional training. :) (ducks) Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
John Griessen wrote: > Eric Brombaugh wrote: >> John Griessen wrote: >>> How about the code intensive hardware system developers that start >>> a project with FPGA then migrate it to ASIC? What language do they use -- >>> c++? >> Typically they'll use a HDL like Verilog or VHDL. > > OK for the HW. But they are developing code in parallel. > What do those types use for code languages is what I'd like to know... > I've been out of chip design work long enough to not know anymore. Hmm - not quite sure what you're asking here. If you are referring to HW/SW co-development for situations like SoCs which have embedded processors, then yes - the folks on the SW side will usually be developing in Assy/C/C++ and using simulators/emulators to test code prior to getting silicon. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
John Griessen wrote: > How about the code intensive hardware system developers that start > a project with FPGA then migrate it to ASIC? What language do they use -- > c++? Typically they'll use a HDL like Verilog or VHDL. Those are generally compatible across FPGAs and ASICs alike. There have been attempts to use C++ for hardware design, but they haven't found their way into the mainstream. There are newer HDLs starting to find more use though - System Verilog is becoming popular among some of my colleagues. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LCD Elastomer contacts
John Luciani wrote: >Unfortunately Tim does all his work in Eagle. >IIRC he was selling a PCB + LCD for apx $7 at the MIT Swap last year. >A >few weeks ago he mentioned to me he was working on a little display >sub-assembly that used that LCD and a PIC. I though you might know him - looks like he's in your neck of the woods. Might have to grab his artwork & create a PCB footprint - would make a nice little display for some projects I've got in mind. Goldmine is close by so it takes about 1 day to get stuff from them (they don't do pickup / willcall) and it looks like they still have plenty of these available at $1/pair. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: LCD Elastomer contacts
I just came across this page: http://tim.cexx.org/?page_id=342 which describes interfacing to a very inexpensive surplus LCD display via a zebra strip elastomer. He seems to have done all his work in Eagle, but I was wondering if anyone had a footprint for this in PCB. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: solder jumpers
DJ Delorie wrote: > I added something like that to my page... > > http://www.delorie.com/pcb/solderjumpers.html > > That one *can* be done as an element :-) Those look like they might also make good switch contacts for elastomeric buttons / keypads. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic bundler?
DJ Delorie wrote: > gschlas -e foo.sch > > My Makefiles copy foo.sch to tmp.sch, gschlas *that*, then copy > tmp.sch to it's final destination. Thanks - sounds nice and clean. Makefiles = good. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic bundler?
John Luciani wrote: > On Wed, Apr 15, 2009 at 6:24 PM, Eric Brombaugh wrote: >> I'm sure I've seen this discussed recently, but I can't find any threads >> to pick up and follow... >> >> Is there a way to suck all the gschem symbols into my schematic for >> archiving and/or distribution? > > I may have been the one that asked the question. > > Select all of the components and then choose embed symbols. Thanks John - that did the trick. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Schematic bundler?
I'm sure I've seen this discussed recently, but I can't find any threads to pick up and follow... Is there a way to suck all the gschem symbols into my schematic for archiving and/or distribution? Thanks, Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: chipscope vs. rerouting signals to test pads/pins
Michael Sokolov wrote: > I thought one of those GUI apps was the Webpack installer, and they've > made it impossible to bypass it by putting all the bits in encrypted (!) > ZIPs. At least this was the case the last time I looked at it in late > 2005, and this problem (the inability to bypass the installer) was what > made me choose Altera over Xilinx. > > How did you get around the installer block? I've had no trouble installing the full ISE on Fedora and I've been using it since 2005 or so. Webpack's installer is limited to 32-bit systems though, so if you're on a 64-bit system that might be getting in your way. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: chipscope vs. rerouting signals to test pads/pins
carzr...@optonline.net wrote: > OK, I was right, it is fpgaeditor. You will be using the 'probes' portion of > it. Here's the run down: > If you need some screen shots, I could probably provide some. Thanks for checking this. I've never tried it myself, but can see it would be useful. There's one little bit of advice you might be able to help with - I'm running ISE 10.1.03 on a Fedora 9 system and several of the GUI apps are impossible to run because they're linked against libXm.so.3 which isn't in any of the standard Fedora repositories. I've tried installing the CCRMA openmotif package, but that provides libXm.so.4. Do you have any suggestions on how to get around this? Thanks, Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Apr 4, 2009, at 11:08 PM, DJ Delorie wrote: > >> but the GUI application is DRMed. And it's also Windows-only from what I recall. I only use it on XP anyway... > Well, that may not work for me then, as I have to funnel the data > through an MCU, then USB, then to the Linux box. I also have nothing > connected to the jtag port, although I suppose I could wire that to > the mcu too. > > What would be cool is getting the LA data into a gtkwave-compatible > format. I've had good luck capturing data inside the FPGA in BRAM at the full clock speed, then reading it out slowly over SPI to an ARM processor where it gets formatted & sent via a USB CDC interface to code running on a PC. It's not screaming fast, but then neither is Chipscope via JTAG. It would probably be straight-forward to write C/Perl/whatever to format data dumped from BRAM as a VCD to load into gtkwave. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Apr 4, 2009, at 10:25 PM, Ben Jackson wrote: > > Why not just use chipscope? I thought you could get that for free > these days (although admittedly I use Altera mainly for free Signaltap > myself). I use Chipscope pretty much constantly, both on my day-job designs (Virtex 5) and on personal projects (Spartan 3E). It's a great way to get visibility & control inside the design and I'd recommend it. As far as I'm aware though, it's not free. IIRC, Xilinx provides a free 60-day trial, but to use it beyond that requires about $700 outlay for the permanent license. The hardware library elements to support it are free, but the GUI application is DRMed. There was an open-source (ish) work-alike that got a write-up in Xilinx's X-cell magazine a few years back that used the Xilinx JTAG library elements along with an external JTAG access API, but it's been pulled from all the websites mentioned in the article. It mainly provided register read/write access via JTAG and an external TCL-TK UI. As far as I know there was no internal logic analyzer provided. It probably wouldn't be too tough to duplicate and expand to include that functionality though. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Symbol style recommendations
Peter TB Brett wrote: > We'll have to agree to disagree. When I look at a schematic, I want to be > able > to quickly and easily work out what the circuit is designed to do, and having > the pins on my symbols arranged by function and bus offset rather than by > physical position helps a great deal. I find myself doing both approaches depending on what kind of components they are. Often I do physical position symbols just to "git 'er done" and I've found that this helps me think about layout issues earlier in the design process, as well as aiding in finding signals during hardware debug. > What do you do about parts that have different pinouts depending on what > package they're in? True. The other side of this coin though is complex parts like MCUs or FPGAs where the pins can have different functions depending on programming. For these parts, functional grouping is somewhat more nebulous. Isn't it nice to have the option to do either? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: sd card
On Mar 18, 2009, at 11:14 PM, DJ Delorie wrote: > > Anyone done any sd-card designs? Looking for symbols, footprints, > connector recommendations, schematics, anything I can leech off > you :-) > > Note: SD, not mini- or micro-SD. Surface mount preferred. Sorry - I used micro-SD. Symbol & SMD footprint available though. Any particular reason why? I've been getting the cards with SD adapters for cheap, so it doesn't seem to make any difference for compatibility and the size advantage of the micro- format is nice. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: mcu to sdram interface project
DJ Delorie wrote: >> I'd definitely recommend putting an SD slot on. The hardware is >> cheap, the interface is simple and there's so much you can do with >> it. I store my FPGA bitstream on the SD card, so updating the the >> hardware design is just a matter of copying the file onto the card >> and clicking it into the board. > > Hey, neat idea. I figured the ethernet was the other option; tftpboot > or the like. One other nice thing is that the DIN/CCLK pins of the FPGA become user I/O after configuration, so when you're done loading the bitstream the MCU can use those pins to talk to the FPGA code you just installed. My design has a SPI slave port on those pins so I can monitor/control with the same SPI port I used to load it up. Good for flexibility so I don't have to resynthesize just to tweak parameters in the hardware. Ethernet would be pretty nifty. A bit outside my comfort zone right now, but it would speed things up a lot. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: mcu to sdram interface project
DJ Delorie wrote: >> For FPGA configuration I used slave serial mode and drove the DIN/CCLK >> direct from a SPI port on my MCU - saved having to use Xilinx's special >> configuration flash parts. Does mean that the start-up process is a bit >> more complex though. > > I thought of doing that, but the advantage of using a separate eeprom > is that I can use the mcu to download the bitstream to it faster than > I can reprogram the MCU to have a built-in bitstream. Plus I can > learn something new in the process ;-) It was the reverse for me - I've always used the Xilinx config flash parts in the past and I wanted to see how well the other approach would work. Turns out to be pretty easy, although there are a few minor caveats about the configuration process that I learned along the way. > I also thought about adding a serial port, ethernet chip, and sdcard > slot to the test board, but then I decided "one step at a time". If I > were using a 32 bit mcu I'd reconsider - big RAM is a key to uclinux > support. The m32c is only a 16 bit MCU. Maybe I'll add them anyway, > though, just for fun. I'd definitely recommend putting an SD slot on. The hardware is cheap, the interface is simple and there's so much you can do with it. I store my FPGA bitstream on the SD card, so updating the the hardware design is just a matter of copying the file onto the card and clicking it into the board. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: mcu to sdram interface project
DJ Delorie wrote: > I finally got a verilog module that does a basic SDRAM interface (I > talked about this a little at the last freedog meeting) so I started > uploading stuff: > > http://www.delorie.com/electronics/sdram/ > > Nothing fancy yet; it does an activate/transfer/precharge for every > access the MCU makes. Perhaps later I'll add some smarts to it to get > rid of the *one* read wait state it requires - the MCU has a 35ns > setup time, so there's not much time to get the data out (and yes, > that's an obvious spot to add a burst cache). The MCU only runs at > 24MHz, the SDRAM is 133MHz (potentially asynchronous). > > Board's not done yet, but the interesting signals are routed > (mcu-fpga-sdram). Nice design - should be handy for giant RAM on small MCUs. I've considered trying to hook SDRAM up through an FPGA as well, but the complexity looked like it would eat up too many of the resources that I wanted for other things. It's interesting to compare the S3A with older parts. Nice that it can get by without the 2.5V VCCAUX - generating & routing that on the 2-layer S3E design I did recently was a bit of a nuisance. I ended up running the three supplies in a kind of 'snail-shell' concentric topology in the back-side of the board directly under the FPGA package which worked out nicely. I'm a bit curious what happens if you forget to set the 3.3V configuration bit - does it damage the part? Xilinx docs have all sorts of dire warnings about proper decoupling of the various supplies. I ended up putting a fair number of caps on the back side of the board just to get them close enough to the package pins. I haven't seen any issues with this in operation though, so it may just be CYA. For FPGA configuration I used slave serial mode and drove the DIN/CCLK direct from a SPI port on my MCU - saved having to use Xilinx's special configuration flash parts. Does mean that the start-up process is a bit more complex though. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Another gEDA-based project working
Jelle de Jong wrote: > Eric Brombaugh wrote: >> I've just finished assembling a new board that I did with gschem / PCB. >> Web page with description, photos & design info here: >> >> http://members.cox.net/ebrombaugh1/synth/armfpga/index.html > > Great work! Keep up the good work. > > Would it be possible to order it as demo kit for gEDA demonstrations that > I like to start doing. Thanks. It's been a fun little project and I haven't even tried out the real applications yet. A few of the things I've learned about on the way: * Hot plate reflow (for the USB connector, micro SD socket and dual LDO with heat-slug). I'm using one of those circular cast-iron ones similar to what DJ has on his website. Works pretty well. * Contaminated solder paste - the first bit that came out of the syringe-full I bought wouldn't stick to _anything_. I had to squirt a fair amount out before getting to the sticky stuff. My best guess is that it must have been the silicone lube that they put in generic syringes. * Dangers of violating minimum line width. :) * Reliability of low-cost fabs. I found a short from USB +5 to ground on one of my boards. A clear failure in the fab since it's not in the gerbers or on the other board I got. * USB interfacing - fairly simple if you use someone else's code on a popular processor. * SD memory interfacing - see above. * I2C interfacing. Watch those clock speeds. I'm sure there are a bunch of other things that will rise up to meet me as I continue with it... As far as kits go, sorry. I'm not set up to sell parts (there are probably about $70 worth on this board if bought in small qty). If you'd like to take the gerbers to your own fab though feel free to do so. It cost me about $80 for two boards shipped from BatchPCB. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Another gEDA-based project working
I've just finished assembling a new board that I did with gschem / PCB. Web page with description, photos & design info here: http://members.cox.net/ebrombaugh1/synth/armfpga/index.html Thanks to all the contributors to gEDA for helping to make this possible. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Digilent USB-JTAG and Lattice
Eric Winsor wrote: > I have been using the Digilent USB-JTAG cable to program Xilinx devices > and now am working with some Lattice CPLDs in a new project. Does > anyone know of some JTAG programming software that will recognize the > Digilent USB-JTAG cable and allow me to program Lattice parts? AFIK, no software in the world supports the Digilent USB-JTAG cable except for Digilent's Adept suite. Digilent doesn't make their protocols available for others to use, and since this cable uses a variation of the Cypress FX2 8051+USB 2.0 interface it's difficult to reverse engineer. A few years back, there was one fellow on comp.sys.fpga who claimed to have an open-source tool that would talk to the Digilent cable, but after trying it I wasn't able to get it to work. Subsequent attempts to contact the original author were unsuccessful. Maybe you would have better luck - find it here: http://sourceforge.net/projects/xilprg I believe that Digilent's Adept suite can 'play' SVF files, so if your Lattice tools can generate a JTAG SVF file, you may be able to load that into Adept. FWIW, Xilinx's Impact can be do this, so it's not unheard of. Let me know how it goes... Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Interesting board defect
Ben Jackson wrote: > On Sat, Feb 14, 2009 at 06:09:36PM -0500, DJ Delorie wrote: >> Yeah, it looks like you violated the "minimum trace width" on the >> hairline copper traces between the two pads, and they broke off and >> got glued down by the solder mask. > > Yep. If you have an unpopulated board and a stout bench supply I'd try > hooking it up and ramping the current limit to try to burn those traces > off. I've even managed that on boards where there were already > components and I could pump enough amps at the target VCC. That would have been interesting, but the x-acto approach worked fine. I was even able to use the ohmmeter to narrow down the location - a few ~0.2 ohm delta between the resistance at the short and a few cm away. Anyway - all fixed now & starting to build up the board. So far so good. Thanks to all for comments & suggestions. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Interesting board defect
DJ Delorie wrote: > I usually go through all my 0603's and increase the clearance just > enough to not have those slivers. Good idea - one more thing to add to my customized footprint library. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Interesting board defect
FYI: I just got a couple of new boards back from BatchPCB and found that one of my power supplies was shorted to ground. A close inspection revealed numerous hairline traces from the pads of some SMT capacitors which had been placed in a surrounding ground plane. A photo is available here: http://members.cox.net/ebrombaugh1/synth/armfpga/gnd_shorts.jpg Looks like just a tad more clearance around those pads would have prevented those fine traces of ground plane from forming, floating free and shorting to the supply pad. I can probably get out the x-acto and scrape these away but it'll be tedious. Learn something new every day... Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GTK RANT
On Jan 25, 2009, at 10:10 PM, DJ Delorie wrote: > The ideal would be to support the standard accelerators (like Ctrl-C > for Copy, etc) as well as two-key ones (like E E) for actions that > don't map easily to gtk standard actions. Non-modified keys are > normally not used as accelerators in applications, because most > applications include heavy use of text entry (word processor, > spreadsheet). gschem doesn't, so it can use unmodified keys for > gschem-specific purposes. This makes a lot of sense. I'd really like to see more of the traditional Ctrl-based accelerators implemented - especially for the more common file & edit menu operations. Two key accelerators for operations unique to schematic editing are fine though. >> (although pcb also uses unmodified keys as accelerators) Getting rid of the 'f s' sequence in gschem (or at least providing an alternative) would go a long way toward alleviating some of my mis- keys. The number of times I've turned my PCB layouts green as a result of using the gschem file save sequence in pcb... Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Convert unplated->plated holes?
DJ Delorie wrote: >> Like that. Is there a recommended best-practice (other than avoiding >> elements with unplated holes?) > > Plot gerbers. If you get an unplated-holes gerber, you missed at > least one. Grep the .pcb file for the word `hole' to fine them. Cool - that's almost what I did. I exported PS & viewed in evince for the unplated holes sheet. Your way is a bit less work. Thanks, Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Convert unplated->plated holes?
DJ Delorie wrote: >> Just looking at the .pcb file it seems it might be as simple as: >> >> s/\"hole\"/\"\"/ > > It would have taken you less time to try it, than to send the email... D'oh! Watch out for the LART! :) Actually, I did try it first. Just wanted to make sure I wasn't overlooking some other subtleties. > Yeah, that might work, if none of the holes have other attributes. Like that. Is there a recommended best-practice (other than avoiding elements with unplated holes?) Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Convert unplated->plated holes?
This seems like a FAQ but digging through the last year's worth of mail list history hasn't turned up the answer: What is the best way to convert all unplated holes in a design to plated? Just looking at the .pcb file it seems it might be as simple as: s/\"hole\"/\"\"/ Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
Larry Doolittle wrote: > On Fri, Jan 02, 2009 at 09:40:08PM -0700, Eric Brombaugh wrote: >> I've been glancing over some of the inexpensive Linux-based >> netbooks lately - a tad underpowered, but potentially useful and cheap >> enough to take a flyer on. I'm curious how useful a 1024x800 screen >> would be for gEDA/PCB. > > 1024x800? Where? They're all widescreen now. The lightweight, > inexpensive ones are 1024*600 or so. The larger, heavier, cheap and > modern notebooks get up all the way to 1280x800. > > The lack of height would hurt me, at least. I now use a 1024x768 > Thinkpad X40 (which I have promoted here before: US$400 on eBay). > I couldn't stand going any smaller in screen size. Dredging up this old thread again... I found an ASUS EEE PC 900A at a local big-box last week for $200. After a few false starts with the pre-installed Xandros distro, I loaded up Ubuntu eee which seems to be working well. gEDA/PCB were easily added with apt-get (although the Ubuntu repositories are still on 20080202 unfortunately) and gschem + PCB work fine. Surprisingly usable, even on the small screen. I do wonder if there is any way to get a newer package though. Fedora 9's yum repository is pretty much up-to-date. I guess compiling from source is the only way for now. Overall not bad though. It would work in a pinch. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: 45deg rotation?
DJ Delorie wrote: > Cut the part > > :FreeRotateBuffer(45) > > Paste the part Thanks! Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: 45deg rotation?
I'm seeing a lot more boards coming out lately with BGAs, QFPs, etc. placed at 45deg from the grid. Is this possible with PCB? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint with thermal paddle
DJ Delorie wrote: > Hmmm... you might want to look in src/draw.c and see if you can bypass > the whole mask drawing operation when the mask size is zero, then. > "Patches welcome" :-) I'll put that on the to-do list & deal with the notches for now. Thanks! Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint with thermal paddle
DJ Delorie wrote: > Edit the file with a text editor and change it to zero. That's what I've been doing. Here's what the pads lines look like: # Back copper pad with full mask: 7.8x3.4mm Pad[ 0 -8660 0 8660 13385 0 0 "25" "25" 0x0100] # exposed copper on top: 3.4x4.48mm Pad[ 0 -4094 0 4094 9448 0 9448 "25" "25" 0x0100] Even when I comment out the second pad I still get a narrow stripe of exposed pad down the center of the first one. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint with thermal paddle
DJ Delorie wrote: >> I wonder if a couple of overlapping pads would work. > > That's what I did. One pad for the copper extent, and a set of > smaller pads to define the paste and mask. You just have to number > them all the same. Thanks - I'm coming close to a solution this way. The trouble is that it seems like it's not possible to define a pad with no mask opening at all - there seems to be a minimum opening in the copper extent even when the mask and clearance are set to 0. This results in a slight notch in the desired mask when combined with the mask pad that I put on top of it. It's not much of a notch and I might be able to live with it, but it's there. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Footprint with thermal paddle
Hi, I'm using a high-power TSSOP24 that needs a thermal paddle under it. The unusual thing about this is that the recommended solder mask on the paddle has less clearance in the X direction than in the Y direction. How would one do this in PCB? MFG dimensions for the pad are 3.4 x 7.8 mm, while the mask opening is supposed to be 2.4 x 4.48 mm. I came up with this pad specification: Pad[ 0 -8660 0 8660 13385 1000 9448 "25" "25" 0x0100] which has the proper amount of copper, but allows the mask opening to be taller than it's supposed to be. Thanks for any insight, Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Dumb PCB question - smd parts on back of 2-sided board
It's been about 6 months since I did a 2-sided board with smd parts on the back side and I seem to have forgotten the magic incantations. Stuff I know: * 'shift-B' flips an element to the opposite side from which it is currently on. * 'B' seems to toggle the back side silk to visible on the previous board I did. Oddly, the front-side silk is also still visible. What I tried: I flipped a few caps from the component to the solder side. This seems to change their position too, and their refdes becomes faint. 'B' doesn't seem to have any effect on this board though. I moved them to the location where I want them, opposite a large LQFP. Now when I try to rotate them the LQFP on the other side rotates instead. My questions: * Why doesn't the 'B' work on my new project? * How to prevent edits to elements on the solder side of the board from operating on component-side elements? Thanks, Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Dumb PCB question - smd parts on back of 2-sided board
Replying to myself: I did a bit more digging and found the magic 'Tab' key. Now everything works as I remembered. Thanks to DJ's tutorial! Further question though: what's the difference between 'B' and 'shift-B', other than 'shift-B' does odd things to the position? Eric Eric Brombaugh wrote: > It's been about 6 months since I did a 2-sided board with smd parts on > the back side and I seem to have forgotten the magic incantations. > > Stuff I know: > > * 'shift-B' flips an element to the opposite side from which it is > currently on. > > * 'B' seems to toggle the back side silk to visible on the previous > board I did. Oddly, the front-side silk is also still visible. > > > What I tried: > > I flipped a few caps from the component to the solder side. This seems > to change their position too, and their refdes becomes faint. 'B' > doesn't seem to have any effect on this board though. > > I moved them to the location where I want them, opposite a large LQFP. > Now when I try to rotate them the LQFP on the other side rotates instead. > > My questions: > > * Why doesn't the 'B' work on my new project? > * How to prevent edits to elements on the solder side of the board from > operating on component-side elements? > > Thanks, > > Eric > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
On Jan 2, 2009, at 9:02 PM, der Mouse wrote: >>> I just can't say enough good things about my Mackbook Pro. [...] >> I've been happy with Apple laptops for a few years now. [...] > > To offer a slight counterweight to the Apple gushiness...I wouldn't. Despite being one of the earlier 'gushy' folks, I'll grant you've got some valid criticisms: - their dialect of *NIX is different. I liked your comparison to AIX - I remember that! - Closed source OS rubs some folks the wrong way - even when they provide free development tools & documentation for coding on top of the OS, not having access to the guts is annoying. - Hardware is more expensive than commodity PCs. - Apple's sales & support has a certain attitude that can be grating. So given you don't like Apple, what do you recommend for a good laptop? I've been glancing over some of the inexpensive Linux-based netbooks lately - a tad underpowered, but potentially useful and cheap enough to take a flyer on. I'm curious how useful a 1024x800 screen would be for gEDA/PCB. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
Stephen Williams wrote: > > I just can't say enough good things about my Mackbook Pro. The > only glaring issue, is the price. I've been happy with Apple laptops for a few years now. I got an iBook back in '03 which is still in daily use and a newer Macbook about a year ago which is working well. *NIX compatibility and the fink package system make it great for development. gEDA/PCB work well and the packages seem to stay current. Agree that extra memory is helpful, but 3rd-party chips from a reputable vendor are easy to install and more reasonably priced than Apple's. Apple hardware is a bit more expensive, but the polish in hardware & software is worth it to me. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: OpenOCD?
On Nov 1, 2008, at 5:58 PM, John Doty wrote: > Anybody using OpenOCD? I looking at an Atmel AT91SAM7X-EK board for > prototyping a data acquisition device, with the eventual intention of > designing a custom board around the AT91SAM7X256 processor with gEDA. > I need to program it somehow, and Windoze is alien to both the end > users and me. > > I'd be interested in any experiences. There are no doubt other places > to inquire, but I feel I understand the viewpoints of folks on this > list, and they are more likely to be close to mine. I'm using OpenOCD with an Atmel AT91SAM7S64 processor (home-made board) and an Olimex USB-Tiny USB/JTAG converter under Fedora 9. It took a bit of fooling around to get it up and running reliably, but it has been working well since then. The important step for me was to use the FTDI driver. I haven't gotten the gdb stuff working 100% yet - something about the RAM/Flash specifications that OpenOCD is supposed to send to gdb is wrong so breakpoints don't work quite right. OpenOCD works great for downloading code into the ARM flash though, and that's mainly what I've been using it for. Getting it all installed is a bit of a chore - tracking down all the code, drivers, various application scripts, documentation, etc. can take a while. The WinXX users have a lot of pre-packaged installs like Yagarto available, but if you're on Linux then there's a bit less hand- holding available. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: powermeter board, with less ground planes :-)
DJ Delorie wrote: >> At the end of the day the only thing that counts is whether it's >> good enough and it looks like DJ's board should perform pretty well >> now. > > And yet I keep improving it anyway. If there's one thing I've learned about working on layouts it's that you're never really done - you just have to stop sometime. There's always room for one last tweak! I run PCB on my MacBook - sitting on the couch, watching TV & fiddling with board designs is almost like playing solitaire... I know - sick... Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ Delorie wrote: >>> I have one I use every day, but it's in my watch. >> So that watch isn't on a wrist band it is on an adjustable crane hook. > > Heh, I suppose. > > FYI it's a Timex Ironman USB. Very useful watch. But can you talk to it with Linux? Eric (who still uses a VR3 - mostly to play DJ's Ace of Penguins Freecell) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: the peril of ascii file formats
On Sep 20, 2008, at 7:15 PM, DJ Delorie wrote: > > Today I sat down to work on my latest project. Next step, rearrange > some of the signal wires. I type "vi mcu.sch"... er, no, > backspace... "gschem mcu.sch", yeah, that's right. That's not a bug, that's a feature. It _would_ have worked. Just differently. Eric (who appreciates being able to textedit the databases when necessary) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Deformed undesired tiny square
Andrea Grillini wrote: > It happened to me at least twice. I draw a pcb or a footprint and then I > keep seeing the square mentioned in the subject and a can't get rid of > it. It looks like a tiny square hole and apparently it has no connection > with the rest of the drawing, it simply stays there. Any explanation? > Any solution? I've seen this before in some of my designs and it was driving me bananas. I finally figured out what it was by noting the XY coordinates of the 'hole' and searching the .pcb file for similar values. It turned out to be a text object with null string data. I just used a text editor to delete it from the .pcb file and it went away. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Another PCB from the gEDA tool flow
A tiny little SMD board for use with FPGA development systems. Fabbed at BatchPCB - I ordered 5, they sent me 10. Haven't fully tested it yet, but powering it up didn't let out any magic smoke. http://members.cox.net/ebrombaugh1/synth/audiodac/index.html Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: sparkfun 4 layer boards
Dave McGuire wrote: > On Aug 23, 2008, at 1:52 PM, Dave N6NZ wrote: >> So, how much mileage could we get out of a cheap digital camera and >> replaced the IR blocking filter with a visible light reducing filter? >> There might be a cheap hackable camera that is suitable, since a >> lot of >> the low-end imagers are quite sensitive in IR. Old camcorders >> might be >> another bet. > >I'd be shocked and amazed if they could detect thermal IR. Agree - there's a big difference between the short-wave IR that's used by common IR remote controls (which is easily seen on most any webcam) and the long-wave IR used in thermal imaging. You might be able to get a cheap CMOS imager to do it, but you'd probably need a fairly unobtainium long-wave IR filter, and possibly some sort of cooling rig. Maybe mount it on a Peltier junction - of course then you'd need some crazy insulation & sealing to keep it from frosting over. Gets complicated pretty fast. Go here for more info on thermal imaging: http://www.electrophysics.com/ Looks like most of their stuff works in the 7 - 14 micron wavelength. I've got an inexpensive IR thermometer though - $25 from SparkFun: http://www.sparkfun.com/commerce/product_info.php?products_id=86 You might be able to use something like that to hunt down hotspots, except that the response time is slow enough it would get pretty tedious. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: sparkfun 4 layer boards
Mark Rages wrote: > > I've had moderate success clearing blind shorts with the 5V bus of a > high-power computer power supply. (This can be hazardous to other > parts on an assembled board) Otherwise, use a current-limited power > supply to put a few amps into the stuck node. Use a millivolt meter > to measure different places on it. Lower voltage means closer to the > short. An IR camera to look for the hotspot would probably be a handy way to do this too. Who's got an IR camera though? FWIW, strange shorts can happen on high-end board mfg. lines too. I recently had a fairly large board used in my day job start smoking after several hours of use. Tracked it down to a power via that internally shorted to a ground layer. Destroyed the via, carbonized the board and de-laminated the top layer in the vicinity, but after I drilled it out, removed debris and sealed with solder-mask touchup the board is usable again (one-off prototype with several hundred dollars worth of fast ADCs, so we preferred not to junk it). Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: sparkfun 4 layer boards
On Aug 22, 2008, at 9:31 PM, Dave N6NZ wrote: > > Quality has been variable. Until recently I'd have said mostly > good. In > an earlier order I had a bad board, but in my last batch (of 4 > designs) > I ordered 4 copies of one design, a 48mm x 72mm 2 layer board, pretty > simple, all through hole. I got back 6 copies (I'm thinking "bonus!") > but the first one I assembled had a short in it :( I buzzed out > another > one and it was good so I assembled it no problem. A friend wanted > one, > so I buzzed out another one and found another shorted board :( so I > buzzed out yet another one pretty thoroughly for shorts (but not 100% > connectivity) and gave it to him. He found an open trace which he had > to jumper around. What sort of shorts are you seeing? I'm assuming that on a 2-layer board they would ordinarily be pretty easy to correct by appropriate use of an knife. Or are they internal/inaccessible? Is that even possible on a 2-layers? Eric who has one successful design through Batch PCB (3x6 board, ordered one copy & got two) and is waiting for another to come in the mail (5 copies of one small board) - hopefully next week. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
DJ Delorie wrote: >> Well, that's enough reason to use the proper grouping. Would >> 'Optimize Rats' and DRC catch the short, or would it be undetected >> until you built the board and smoked a part? > > In the few cases where I'd seen it, the gerbers are just solid black. > Really hard to miss. > > More common is polygons on their own layer, with no electrical > connection at all. > > Yeah, most of the time drc or rats would catch it. Thanks to DJ & Ben for all the help. The design is looking much nicer now. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
DJ Delorie wrote: >> Thanks - I've made that change. Just out of curiosity, what's the >> impact of the incorrect grouping? > > Worst case? Polygons shorting your SMT pads. Well, that's enough reason to use the proper grouping. Would 'Optimize Rats' and DRC catch the short, or would it be undetected until you built the board and smoked a part? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
DJ Delorie wrote: >> Interesting. I believe that this grouping came from the default >> generated by gsch2pcb that 'ships' with the 20080202 rpm from fedora. > > In my tutorials, I have the user create a blank board first, then use > gsch2pcb *only* to add elements and update the netlist. Aha - now I see the price paid for following the wrong tutorial. I started with this one: http://geda.seul.org/wiki/geda:gsch2pcb_tutorial Now that you mention it, I do recall some discussion on the list a while back about the problems with using the defaults created by gsch2pcb. Any particular reason why that hasn't been corrected? >> Can I fix it simply by editing the 'Groups' block in the .pcb file? > > Yes. Thanks - I've made that change. Just out of curiosity, what's the impact of the incorrect grouping? Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
Ben Jackson wrote: > On Thu, Aug 21, 2008 at 09:45:04PM -0400, DJ Delorie wrote: >>> http://members.cox.net/ebrombaugh1/synth/dsPICfun2/dsPICfun2.pcb.tgz >> I've reproduced this, it's the usual b->contours bug. > > It is crashing because the polygon dicer is trying to cut a polygon > through its first hole > It's caused by the > cluster of vias near C109. If you draw a small poly on the solder side > just over that "southern cross" of vias you can see it clears badly. > > The problem line appears to be the "C" shaped trace on the solder layer. > If you delete it and redraw it (at least the way I happend to redraw it) > you can have the polygon > > Aha! The longest 45 degree line in that trace is actually two co-linear > lines. It's not supposed to be possible to create them, and I've known > it to cause trouble with the polygon code before. You can easily see it > if you use the move tool on it. If you move them out of a straight line, > or get rid of the vertex, or just totally redraw it, everything works. Indeed - Upon closer examination of that area I see that even the latest CVS version is having trouble with the geometry in that area, shorting some of it out to the plane. Replacing the co-linear lines with a single line appears to fix the problem. > I'd be curious to know how you drew that line, if you recall :) If you > have a lot of cvs revisions I'd also like to know if it got split at > some point along the way after the initial drawing. Oh - now you're asking _me_ to do some work. :) Unfortunately my CVS versions aren't fine-grained enough to catch how that happened. Knowing me though, I was editing a more complex set of lines and just straightened out a vertex. Thanks for looking into this in such detail - I'm learning a lot by trying to follow along... Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
DJ Delorie wrote:
> Quick notes:
>
> One big rectangle is better than five overlapping rectangles.
Indeed - that's what I'd prefer too. My experience with 20080202 however
was that one big rectangle had a tendency to fill incorrectly and leave
large gaps. Multiple overlapping rectangles were my answer to that. Now
with the CVS version I see that one big rectangle works correctly, so
that's what I'll do from here-on out. Of course now I need to figure out
how to get my Mac OS X Fink installation of PCB updated to be in sync
with CVS.
> I don't know how, but you have two groups containing the "component"
> side, and two containing the solder side:
>
> Groups("1,2,3,s:4,5,6,c:s:c")
>
> The last :s:c should be :7:8
Interesting. I believe that this grouping came from the default
generated by gsch2pcb that 'ships' with the 20080202 rpm from fedora.
Can I fix it simply by editing the 'Groups' block in the .pcb file?
Thanks for checking! It seems that I've acquired a lot of bad habits
from to the rpm version...
Eric
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Re: gEDA-user: Halp! PCB crashing on my design
DJ Delorie wrote: > Yeah, just delete the polygons from the .pcb and it should go away. > I'll poke at it and see what I can do with it. That worked. Thanks a bunch! Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
DJ Delorie wrote: >> http://members.cox.net/ebrombaugh1/synth/dsPICfun2/dsPICfun2.pcb.tgz > > I've reproduced this, it's the usual b->contours bug. Aha - any way I can hand-edit the .pcb file to recover from this? If it's just the rectangle fills I wouldn't mind deleting them to get my routes & moves back. Thx, Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
Dan McMahill wrote: > Eric Brombaugh wrote: >> the README.cvs document appears to be out of date > > I just fixed the README.cvs document to have the right server name. Thanks! >> Note that >> building bombs out on documentation due to lack of some files: > > Yep. When building from cvs, you need either --enable-maintainer-mode > or --disable-docs. Thats covered in README.cvs. This headache is the > price we're paying for allowing users building from a tarball to not > need latex for building documentation. Sorry - my bad for not reading all the way through the dox. For those who are interested, the new version I just built did spit out a bugreport when crashing on my design. It's available here: http://members.cox.net/ebrombaugh1/synth/dsPICfun2/pcb-bugreport.txt Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
Eric Brombaugh wrote: > I've been trying to get logged into the sourceforge CVS server > for a while now but it seems to be hung (just sits waiting after I hit > for the PW prompt). I'll try again later tonight. That's solved - the README.cvs document appears to be out of date and is giving incorrect checkout information (the server name is wrong). Instead, use the information on the PCB CVS information page. Built from CVS OK after installing intltool & gettext-devel. Note that building bombs out on documentation due to lack of some files: pcb.texi:4293: warning: @image file `pad.txt' (for text) unreadable: No such file or directory. /home/ericb/build/pcb/pcb/doc//actions.texi:1509: warning: @image file `puller.txt' (for text) unreadable: No such file or directory. pcb.texi:5819: warning: @image file `thermal.txt' (for text) unreadable: No such file or directory. The new executable is able to load the previous version but still bombs out on loading the design. I've put a compressed zip of the bombing design here for your debugging pleasure: http://members.cox.net/ebrombaugh1/synth/dsPICfun2/dsPICfun2.pcb.tgz Thanks for any suggestions/help. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Halp! PCB crashing on my design
Ben Jackson wrote: > On Thu, Aug 21, 2008 at 05:26:20PM -0700, Eric Brombaugh wrote: >> I'm using pcb version 20080202 installed from rpm for Fedora 9 with the >> GTK HID. > > As always it's worth trying the CVS, since PCB improvement has been > rapid in the last year or so. Thanks - I've been trying to get logged into the sourceforge CVS server for a while now but it seems to be hung (just sits waiting after I hit for the PW prompt). I'll try again later tonight. > You could also make the file available to the core developers to debug > the problem. I think anyone here who has posted a PCB that gave them > problems has gotten extremely good support! That's last resort if CVS doesn't help. I have a feeling this is related to rectangles - 20080202 has some real heartburn area filling with complex keepouts and I had just added some new flood-fill to the backside before saving. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Halp! PCB crashing on my design
PCB Gurus, This morning I made some edits to a design, saved the results, quit and checked them in to CVS. Now when I try to open the design up in PCB the application bails out without issuing any errors. Running pcb without arguments brings up the application, but attempting to load the design from the File menu also crashes it. Running pcb with the --verbose switch doesn't give anything particularly useful either: Action: RouteStylesChanged() ChangeGroupVisibility(Layer=0, On=1, ChangeStackOrder=1) Action: LayersChanged() Action: PointCursor() Action: PointCursor() Action: RouteStylesChanged() ChangeGroupVisibility(Layer=3, On=1, ChangeStackOrder=1) Action: LayersChanged() Action: PointCursor(True) Action: PCBChanged() Action: PCBChanged() EvaluateFilename: Template: /usr/bin/../share/pcb/ListLibraryContents.sh '%p' '%f' Path: .:/usr/bin/../share/pcb Filename: pcblib Parameter: (null) EvaluateFilename: /usr/bin/../share/pcb/ListLibraryContents.sh '.:/usr/bin/../share/pcb' 'pcblib' Action: LibraryChanged() Action: PointCursor(True) Action: PointCursor(True) ghid_layer_buttons_update cur_index=0 update_index=3 Activating button 3 Action: PointCursor() >crash< This isn't a killer - I've got the previous version of my design in CVS and can revert to that so I would lose a bit of work, but it's not too bad. The question though: is there any way to find out what went wrong? I'm using pcb version 20080202 installed from rpm for Fedora 9 with the GTK HID. Thanks, Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
