Re: gEDA-user: How to find which specific part of a PCB is shorted?

[Ethan Swint]

On 08/31/2011 07:09 PM, Kai-Martin Knaak wrote:

Thomas Oldbury wrote:


I am getting these messages:

Warning! Net "3V3plus" is shorted to net "GND"
Warning! Net "GND" is shorted to net "3V3plus"

The 3.3V bus is used all over the board. How can I locate
specifically which part is shorted?

This is what I do:

1) open the net list window

2) click on one of the offending nets. The right side of the netlist
window will show all the pads and pins that are connected to this net.

3) double click a pin or pad. On the canvas, the cursor warps to the
pin.

4) move the mouse slightly

5) zoom in

6) type [f] while te mouse hovers over the pin or pad

7) follow the highlighted path to see, where it goes off-road.

Step 4 and 5 are really only necessary, if the pin count is fairly
large.

If the offending connection is to ground, like in your case, and there
is a ground plane, then there may be find color all over the place. So,
there is no visible path to follow. In that case, I put the polygons
into their own layers with their own, private layer group. They are not
considered connected anymore

If everything else fails, I resort to plain old bisection: Remove the
right half of the layout and check, whether the short goes away. Repeat,
until you spot the problem. Then revert to the complete layout.

---<)kaimartin(>---
Since we have such a good, algorithmic method for finding these shorts, 
perhaps we can write some code to do it for our puny human minds?  ;)


Usually, when I have power and ground shorted, it's because of a via 
placed some where that was accidentally assigned thermals to the wrong 
layer.


-Ethan


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Re: gEDA-user: gschem vs. PCB diode pin numbering

[Ethan Swint]

On 08/27/2011 10:37 PM, John Doty wrote:

On Aug 27, 2011, at 8:12 PM, Dan McMahill wrote:


This problem goes beyond diodes and transistors.  For example, the old
10H series of ECL parts came both in DIP packages as well as PLCC
packages.  Some of the parts though, would be in a 16 pin DIP or a 20
pin PLCC and so the pin numbers didn't agree between the two packages.

Yep. I recently got bit by this with the LT1078 opamp (different pinouts in 
DIP8 and SO8).
You could (ab)use the slotting functionality to account for different 
packages - just remember which package goes with which slot number.  I'm 
guessing (though I haven't checked) that slots must be assigned a 
number, and not a string.  If it were a string, that would make it quite 
a bit more versatile for this usage.


-Ethan


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Re: gEDA-user: gschem vs. PCB diode pin numbering - anode/cathode definition

[Ethan Swint]

On 08/24/2011 01:15 PM, Colin D Bennett wrote:

On Wed, 24 Aug 2011 08:21:17 -0400
Ethan Swint  wrote:


On 08/23/2011 08:47 PM, Matthew Lewis wrote:

I was double checking a pcb layout today and I discovered a rather
nasty gotcha. It seems that gschem and PCB don't agree on which end
of a diode should be pin 1. Gschem views pin 1 as the anode and PCB
considers pin 1 to be the cathode. It doesn't prevent you from
laying out a board correctly, but it does cause the silkscreen
polarity to be printed backwards (for the SOD devices at least).

I've defined my own symbols and footprints to use 'A' and 'K' instead
of 1 and 2.

That's a good idea.  Anything you can do to error-proof yourself is
a Good Thing.

However, I refuse to use “anode” and “cathode” for diode symbols, since
these terms refer to electron flow and are _incorrect_ when the diode is
reverse-biased (most obvious for common Zener diode circuits).




I understand that it is electrical convention to name diode terminal
anode and cathode, but I reject it as a confusing and ambiguous naming
convention.
Yes, it's not quite correct, but it is a widely held convention, unlike 
numbering the pins 1 and 2 (or 3 or 4).

For my diode symbols and footprints, I choose to name the terminals
“P” and “N“ (for the p-type doped side and the n-type doped side).

If you use "P" and "N", Schottky diodes are now in error.  ;)


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Re: gEDA-user: Symbols with Multiple Heterogeneous Gates in Gschem

[Ethan Swint]

On 08/24/2011 12:34 AM, Gus Fantanas wrote:

Hello All,

How does gschem handle cases of different "gates" in the same 
package?  For example, I am trying to create a symbol for On 
Semiconductor's NTZD3155C complementary PMOS-NMOS MOSFET pair.  Unlike 
the dual/quad NAND/NOR gates in the gschem tutorials, this package 
contains two heterogeneous (non-interchangeable) and totally separate 
gates.  I can put the whole thing in one big symbol, but I like the 
elegance of using each of the two complementary MOSFETs separately by 
itself in the schematic.
I believe that the accepted way to do this is similar to separating 
power and logic pins - just simply define two separate symbols and make 
sure that they have the same refdes.



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Re: gEDA-user: gschem vs. PCB diode pin numbering

[Ethan Swint]

On 08/23/2011 08:47 PM, Matthew Lewis wrote:
I was double checking a pcb layout today and I discovered a rather 
nasty gotcha. It seems that gschem and PCB don't agree on which end of 
a diode should be pin 1. Gschem views pin 1 as the anode and PCB 
considers pin 1 to be the cathode. It doesn't prevent you from laying 
out a board correctly, but it does cause the silkscreen polarity to be 
printed backwards (for the SOD devices at least).
I've defined my own symbols and footprints to use 'A' and 'K' instead of 
1 and 2.



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Re: gEDA-user: Preventing elements from appearing in BOM

[Ethan Swint]

On 08/20/2011 11:50 AM, Matthew Lewis wrote:
Is there a way to prevent a device from appearing in the BOM and in 
the XYRS file? The problem I'm trying to solve is that I have a pin 
defined in my schematic for attaching a wire to the PCB. There is no 
actual device to be installed. In order to get the pin to show up on 
PCB's rat's nest, I defined a dummy device with a hole for a 
footprint. This allows the rat's nest to show that there's something 
that needs to be added to the PCB layout. The problem now is that the 
dummy device shows up in the BOM and is also being placed in the 
gerber XYRS file. So the question is how do I get the hole to be 
recognized by the rat's nest on PCB, but get omitted from the BOM and 
the XYRS exports?


I usually put 'DNP' for 'Do Not Populate' in the 'Value' attribute and 
append a note in the file to that effect.  Most assembly houses know and 
work around that.  If not, then you get to write a handy script to scrub 
DNP lines or do it manually.
I've also noticed that the BOM generated by the export function of PCB 
is showing the device's footprint rather than the device name for the 
description. Is this correct?
I think that the intended/more common flow is to use gnetlist to 
generate the BOM from the schematic.  There was a message on the list 
just recently that pointed to the exact locations for generating BOMs.


-Ethan


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Re: gEDA-user: Anybody ever had a board assembled (pick and place)?

[Ethan Swint]

On 08/01/2011 06:33 PM, yamazakir2 wrote:

Still looking for suggestions for assembly besides 4pcb.


Advanced Assembly, aapcb.com.  Where are you located?


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Re: gEDA-user: Anybody ever had a board assembled (pick and place)?

[Ethan Swint]

On 07/27/2011 05:57 PM, Stephen Ecob wrote:

On Thu, Jul 28, 2011 at 5:35 AM, yamazakir2  wrote:

I sometimes get boards done at 4pcb, I didn't know they do assembly.
How much to they charge? And how big of a reel do you have to send
them? And you just cut tape the amount of parts you need to assemble
the amount of boards you want to manufacture?

A length of tape with no reel can be put onto a spare reel quite
easily, there's usually no charge.  The tape does need a leader of
around 300mm (varies) that has no components.  If your tape has no
leader then one option is to junk the components on the leader length
- not very expensive if you're talking about 60 millicent resistors
but a problem for expensive components.
One house I've worked with is Advanced Assembly, which is just down the 
street from Advanced Circuits.  (They'll pick your boards up from 4PCB's 
will-call.)  IIRC, it was ~$100 for the first moderate board (150 or so 
SMT components), add ~$30 if you do SMT on both sides, and $0.50 per 
thru-hole device.  Additional boards run cheaper, as usual,  and they 
will do a quick-turn on the first two or three boards and send them to 
you to verify before populating the rest of the order.  The quick-turn 
boards are billed at the same rate as the rest of the order, so you 
don't pay a premium on them.


A Assembly will purchase components on your behalf, but of course you 
pay a bit extra for that.  If you 'kit' the components yourself, you can 
send them your BOM and they will send back kitting labels similar to 
what you get on Digikey parts (mfg, mfg PN, refdes, description, 
internal bar-code, etc.) that you stick onto your components, either 
reel or cut-tape.  They can do 0603s reliably, 0402s have a significant 
mortality rate.


Regards,
Ethan



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Re: gEDA-user: PCB segfaults on click in netlist window

[Ethan Swint]

On 07/19/2011 05:48 PM, Kai-Martin Knaak wrote:

Andrew Poelstra wrote:


There is nothing on the command line except for the
string "Segmentation fault".


Fixed in 0c2f7e77.


Nice!

You beat me write a bug report at launchpad! :-))

---<)kaimartin(>---
Thanks for the quick fix!  I have observed a similar crash before 
without hierarchical netlists, but I can't reproduce at the moment.  I'd 
suggest going ahead and put in the bug report with the fix so that we've 
got a record of a bug and it's fix for future reference.


-Ethan


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Re: gEDA-user: PCB segfaults on click in netlist window

[Ethan Swint]

   On 07/17/2011 07:04 PM, Kai-Martin Knaak wrote:

Hi.
With my current project PCB sefaults reproducably. It crashes when
I click on one of the node items on the right column of the netlist
window. Curiously, everything is fine if I click on the right column
for the first time in a session. The cross hair jumps to where the
node happens to be on the canvas and everything looks fine. But when
I try this trick again (with a different node), PCB segfaults
instantly. There is nothing on the command line except for the
string "Segmentation fault".

It does not seem to matter, which node I choose.
PCB from git-head shows the same behavior as v20100929 distributed by
debian/testing. I cannot reproduce with other layouts of mine, though.
My current is bit larger than usual. Size of the layout is 2.4 MB.
Probably larger than the list allows. I attached the netlist (53 kB)


   The most recent investigation was started by Russell Dill titled
   "gEDA-user: PCB invalid free with latest git".  Andrew Poelstra asked
   us to run valgrind on PCB.  Unfortunately, once the bug knew it was
   being watched, it didn't poke out it's head.  If you can capture the
   event on valgrind, that would be fantastic!
   -Ethan

Anyone else seen this? Is this a known bug?

---<)kaimartin(>---




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References

   1. mailto:geda-user@moria.seul.org
   2. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user


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Re: gEDA-user: pcb GL can't render stretched arcs

[Ethan Swint]

On 07/14/2011 11:23 PM, Andrew Poelstra wrote:

On Thu, Jul 14, 2011 at 08:50:10AM +0200, Igor Lopez wrote:

Check if point px,py is on rotaded elliptic arc:
1) Translate point to use ellipse center as origin,
Px = px-x
Py = py-y
2) Insert Px, Py in Eq1
  lval equal 0 ->  point is exactly on arc
  lval above zero ->  point is inside arc
  lval below zero ->  point is outside arc


The problem here is that the elliptical arc has nonzero
thickness (usually, if it is a drawn solder arc). So I
actually need to see if the point is /within a certain
radius/ of the arc.

For that I need the distance from the point to the arc,
or to draw a circle around the point and check if that
intersects the arc.

To do either one analytically looks like a 4th order
equation must be solved. So I am looking for cheap
iterative solutions, or approximations, instead.

If the point is within the arc's bounding box, transform the point's 
global coordinates into the arc's local (x: major axis, y: minor axis) 
coordinates.  Then the distance calculation is a no-brainer.


-Ethan


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Re: gEDA-user: PCB invalid free with latest git

[Ethan Swint]

On 06/23/2011 07:21 PM, Ethan Swint wrote:

On 06/24/2011 03:45 AM, Andrew Poelstra wrote:

On Wed, Jun 22, 2011 at 09:26:09PM -0700, Russell Dill wrote:

I was selecting a net when PCB crashed.


Has anyone else seen this? I can confirm
valgrind is unhappy but cannot produce a
crash.


Yes, I see it multiple times a day.  ;)
A bit more detail - I've seen this crash for a couple of years, but 
hadn't had anyone else reproduce it.  I last reported it a few days ago:

http://www.seul.org/pipermail/geda-user/2011-June/054585.html

-Ethan


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Re: gEDA-user: PCB invalid free with latest git

[Ethan Swint]

On 06/24/2011 03:45 AM, Andrew Poelstra wrote:

On Wed, Jun 22, 2011 at 09:26:09PM -0700, Russell Dill wrote:

I was selecting a net when PCB crashed.


Has anyone else seen this? I can confirm
valgrind is unhappy but cannot produce a
crash.


Yes, I see it multiple times a day.  ;)

-Ethan


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Re: gEDA-user: PCB: Silk and drill not shown properly in gerbv

[Ethan Swint]

   On 06/21/2011 10:06 PM, Andrew Poelstra wrote:

On Tue, Jun 21, 2011 at 09:59:51PM -0400, Ethan Swint wrote:

416ccb60d759cd0e4e27d230a2af01bcc9f3ccdc (22 May 2011 committed by
Krzysztof Kosciuszkiewicz: "hid/gtk: Cleanup conditional code
because GTK 2.12 is required now") produces correct output. I'll run
bisect on it and see if I can nail down which commit messes things
up for me.


Before you go to that much trouble, you might want to
check and see if my pcb-printf commit was the cause.

I see no problems, but my suspicion is that there is some
overflow error somewhere. Are you running a 32-bit system?


   I'm running 64-bit.  Here's the strange thing: compiling with git
   bisect, I always got a good gerber file output.  I created a fresh,
   clean slate:
   git clone git://git.gpleda.org/pcb.git
   Then I ran:
   git bisect start
   git bisect good 416ccb60d759cd0e4e27d230a2af01bcc9f3ccdc
   git bisect bad 6808e757496cca0347d92d72851d0c34ae31b532
   sh ./autogen.sh
   ./configure --disable-doc
   make
   ./src/pcb $FILENAME
   --export gerbers here in GUI--
   git bisect good
   and repeat from autogen.sh.  Every build came out good.  BUT - when I
   ran
   git bisect reset
   then re-compiled and ran according to the above commands, I'm back to
   bad gerbers!  I'll have to trouble-shoot more in the morning.  Thanks
   for helping me track this down.
   -Ethan


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Re: gEDA-user: PCB: Silk and drill not shown properly in gerbv

[Ethan Swint]

On 06/21/2011 09:37 PM, Ethan Swint wrote:

On 06/21/2011 08:24 PM, Ethan Swint wrote:

On 06/21/2011 04:56 PM, Andrew Poelstra wrote:
On Tue, Jun 21, 2011 at 02:03:04PM -0500, eswint.r...@verizon.net 
wrote:

I just finished up a board in PCB and expoerted my Gerber files. The
copper, mask, and paste layers look fine in gerbv, but the top and
bottom silk screens and the drill file are way out of line. There seem
to be silk-screen artifacts way out of the board outline (720 
inches in

the Y) and the drill file has all of the drills clustered around the
origin. I've posted a zip of a few Gerber layers and my PCB file if
someone has a moment to verify what I'm seeing.


What version of pcb are you using? What gerber options?

I can confirm that your gerber files are messed up, but
I cannot reproduce with the 2010-Sept release, or in the
latest source from this morning.

It has the same behavior on two machines, which are both running 
6808e757496cca0347d92d72851d0c34ae31b532 (commit by Andrew Poelstra 
on 12 Jun 2011, "convert gerber hid to use pcb-printf").
Forgot to mention that it is the default GUI options (copy-outline = 
none, name-style = fixed).
416ccb60d759cd0e4e27d230a2af01bcc9f3ccdc (22 May 2011 committed by 
Krzysztof Kościuszkiewicz: "hid/gtk: Cleanup conditional code because 
GTK 2.12 is required now") produces correct output. I'll run bisect on 
it and see if I can nail down which commit messes things up for me.


-Ethan




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Re: gEDA-user: PCB: Silk and drill not shown properly in gerbv

[Ethan Swint]

On 06/21/2011 08:24 PM, Ethan Swint wrote:

On 06/21/2011 04:56 PM, Andrew Poelstra wrote:

On Tue, Jun 21, 2011 at 02:03:04PM -0500, eswint.r...@verizon.net wrote:
I just finished up a board in PCB and expoerted my Gerber 
files.  The

copper, mask, and paste layers look fine in gerbv, but the top and
bottom silk screens and the drill file are way out of line.  
There seem
to be silk-screen artifacts way out of the board outline (720 
inches in
the Y) and the drill file has all of the drills clustered around 
the
origin.  I've posted a zip of a few Gerber layers and my PCB 
file if

someone has a moment to verify what I'm seeing.


What version of pcb are you using? What gerber options?

I can confirm that your gerber files are messed up, but
I cannot reproduce with the 2010-Sept release, or in the
latest source from this morning.

It has the same behavior on two machines, which are both running 
6808e757496cca0347d92d72851d0c34ae31b532 (commit by Andrew Poelstra on 
12 Jun 2011, "convert gerber hid to use pcb-printf").


-Ethan
Forgot to mention that it is the default GUI options (copy-outline = 
none, name-style = fixed).


-Ethan


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Re: gEDA-user: PCB: Silk and drill not shown properly in gerbv

[Ethan Swint]

On 06/21/2011 04:56 PM, Andrew Poelstra wrote:

On Tue, Jun 21, 2011 at 02:03:04PM -0500, eswint.r...@verizon.net wrote:

I just finished up a board in PCB and expoerted my Gerber files.  The
copper, mask, and paste layers look fine in gerbv, but the top and
bottom silk screens and the drill file are way out of line.  There seem
to be silk-screen artifacts way out of the board outline (720 inches in
the Y) and the drill file has all of the drills clustered around the
origin.  I've posted a zip of a few Gerber layers and my PCB file if
someone has a moment to verify what I'm seeing.


What version of pcb are you using? What gerber options?

I can confirm that your gerber files are messed up, but
I cannot reproduce with the 2010-Sept release, or in the
latest source from this morning.

It has the same behavior on two machines, which are both running 
6808e757496cca0347d92d72851d0c34ae31b532 (commit by Andrew Poelstra on 
12 Jun 2011, "convert gerber hid to use pcb-printf").


-Ethan


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Re: gEDA-user: gschem saving symbols

[Ethan Swint]

On 06/15/2011 10:10 PM, Kai-Martin Knaak wrote:

Josh Jordan wrote:


What I am trying to do is save symbols that were modified in the
schematic.  For instance, making a schematic and add a generic
capacitor.  Then add a value, footprint, partnumber and documentation.

This does not change the symbol but adds attributes to the instance
in the schematic.

If I want to change a generic symbol I'd:

1) copy and rename the symbol to some other place with some
external tool like the bash shell, or a file browser.


snip

4) save and quit.


Alternatively:

1) copy and rename the generic symbol to some other place.

snip

7) save [fs]

If you have symbols that are already modified with a bit of work behind 
them, locate them in the *.sch file with a text editor (search for 
refdes or description) and copy the symbol definitions to an empty 
file.  This may not work in some instances, e.g. you may need to choose 
'embed symbols' to get the full symbol definition in the sch file.


-Ethan


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Re: gEDA-user: help request: gnetlist not reading scm files

[Ethan Swint]

On 06/14/2011 05:27 PM, Stefan Salewski wrote:

On Tue, 2011-06-14 at 17:20 -0400, Ethan Swint wrote:

For some reason, when I call gnetlist, e.g.

gnetlist -g BOM2 asymmetric_3phs.sch -o bom.txt

it encounters an error:

Failed to read BOM2 scm file [/usr/share/gEDA/scheme/gnet-BOM2.scm]
Backtrace:
In current input:
 1: 0* (BOM2 "output.net")

:1:1: In expression (BOM2 "output.net"):
:1:1: Unbound variable: BOM2


The files are present and have read permissions.  I'm using the bundled
version in Fedora 14, geda-gnetlist-1:1.6.2-1.fc14 (x86_64).  Anyone
else run into a similar problem?

Thanks,
Ethan


Guess: try bom2 as advertised from
gnetlist -g help

If that does not help, then we have to wait for a reply from smart
people. I have no idea about the meaning of the error messages...
Doh!  caPitaliZation matters.  The correct backend is bom2, not BOM2.  
Thanks!



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gEDA-user: help request: gnetlist not reading scm files

[Ethan Swint]

For some reason, when I call gnetlist, e.g.

gnetlist -g BOM2 asymmetric_3phs.sch -o bom.txt

it encounters an error:

Failed to read BOM2 scm file [/usr/share/gEDA/scheme/gnet-BOM2.scm]
Backtrace:
In current input:
   1: 0* (BOM2 "output.net")

:1:1: In expression (BOM2 "output.net"):
:1:1: Unbound variable: BOM2


The files are present and have read permissions.  I'm using the bundled 
version in Fedora 14, geda-gnetlist-1:1.6.2-1.fc14 (x86_64).  Anyone 
else run into a similar problem?


Thanks,
Ethan


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Re: gEDA-user: PCB: crash on Find

[Ethan Swint]

On 06/12/2011 03:14 AM, Peter TB Brett wrote:

1) I can't locate the git command to tell you exactly what you have
checked out.

Use `git describe'.  Ideally, PCB should show the git version in
--version output, like gnetlist does if you're running unstable:

   $ gnetlist --version
   gEDA 1.7.0 (g09c6613)
   Copyright (C) 1998-2011 gEDA developers
   This is free software, and you are welcome to redistribute it under
   certain conditions. For details, see the file `COPYING', which is
   included in the gEDA distribution.
   There is NO WARRANTY, to the extent permitted by law.


Thanks, Peter.
pcb --verizion only puts out "1.99z"
Using git describe, my current version hash is 
'8b43834c988ea8075b79a55956db3f181a4ea560' on the branch 
'pcb+gl_experimental'.  Now - how do I need to build in order to catch 
the program state at the crash?


-Ethan


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gEDA-user: PCB: crash on Find

[Ethan Swint]

I compiled PCB from the GL repository a few days ago.  It looks great, 
however, it does crash quite frequently when I use 'F' to find a net's 
connections - no warnings, nothing when I invoke PCB from the command 
line.  I'd like to help pin down this bug, but I'm stymied by two things:
1) I can't locate the git command to tell you exactly what you have 
checked out.  I know it's been answered in the list before, but I 
haven't been able to locate it here or on the web.

2) What should my build configuration be to catch the crash?

Thanks,
Ethan


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gEDA-user: High voltage caps in small places

[Ethan Swint]

Interesting study sent to me by a friend - Johanson Dielectrics has a 
study posted to Digikey:
http://dkc1.digikey.com/us/en/tod/JohansonDielectrics/PCBDesign_NoAudio/High_Voltage_PCB_Design_for_Arc_Prevention_NoAudio.html 

Summary:  For high voltage (>1kVac), small (1206, 1808) caps, it's bad 
to leave soldermask between the terminals of the device, particularly in 
humid conditions.  Rounding the pads is beneficial on 1206, but not so 
much on 1808.  I wonder what materials are available for soldermask and 
if they have higher moisture resistance?  Is soldermask polyimide?


-Ethan


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Re: gEDA-user: Water proof panel connectors

[Ethan Swint]

On 06/08/2011 04:58 PM, Rob Butts wrote:

I have a water proof box with two volage sources inside.  I need a
power connector to be water proof that I can in the box and be water
proof.  It doesn't have to be submersible because it will be on the
back of my wheelchair but the more water proof the better.



Can anyone recommend one?



Thanks
How many connections are you looking to pass through?  There are some 
good water-resistant connectors for PV systems, e.g. Tyco SolarLok, that 
handle oodles of current, which you can pair with a water-tight 
glandular feed-through that fits in a standard knockout.  The advantage 
is that you have strain relief right at the box and the connector can go 
in another location where the rigid section is not a problem.  Or, if 
you don't need to make/break the connection frequently, the wire can go 
straight into the box without any connector.


-Ethan


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Re: gEDA-user: import schematics with local footprints

[Ethan Swint]

On 06/06/2011 08:25 PM, Kai-Martin Knaak wrote:

DJ Delorie wrote:


If you're using File->Import, gnetlist is not looking at the libraries
at all.  Only PCB is, so you just need to teach PCB how to prefer your
libraries over the system ones.

My library string in preferences does not mention the default libs
at all. It currently reads:
~/geda/footprints:./packages:.

So how would I teach PCB to prefer them?
Besides, my aim is not only prefer my libs, but use them exclusively.

---<)kaimartin(>---

I've got the line
(component-library-search "/../../footprints")
in my gafrc file.  Does that set a priority?

-Ethan


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Re: gEDA-user: Hierarchy help

[Ethan Swint]

On 06/06/2011 11:13 PM, John Doty wrote:

On Jun 6, 2011, at 12:13 PM, Ethan Swint wrote:


OK- I've been messing around with hierarchy for the first time, but I'm a bit lost.  I've 
got an asymmetric phase leg inverter with three phases, for which I was planning to use 
hierarchy to make updating components more resistant to operator error.  I have a sub-sch 
file and a symbol file and it works as it should, for which I followed the 
"gTAG" example that ships with gEDA.

My problem then comes when I try to create the PCB.  Components there take on the refdes "A/D?", as 
opposed to "A/D1", "A/D2", etc.  I did run across 
http://www.bourbonstreetsoftware.com/GEDABlocks.html, but I was hoping to find something a bit more 
automatic.  My Bing-fu and Google-fu have failed me, as well.

My gnetlistrc file consists of:
(hierarchy-netattrib-mangle "disabled")
(hierarchy-netname-mangle "disabled")
(hierarchy-uref-mangle "disabled")

Well, with those settings in gnetlistrc, you've turned off the renaming of nets 
and components in the subcircuits. So all of the components are duplicated 
between similar subcircuits, and all nets are shorted between similar 
subcircuits.

Use (hierarchy-netattrib-mangle "disabled") only if *every* net named in a net= 
attribute should be global. Otherwise, such nets are local, and you'll have to connect 
them explicitly between levels if that's required.

Use (hierarchy-netname-mangle "disabled") and (hierarchy-uref-mangle 
"disabled") only if *every* subcircuit has distinct schematics.

John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
j...@noqsi.com
Thanks for the pointers from you and Griessen.  I emptied the gnetlistrc 
file - it is now working.  The troubling thing is I *thought* I had 
tried that first and that it didn't work properly.


Is the best place to find the gnetlistrc documentation in the source files?

Too bad for the new moderation requirement - it really lowers the 
bandwidth on help!


-Ethan


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gEDA-user: Hierarchy help

[Ethan Swint]

OK- I've been messing around with hierarchy for the first time, but I'm 
a bit lost.  I've got an asymmetric phase leg inverter with three 
phases, for which I was planning to use hierarchy to make updating 
components more resistant to operator error.  I have a sub-sch file and 
a symbol file and it works as it should, for which I followed the "gTAG" 
example that ships with gEDA.


My problem then comes when I try to create the PCB.  Components there 
take on the refdes "A/D?", as opposed to "A/D1", "A/D2", etc.  I did run 
across http://www.bourbonstreetsoftware.com/GEDABlocks.html, but I was 
hoping to find something a bit more automatic.  My Bing-fu and Google-fu 
have failed me, as well.


My gnetlistrc file consists of:
(hierarchy-netattrib-mangle "disabled")
(hierarchy-netname-mangle "disabled")
(hierarchy-uref-mangle "disabled")

What obvious thing (or reference material) am I missing?

Thanks,
Ethan


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Re: gEDA-user: gnetlist

[Ethan Swint]

On 05/30/2011 09:35 PM, John Doty wrote:

On May 31, 2011, at 6:35 AM, John Griessen wrote:


I'd like the first definition
of what gnetlist does be, "Output any data it takes in, in the same format,
with lost spatial position information allowed, but keeping all other data 
intact."

I think the reader should preserve *all* of the information in a .sch file. 
There are several reasons:

1. Net connectivity depends on spatial information. But one approach doesn't fit all 
needs here. Right now, we have a simple minded netlister that reduces the net geometry in 
the schematic to a netlist model in which a net is topologically a single point. But 
suppose we start putting attributes on net segments ("this segment must carry 
10A")? Shouldn't a back end for a layout tool that can handle this be able to see 
this, figure it out?
+1 from me.  Gate drive sub-circuits in power designs come to mind, as 
well as Kelvin connections.



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Re: gEDA-user: file format documentation formatting in the wiki

[Ethan Swint]

On 05/25/2011 06:22 PM, Kai-Martin Knaak wrote:

Krzysztof Kościuszkiewicz wrote:


On Wed, May 25, 2011 at 05:04:04PM +0200, Felix Ruoff wrote:

I like this idea!

Had the same problem few times...

+1


done.

---<)kaimartin(>---
$0.02 request/opinion from me: a keyword, rather than a number, so that 
arguments can be optional and more-human readable?



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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

[Ethan Swint]

On 04/10/2011 04:55 PM, Andrew Seddon wrote:

I am exploring the idea of using the Scalable Vector Graphics standard
as an EDA format.

https://github.com/seddona/svgparts

Would be interested in your thoughts, there's a little more
explanation on my blog.

You might want to check out Fritzing (fritzing.org).  It targets 
non-EEs, but they have all of their graphics in SVG.




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Re: gEDA-user: PCIe x1 connector footprints

[Ethan Swint]

On 03/08/2011 11:04 PM, Darrell Harmon wrote:

On Tue, Mar 8, 2011 at 6:04 PM, Stephen Ecob
  wrote:

I'm looking for PCIe x1 footprints, both card and motherboard sides.

Ethan Swint posted PCIe x4 footprints to this list in February 2009,
my current plan is to reduce these down to PCIe x1.
Has anyone used Ethan's footprints ? It'd be nice to know if they've
been fabbed and loaded successfully, or if anyone has improved them in
some way.

BTW thanks for posting the x4 footprints Ethan!
You're welcome!  I used the x4 footprints successfully where I bevelled 
the card edges with a flat file.  Not gold plated, but they worked well 
enough.  I might have made a change to the footprint after posting to 
include the outline - I have two versions of the footprint on the card 
edge connector, but I don't remember which one I ultimately used.  The 
MX... is the Molex part number.


-Ethan


PCIEx4_fingers.fp
Description: application/pcb-footprint


MX877159108_fingers.fp
Description: application/pcb-footprint


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Re: gEDA-user: General Layers questions

[Ethan Swint]

On 02/24/2011 06:35 PM, Colin D Bennett wrote:

I agree that color does not belong in the layout file.  I may keep
changing my preferences on my pcb color theme, but I don't want to
update all my layout files to take advantage of an updated color theme
-- UI preferences like color theme should definitely not be included in
the .pcb layout file itself.  Also consider collaborative work with
other users who might prefer different colors than you.
OK, that is your preference - but that's no reason to prohibit someone 
else from including color information in their layout.  There just needs 
to be a method to quickly (i.e. 1-click) change an offensive color 
scheme to your preferred, in-editor, scheme.



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Re: gEDA-user: PCB+GL instructions

[Ethan Swint]

On 02/20/2011 09:32 PM, Kai-Martin Knaak wrote:

Ethan Swint wrote:


I was expecting just to get back "git
clone -o pcjc2 git://repo.or.cz/geda-pcb/pcjc2.git" or some such, but in
response Peter has posted what looks to be an excellent guide to his
blog at

http://pcjc2.blogspot.com/2011/02/pcbgl-repository-instructions.html


Is it just me, or is anyone else also having a speed issue with Peters
blog? Scrolling takes about two seconds to jump by a screen...
(My browser is epiphany, the default with debian)

---<)kaimartin(>---
Fairly slow scrolling on Firefox 3.6.13 on Fedora, but it seems faster 
in the sections without images.  I looked at a few of the images and 
they all seem to be >150kB, even though they are pretty small 
pixel-wise.  Much slower scrolling than other web sites.


-Ethan


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gEDA-user: PCB+GL instructions

[Ethan Swint]

I sent a private email to Peter Clifton as I was (yet again) having 
trouble finding the list message outlining his work, where to pull it, 
and what branch to check out.  I was expecting just to get back "git 
clone -o pcjc2 git://repo.or.cz/geda-pcb/pcjc2.git" or some such, but in 
response Peter has posted what looks to be an excellent guide to his 
blog at


http://pcjc2.blogspot.com/2011/02/pcbgl-repository-instructions.html

Many thanks Peter!

-Ethan


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Re: gEDA-user: Help I can move by REFDES

[Ethan Swint]

On 02/19/2011 09:51 PM, Ethan Swint wrote:

On 02/19/2011 09:41 PM, Oliver King-Smith wrote:

I have managed to get my refdes for one component about 7" away from
the component.  When I select the refdes I can seem to move it.  
How do

I get it back to my poor component?
Oliver
To move a refdes in the GUI, 1) make sure that it is not currently 
selected 2) click over refdes and drag to desired location.
In a text editor, just manually set the XY coordinate of the refdes to 
0 0 (http://pcb.gpleda.org/pcb-cvs/pcb.html#File-Syntax).

More specifically, http://pcb.gpleda.org/pcb-cvs/pcb.html#Element-syntax


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Re: gEDA-user: Help I can move by REFDES

[Ethan Swint]

On 02/19/2011 09:41 PM, Oliver King-Smith wrote:

I have managed to get my refdes for one component about 7" away from
the component.  When I select the refdes I can seem to move it.  How do
I get it back to my poor component?
Oliver
To move a refdes in the GUI, 1) make sure that it is not currently 
selected 2) click over refdes and drag to desired location.
In a text editor, just manually set the XY coordinate of the refdes to 0 
0 (http://pcb.gpleda.org/pcb-cvs/pcb.html#File-Syntax).



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Re: gEDA-user: OT: Vintage uP

[Ethan Swint]

Stephan-

Here's what I've got in the Motorola family:
MC68010L8 - 1 unit
SC87876L8 - 1 unit
MC68000P8 - 2 units
MC68000P10 - 2 units

These are all 64-pin devices; I'm not sure about the SC87876.  It looks 
like shipping is reasonable - USD$13.25 for a DVD-sized box.


Regards,
Ethan

On 02/13/2011 05:57 PM, Stephan Boettcher wrote:

Ethan,

Ethan Swint  writes:


I recently ran across a cache of 'vintage' microprocessors - a
Motorola MC68010L8 and other MC68K chips, Dallas Semi Speed it uP, AMD
8088, etc.  The are all in new condition, most in ESD foam.  Any of
these of interest to the list?

Well, if you could ship to Europe in an unsusicious package to avoid
customs excessive duties, I'd be interested in an MC68010L8 and maybe
other MC68K chips (what are those? UART? FPU?)  I could pay via paypal.

Cheers, Stephan


Regards,
Ethan




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Re: gEDA-user: OT: Vintage uP

[Ethan Swint]

On 02/12/2011 03:23 PM, Dave McGuire wrote:

   Are you selling them, giving them away, or what?

-Dave

Average listing price on eBay is ~$15/ea, with up to $50 for the 
MC68010L8's.  As for selling price, I don't know.  If there's not much 
interest, then I'd be willing to send them on for the price of postage.


-Ethan


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Re: gEDA-user: OT: Vintage uP

[Ethan Swint]

I did look at a couple and they seem to look OK, but I'll check them 
carefully.  Thanks for the warning!


On 02/11/2011 09:18 AM, Bob Paddock wrote:

most in ESD foam.

Check the leads.
Long term storage, years, in some ESD foam will actually eat away the leads.
Been-there-done-that. :-(


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gEDA-user: OT: Vintage uP

[Ethan Swint]

I recently ran across a cache of 'vintage' microprocessors - a Motorola 
MC68010L8 and other MC68K chips, Dallas Semi Speed it uP, AMD 8088, 
etc.  The are all in new condition, most in ESD foam.  Any of these of 
interest to the list?


Regards,
Ethan


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Re: gEDA-user: Question about using slots in .sym files

[Ethan Swint]

On 12/16/2010 10:31 PM, DJ Delorie wrote:

Select one of them and do Edit->Slot.  Change the slot and the pin
numbers will change too.
I always make the slot a visible attribute, both name and value, to make 
it a bit more obvious that it is a slotted part.  Also - watch out if 
you auto-assign refdes, as slots you wish to be on the same component 
can get renumbered or grouped contrary to your wishes.


Regards,
Ethan


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Re: gEDA-user: PCB: coordinates and angles of the components

[Ethan Swint]

On 12/02/2010 12:40 PM, DJ Delorie wrote:

Yes, but as I pointed out earlier, it doesn't do what I want. It averages the
coordinates of the pins/pads, and it is not good when you working with
asymmetric element such as SOT223.

So change it :-)


Could you pinpoint the function/source file?  I should be able to knock 
out something pretty quickly - the centroid would be the center of the 
bounding box, which is already implemented elsewhere in PCB, IIRC.





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Re: gEDA-user: PCB: coordinates and angles of the components

[Ethan Swint]

On 12/01/2010 04:53 AM, Kovacs Levente wrote:

On Wed, 01 Dec 2010 01:58:06 +0100
kai-martin knaak  wrote:


Is the goal you achieve a common one? If so, can the script be
included in the distribution of pcb in some way, please? It would
spare other users the need to reinvent the wheel.

This is a good question. Well, I made a few scripts in the past. They are
here:

http://git.logonex.eu/?p=utils4geda.git;a=tree

If someone thinks that some of them are worth distributing along with
gEDA/PCB, then it can be downloaded from here.

However, I don't think they should go with PCB. Instead I'd create a PCB
goodies package, which would be full of scripts, and user contributed stuff.

Even, it would be enough to have a web page full of user contributed links.

Just my EUR 0.02

Note that the script now outputs the placement side of a particular element as
well.

Levente

Sorry for my late reply - but have you tried the BOM export (File -> 
Export Layout->BOM).  One of the output files from that is an XYRS (X, 
Y, Rotation, Side) text file.


http://archives.seul.org/geda/user/Feb-2009/msg00351.html

-Ethan


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Re: gEDA-user: Functional blocks and PCB format changes

[Ethan Swint]

On 09/13/2010 09:57 PM, Ouabache Designworks wrote:

  pin:
   pinNumber: 2
   pinName: "rst"
   x1: 1234
   y1: 4321
   x2: 2345
   y2: 4321
   layer: component
  or
  2"rst"<\pinName>1234<\x1>4321<\y1>2345<\x2>5432<\y2>component<\layer><\pin>
  I call the second large, bloat, and ugly.
   

I would prefer

rectangle:
type: pin
pinNumber: 2
pinName: "rst"
x1: 1234
y2: 4321
x2: 2345
y2: 4321
layer: component

or


pin
  2<\pinNumber>
  rst
<\type>
  ref92134<\basepos>

  1234<\x>
  4321<\y>
<\loc, ID = 12360>

  <\x>
  0<\y>
<\loc>
<\rectangle>

I'm not exactly sure how the referenced position will work out in XML or the 
first format (yaml?).  Time for me to leave the house - so I'm not sure how 
correct any of this is.




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Re: gEDA-user: Functional blocks and PCB format changes

[Ethan Swint]

XML is far too heavy, agreed, and it's signal-to-noise ratio is abysmal.
I think that using a Lisp (or Lispy-looking) format would be extensible,
easy to parse, and make the most people happy.
   

Allow me to toss out JSON.  It is about as light weight as using S-EXP,
...else along those lines anywhere else.

 

The problem I have with JSON (and to some extent, Lisp) is that it is
not self-documenting. You can't open a JSON document and immediately
see what everything is and what it does; it just looks like gibberish
and brackets.

Also, it doesn't require a consistent newline scheme.
   
Every time I run against it, I'm still in disbelief that, in this era, 
some of our most powerful and useful tools are restricted to one 
character for parsing, and that one character is furthermore restricted 
to newline!



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Re: gEDA-user: next PCB release - 1.99za vs 4.0

[Ethan Swint]

On 09/12/2010 03:17 PM, Windell H. Oskay wrote:

On Sep 12, 2010, at 10:35 AM, Bob Paddock wrote:

   

Well, a both-sides silkscreen layer makes little sense.
   

Actually it does make sense.  Think about a transformer with through-hole pins.
You want the top silk to show the courtyard, for clearances.  You want
the bottom silk to show the pin numbers/labels.

+10.  Obvious, important feature.

Most of my boards have silkscreen on both sides.  Every major fab shop supports 
it. We should too.
   
I think he is referring to a single silkscreen that printed on both top 
and bottom.



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Re: gEDA-user: next PCB release - 1.99za vs 4.0

[Ethan Swint]

On 09/11/2010 07:07 PM, Bob Paddock wrote:

  (Can someone who uses / has used keepouts on another package
  describe
  for me how they work, or how you use them?)

In Protel there is a keep-out layer.  A object, square, polygon etc, on
that layer prevents traces from being run through that area, either
manually or by the auto-router (which sucks so bad I never use it).
   
Hmmm... Can we have multiple keep-outs for a single copper layer, e.g. 
digital keepout, analog keepout, HV keepout?  That would be very 
useful!  (Or maybe more appropriate to say "keep-in".)



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Re: gEDA-user: next PCB release - 1.99za vs 4.0

[Ethan Swint]

On 9/8/2010 4:37 PM, DJ Delorie wrote:

Yes, but if you read the previous message, DJ assumed that "allows"
meant "requires".

To reiterate my position on that: I don't mind the "use a text editor"
solution.  My concern is editing it *while* PCB is *also* editing it
The reason I don't close down PCB is that it's a pain to close down PCB, 
then open it again, position the window where you want it, resize the 
PCB window, move the status box where you want it, close the library, 
etc., particularly when you make a small tweak and want to visualize it 
several times in a row.



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Re: gEDA-user: next PCB release - 1.99za vs 4.0

[Ethan Swint]

On 9/8/2010 11:38 AM, John Griessen wrote:

On 09/08/2010 01:09 AM, DJ Delorie wrote:


I'm keeping all the emails at least...


The last time we were talking blue sky features I made a list on a wiki,
and did not notice anyone else adding to the wiki.  Was it read?  Did 
it help?



Link please?  I'll edit!


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Re: gEDA-user: next PCB release - 1.99za vs 4.0

[Ethan Swint]

On 09/07/2010 08:50 PM, DJ Delorie wrote:

Surely in 2010 there is a portable non-polling way to get file update
notification?
 

More than one, I think...

But any design that requires you to edit files behind pcb's back, is bad.
   
I text-edit PCB files on every single board I do... arcs are the most 
blatant example.  Other things I do where it's easier to text edit 
rather than to look up/create a command in PCB:
*connect vias to polygons as a workaround for not being able to 
associate polys with a net, i.e. I search & replace  '"found"' for 
'"thermal(1x,2x),found"'.

*change multiple trace segments to a desired numerical width
*change clearances on multiple pins/pads to a desired numerical value
*change the min size of via holes or soldermask openings 
(tented/cleared) when I've forgotten to change the defaults to my 
projects requirements at the start
*create/modify footprints where a given numerical value is desired 
(concurrently performing sanity-check in PCB)



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Re: gEDA-user: next PCB release - 1.99za vs 4.0

[Ethan Swint]

On 09/07/2010 08:28 PM, Mark Rages wrote:

* Ability to edit netlist in-situ (possibly by drawing on the rat lines
layer) - e.g, when you want to add a heatsink soldered to ground, it will
always show up as shorted until the netlist is edited to incorporate it.
 

A desirable feature, but drawing on rat lines seems less useful to me
than just popping a text editor and editing the netlist directly.
   
Too true - but it can cause quite a fuss when you reload the file in the 
wrong window.  How about having PCB (and gEDA, too, FTM) scan the file's 
timestamp periodically and alert the user when the file has been 
overwritten?




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Re: gEDA-user: PCB format wishlist

[Ethan Swint]

On 09/06/2010 04:32 PM, DJ Delorie wrote:

Or, could we base everything off of lines, attach a 'curvature'
property to create arcs, and build polygons from that.

Arcs can be simulated with many short lines, so the only primitive we
need are lines.  Of course, if "line" is a two-point polygon, then the
only primitive we need is polygons.
   
I don't really like the idea of 'simulating' arcs - it uses a *lot* of 
information to approximate what you are trying to do.  My preference 
would be to keep an arc as a primitive type.

A point is just a line that starts and ends at the same coordinates.
   
Not really - a line that starts and ends at the same coordinate looks 
like a point, but it isn't.  That presently causes us problems with 
square pads.  I think I remember some issues with approximations of a 
point using traces, too?



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Re: gEDA-user: PCB format wishlist

[Ethan Swint]

On 09/06/2010 04:54 PM, DJ Delorie wrote:
   

Yes. Build higher-level objects by composition, not merely by
listing.
 

I was arguing for the opposite - separate the compositing from the
grouping, so that when you *do* group, you mostly just list.

Even internally to PCB, I'd want to keep "exemplar" composites as a
library called by reference, so if you edit one pin of an IC, by
default you end up editing all the same-shape pins (usually what you
want when you're changing drill or annulus, for example) with the
option to make the pin unique so you can change it separately.
   
Yes - but I'd also like to be prompted to answer the question 'Do you 
want this change to 1) apply to all instances of object X; 2) do you 
want to modify this one instance of object X to derive object Y with 
some inherited characteristics; or 3) do you want to make an independent 
object Z which starts out with parameters identical to X?'



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Re: gEDA-user: PCB format wishlist

[Ethan Swint]

On 09/06/2010 04:27 PM, Levente Kovacs wrote:

On Mon, 6 Sep 2010 12:57:59 -0700
Andrew Poelstra  wrote:

   

Or, could we base everything off of lines, attach a 'curvature'
property to create arcs, and build polygons from that.
 

I woldn't do that. The file would end up consisting of the same stuff. It's
like you could only have points.

I think we should define primitives as the most commonly used shapes in pcb
layouts.

I prefer

   line,
   polygon,
   circle,
   arc.

Why arc and circle are not merged? Because the diameter of the arc is the
center of the bent line; however, the diameter of a circle is the edge.

And of course we have to implement padstacks at the footprint level.
   
What do you consider the 'footprint' level?  If the 'footprint' is 
defined the base object of a group of arbitrary elements, then the 
ability to define footprints with arcs, pad stacks, etc. comes quite 
naturally, as a combination of #2 and #5 of the original list of 
qualities I proposed:


2) Footprint re-use: reduce file size by having components refer to a 
'base' component with XYRS information, make component tweaking 
easier. Say you wanted to change all your 0603 resistors - it's easier 
to change the fundamental component, rather than the present case of 
to modifying individual components in all of their rotations. 
5) Ability to lock any portion of the location coordinate, either in 
absolute or relative to another entity (line segment locked to 
pin/pad, components locked to the same Y coordinate, etc) - rather 
than just specifying an absolute coordinate. 





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Re: gEDA-user: PCB format wishlist

[Ethan Swint]

On 09/06/2010 11:59 AM, Kovacs Levente wrote:

I'd add a capability of storing net information along with lines, polygons,
vias, and other copper objects. It would then make it unnecessary to have the
"new lines arcs clear polygons" stuff. A line in a polygon with the same
net wouldn't clear.

Levente

Hmm... this could be incorporated into
4) DRC re-use: refer to a 'base' DRC rule, rather than re-describing 
the DRC at every instance.  DRC rules could be arbitrarily complex or 
simple, e.g. elements in DRC class '250V' must have a 0.050" clearance 
from class '5V', but can have 0.010" clearance within '250V', or 
something along the lines of the 'skinny, normal, fat, power' we have 
in place now. 
A 'net' could be specified by a class/group of elements within which the 
DRC clearance would be 0 and probably the minimum intersection between 
two elements would be enforced as the minimum width for that group.  If 
elements are tagged with a net ID, including polygons, then that would 
still take care of the 'new lines & arcs clear'.




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Re: gEDA-user: PCB format wishlist

[Ethan Swint]

First grow up, you are the one crying

And here is the solution for making the version control with git understand a 
zipped pcb file.

http://the-gay-bar.com/2010/06/23/managing-zip-based-file-formats-in-git/

In summary you tell git that to diff the file it needs to me unzipped first.

Steve
   
Woah... I intended this thread for *what* we want to put in the file 
format to allow one to easily assign relationships between and 
characteristics of elements.  I was trying to shift the focus away from 
awk, ruby, other program's file formats.  I re-submit my original list:


1) Better angle support: include rotation (in degrees, 
rotation/translation matrix, whatever) as a location argument instead of 
altering the pad/pin/silk/refdes/whatever location data separately
2) Footprint re-use: reduce file size by having components refer to a 
'base' component with XYRS information, make component tweaking easier. 
Say you wanted to change all your 0603 resistors - it's easier to change 
the fundamental component, rather than the present case of to modifying 
individual components in all of their rotations.
3) Connectivity information: include the connection information between 
line segments, similar to (but not necessarily exactly!) SVG format, 
where multiple points and arcs can be included in one line.
4) DRC re-use: refer to a 'base' DRC rule, rather than re-describing the 
DRC at every instance.  DRC rules could be arbitrarily complex or 
simple, e.g. elements in DRC class '250V' must have a 0.050" clearance 
from class '5V', but can have 0.010" clearance within '250V', or 
something along the lines of the 'skinny, normal, fat, power' we have in 
place now.
5) Ability to lock any portion of the location coordinate, either in 
absolute or relative to another entity (line segment locked to pin/pad, 
components locked to the same Y coordinate, etc) - rather than just 
specifying an absolute coordinate.





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Re: gEDA-user: PCB format wishlist

[Ethan Swint]

On 09/04/2010 10:19 PM, Andrew Poelstra wrote:

I have one more suggestion: the facility to create recursive PCBs.
What this will look like in the file format, I dunno. But we should
keep it in mind.
   
Recursive PCBs could work the same way as the footprint re-use: a node 
could contain a reference to a parent node; the parent node could be a 
single element or itself a reference to a collection of elements.



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Re: gEDA-user: PCB format wishlist

[Ethan Swint]

On 09/04/2010 10:04 PM, Andrew Poelstra wrote:

3) Connectivity information: include the connection information
between line segments, similar to (but not necessarily exactly!) SVG
format, where multiple points and arcs can be included in one line.
 

I'm not sure what you're getting at here. I think the rule of least
surprise dictates that line segments be line segments, since that is
how they are manipulated.
   
If you are familiar with mechanical CAD packages, they would be called 
'polylines': connected line segments/arcs which otherwise have the same 
characteristics.  I often find myself editing the PCB file in a text 
editor and it's a real pain to find connected traces, as they are 
scattered over the entire file.

5) Ability to lock any portion of the location coordinate, either in
absolute or relative to another entity (line segment locked to
pin/pad, components locked to the same Y coordinate, etc) - rather
than just specifying an absolute coordinate.
 

More generally, we should support creating "groups" of components
that can be transformed and manipulated as a collection. However,
I'm not sure how much functionality this would give on top of the
functional-block proposal.
   
This idea encompasses a component group: the XYRS data of each of these 
components would be locked to a 'base' component.  When the base 
component is moved, all of the components are moved.




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gEDA-user: PCB format wishlist

[Ethan Swint]

In parallel to how we want to implement the PCB file format, why don't 
we have a separate thread on *what* we want to implement?  I'll propose 
the following as a starting point:


1) Better angle support: include rotation (in degrees, 
rotation/translation matrix, whatever) as a location argument instead of 
altering the pad/pin/silk/refdes/whatever location data separately
2) Footprint re-use: reduce file size by having components refer to a 
'base' component with XYRS information, make component tweaking easier. 
Say you wanted to change all your 0603 resistors - it's easier to change 
the fundamental component, rather than the present case of to modifying 
individual components in all of their rotations.
3) Connectivity information: include the connection information between 
line segments, similar to (but not necessarily exactly!) SVG format, 
where multiple points and arcs can be included in one line.
4) DRC re-use: refer to a 'base' DRC rule, rather than re-describing the 
DRC at every instance.  DRC rules could be arbitrarily complex or 
simple, e.g. elements in DRC class '250V' must have a 0.050" clearance 
from class '5V', but can have 0.010" clearance within '250V', or 
something along the lines of the 'skinny, normal, fat, power' we have in 
place now.
5) Ability to lock any portion of the location coordinate, either in 
absolute or relative to another entity (line segment locked to pin/pad, 
components locked to the same Y coordinate, etc) - rather than just 
specifying an absolute coordinate.


We might not be able to use this flexibility until PCB's internals are 
modified, but the ability will be there, waiting to be tapped.



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Re: gEDA-user: crosshair snaps to pins and pads... on locked component

[Ethan Swint]

I just can't figure out why can't the "Crosshair snaps to pins/pads" work when
the component is locked. As far as I know, locking a component is for to lock
the position of the component.

What a coincidence.  We were just discussing that on IRC.

I think snap-to-locked is OK, but I want locked *elements* to be
ignored.  I have one design that has a big LCD covering up all my
other parts, it's really hard to edit when every operation tags the
LCD instead of the parts under it.
How about snapping to pads on the far side?  That can get pretty 
annoying for me.  I want to see pads on the other side so I know where I 
can place vias, but I don't want to snap to them.



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Re: gEDA-user: "click on zoom focus"

[Ethan Swint]

Dave-

Is your behavior triggered by the same event that I describe?  I've 
encountered this bug in multiple versions of PCB on Fedora 10-13, distro 
repository and compiled from git head.  You are only other person on 
this list that I've seen that has encountered the bug.


-Ethan

On 07/23/2010 08:01 PM, David McQuate wrote:

Thanks for your reply.

 That's the first thing I did, of course, but "nothing happens".

I've tried clicking, double-clicking, click-and-drag, mouse button 
combinations, shift / control / alt click.
Nothing seems to bring the menus and buttons back from their 
grayed-out inactive state.


The mouse cursor still moves, and pauses at via centers, etc. and the 
cursor changes from an arrow to a small, fancy
square.  The mouse wheel does change the zoom level.  All this works, 
but the menus and buttons remain deactivated.


Dave

DJ Delorie wrote:

In the status line at the bottom, it says, "click on zoom focus".


So click somewhere on the pcb to tell it where to zoom in on.


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Re: gEDA-user: "click on zoom focus"

[Ethan Swint]

On 07/23/2010 06:09 PM, David McQuate wrote:
PCB gets into a state in which all menus and buttons are grayed out, 
and therefore not active.

In the status line at the bottom, it says, "click on zoom focus".
I get that when I am working with two programs open.  If the other 
window has focus, but I scroll with the mouse wheel over PCB, menus and 
buttons gray out and do not return.


What is it looking for?
How do I get it out of this state? (eg so I can save the layout)

I exit anyway, and it prompts to save if there are changes.

Regards,
Ethan


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Re: gEDA-user: "click on zoom focus"

[Ethan Swint]

This is a re-send... the first message hasn't posted after almost an hour!

On 07/23/2010 06:09 PM, David McQuate wrote:

PCB gets into a state in which all menus and buttons are grayed out,
and therefore not active.
In the status line at the bottom, it says, "click on zoom focus".
I get that when I am working with two programs open.  If the other 
window has focus, but I scroll with the mouse wheel over PCB, menus and 
buttons gray out and do not return.


What is it looking for?
How do I get it out of this state? (eg so I can save the layout)

I exit anyway, and it prompts to save if there are changes.

Regards,
Ethan


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Re: gEDA-user: Fab, Pick and Place, Stencil

[Ethan Swint]

On 04/27/2010 04:52 PM, DJ Delorie wrote:

For pick-n-place, do a BOM export.  It has an X-Y option.
   

Is there a theta?


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Re: gEDA-user: Drill file zero suppression

[Ethan Swint]

On 04/27/2010 12:44 AM, Dan McMahill wrote:

Ethan Swint wrote:

On 04/26/2010 01:58 PM, DJ Delorie wrote:

What generated those files?  PCB uses *.cnc for drill files...



>
> It's original format is PADs, I believe.
>

be aware that there are various combinations of # of significant 
digits and leading/trailing zero suppression which can be generated by 
various programs that don't strictly conform to the specified subset 
in the excellon documentation.  Also some programs, and I think pads 
may be one, has options that let you use a different origin for the 
drill file.  I call it the "please increase the risk of a bad board" 
option ;)


With gerbv, you can turn off autodetection of drill formats and 
manually specify what the format is as well as an offset.  By playing 
with those settings you'll probably be able to clearly see when you 
have them set right.
OK - thanks for the input!  I'll have to see about customizing the drill 
format.


-Ethan


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Re: gEDA-user: Drill file zero suppression

[Ethan Swint]

It's original format is PADs, I believe.

On 04/26/2010 01:58 PM, DJ Delorie wrote:

What generated those files?  PCB uses *.cnc for drill files...


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gEDA-user: Drill file zero suppression

[Ethan Swint]

A quick sanity check with users: I've got some Gerbers and a drill file 
to review.  The drill file (*.drl), however, is not drawn to the same 
origin as the other layers.  Also, there are leading zeros on some of 
the hole locations, e.g.


T12C.145F035S9
X-01Y-01
X-01Y01
X01Y01
X01Y-01

which should be holes located at [+/-1.000",+/-1.000"].  I talked to one 
board house, but the conversation had so many double negatives (along 
the lines "We don't prefer to not have zeros suppressed.") that I'd like 
to check in here.


Thanks,
Ethan


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Re: gEDA-user: PCB template?

[Ethan Swint]

Jim wrote:
I am designing a couple of boards (if successful more than 2) that 
have the same "form factor".  That is they are the same physical size 
and both (all) have fingers to plug into a card slot on a mother 
board.  So I don't have to worry about registration of the fingers 
each time I come up with a new board, is there a way I can define a 
PCB template that includes the fingers?  That seems like it would be 
hard to do since the fingers are a connector on the schematic and 
wouldn't line up right without some tricks.  The other option might be 
if there were a command line to PCB that I could execute to tell it 
"put pin 1 of conn1 at X, Y".  Or would it be best to have a template 
that has a target in silk to line the fingers up?

I'm open to the simplest solution.
Make a board with only the connector loaded, at the desired position.  
When you would like to lay out a new board, copy & rename the "template" 
file, renumber the connector, then run gschem2pcb.  It will make an 
additional .pcb file that you can then "load layout data from file". 


-Ethan
<>

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Re: gEDA-user: im new, soy nuevo

[Ethan Swint]

On 04/16/2010 04:42 AM, Miguel Sánchez de León Peque wrote:

Hi Luis,
I live in Spain, so we wont have problems with the language ;-). The
only thing I suggest you is to write us personal emails instead of
using geda-user list if you write in spanish :-)
---
--
   

Por favor, escribe en Espanol!  Algunas quiere practicarlo.

Please, write in Spanish!  Some of us want to practice it.  (And need 
to, as you can tell!)


The dual English/Spanish posts are quite helpful.

-Ethan


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Re: gEDA-user: OT: Looking for DSP

[Ethan Swint]

Thanks!

On 03/24/2010 03:36 PM, Gabriel Paubert wrote:

On Wed, Mar 24, 2010 at 10:30:00AM -0400, Ethan Swint wrote:
   

OT, but we're running out of leads at my company to locate ~25 TI DSPs -
TMS320F280x (substitute 1,2,6,8,9 for X).  Anybody here have a couple
that they're willing to sell, or know of some other parties who may?
 

For x=1, Newark has right now 53 in stock:
http://www.newark.com/texas-instruments/tms320f2801pza-60/digital-signal-controller-dsc-ic/dp/03M1089

Gabriel


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gEDA-user: OT: Looking for DSP

[Ethan Swint]

OT, but we're running out of leads at my company to locate ~25 TI DSPs - 
TMS320F280x (substitute 1,2,6,8,9 for X).  Anybody here have a couple 
that they're willing to sell, or know of some other parties who may?


Thanks,
Ethan


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Re: gEDA-user: Toporouter: Line constraints

[Ethan Swint]

On 03/20/2010 04:06 PM, Anthony Blake wrote:

kai-martin knaak wrote:

What is the metric of small in this regard?
The number of connections to be auto routed? The size of the netlist 
includes connections ignored by the auto router The physical size of 
the board?


The number of constraint edges.
Constraint edges - those are the edges of the pads, pins, polygons, and 
existing tracks?



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Re: gEDA-user: Toporouter update?

[Ethan Swint]

On 03/17/2010 08:24 PM, kai-martin knaak wrote:

Anthony Blake wrote:

   

btw, if there are other little projects or features you would like to
add..

  design rules that depend on the net, ...
   

+1, for my work.

-Ethan


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Re: gEDA-user: rant: pcb print from command line

[Ethan Swint]

Yes - but what is the function!?! (A,B,C; 1,2,3 please.)

On 03/10/2010 03:07 PM, Alberto Maccioni wrote:

I called it a procedure, but it's the fact that there is a submit
patch function; it's so obvious to any developer that it's not written
anywhere.
And I didn't notice it until very recently.


2010/3/10 Jared Casper:
   

On Wed, Mar 10, 2010 at 5:14 AM, Alberto Maccioni
  wrote:
 

the code on the mailing list, but it took me several months to
discover the "submit patch" procedure.
   

What procedure did you find?

Jared


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Re: gEDA-user: Toporouter update?

[Ethan Swint]

On 02/23/2010 06:46 PM, Anthony Blake wrote:
Ok, then. Can you compile a list of tasks that need to be 
accomplished before the topo router is ready for general use? The 
smaler the individual tasks, the more likely they can be tackled by 
low time hackers like me...
For sure. It would require some careful consideration though.. I'll 
get back to you within a week.

Keep me in the loop, too.

-Ethan



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gEDA-user: Toporouter update?

[Ethan Swint]

Hi-

The last update on the toporouter looks like it was last June.  Any news 
since then, or is it waiting for me to jump in to the code? ;)  It looks 
fantastic.


FWIW - I think a better metric of router performance (instead of total 
track length as used on the web page 
http://www.wand.net.nz/~amb33/toporouter/detour.html), would be a 
statistical aggregation of the ratio of the individual nets track length 
compared to the minimal point-to-point length (think rat's nest).


Regards,
Ethan


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Re: gEDA-user: pcb: All v. Any pin connectivity

[Ethan Swint]

On 02/03/2010 03:33 AM, timecop wrote:

At the very least, it seems that there should be a way to specify that "any" 
pin with the same number satisfies the connection.
 

fairly ridiculous assumption especially with ICs, many of which
specifically say something like "all GND/VCC pads must be connected".
   

In which case, the pins have unique numbers, if not names.




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Re: gEDA-user: more kvetch re: pcb Arcs

[Ethan Swint]

  - "offset" button like 2d CAD packages have
 
offset - creates a new line, parallel to a selection, at a given 
distance on one (or both sides).  In the case of a line, the new line 
has the same length, and a perpendicular line will pass through the 
endpoints of both the original and new line.  For arcs, the start and 
stop angles are preserved.

  - "extend/trim" mode like 2d CAD packages have
 
extend/trim - using one line/arc as a boundary, change the length of 
another line/arc so that its endpoint lies on the first geometry.  In 
the case of non-existent intersection of the as-drawn objects, the 
algorithm may extend the reference geometry in order to find an 
intersection.


-Ethan


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Re: gEDA-user: Dsub15 HD

[Ethan Swint]

>> pins/pads/vias on the board and automagically set the mask clearance to
>> your desired value (e.g. 3 mils each side, +600 PCB units to the
>> pad/pin/via copper).  On my last board, I modified the numbers in a text
>> editor, but a pearl script would be much easier.  It would be a help if
>> anyone had a bit of parser already written... (Don't build when you can
>> steal!)
>>  
> Two months ago I did something similar this way:
>
> #! /bin/awk -f
> !/\tPin/ { print }
> /\tPin/ {delta=600;
>   if ($3+delta<$5) print; else
>   print "\t"$1" "$2" "$3" "$4" "$3+delta" "$6" "$7" "$8" "$9" "$10;
> }
>
> #! /bin/awk -f
> !/\tPad/ { print }
> /\tPad/ {delta=600;
>   if ($5+delta<$7) print; else
>   print "\t"$1" "$2" "$3" "$4" "$5" "$6" "$5+delta" "$8" "$9" "$10;
> }
>
> (two scripts: for pins and for pads to set minimum mask clearance
> to 3 mil (delta/2/(100 PCB units/mil))
>
> Such things are done in a minute, they don't need any special tool.
>
>
OK - many thanks.  I'll look up a primer on awk!

-Ethan


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Re: gEDA-user: Dsub15 HD

[Ethan Swint]

On 11/27/2009 01:43 AM, DJ Delorie wrote:
> I set my mask clearance to be 3 mil away from the copper, that's what
> most fabs want.
>
Do you (or some one else) have a script that will edit the 
pins/pads/vias on the board and automagically set the mask clearance to 
your desired value (e.g. 3 mils each side, +600 PCB units to the 
pad/pin/via copper).  On my last board, I modified the numbers in a text 
editor, but a pearl script would be much easier.  It would be a help if 
anyone had a bit of parser already written... (Don't build when you can 
steal!)

-Ethan


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Re: gEDA-user: PCB: window focus bug in GL branch?

[Ethan Swint]

On 11/10/2009 09:47 PM, Peter Clifton wrote:
> On Tue, 2009-11-10 at 13:15 -0500, Ethan Swint wrote:
>
>> I just did a git fetch&  build today from Peter's GL branch - many kudos
>> again! - but I'm getting a few "features" in my zooming activity.  The
>> first is reproducible by
>> 1) open PCB layout
>> 2) Swap application focus
>> 3) Use Alt+TAB to return focus to PCB.
>> 4) Use scroll wheel to zoom
>>
>> The menu bars around the drawing area gray out and don't return,
>> although you can zoom in and out all day long.  Gone also is the command
>> interface or any other action.  I have seen this behavior on the GTK
>> interface, as well.
>>  
> I think that is a bug in the GTK HID as well, as I've not touched any of
> that code. It would be a good one to get fixed though!
>
>
Any idea where that might be located?  I'm willing to work out a patch 
for it!
>> The second bug I'm seeing may be more GL-specific and involves the DRC
>> window.  After double-clicking in the DRC window, the cursor is
>> transferred to the main PCB window on top of the DRC error.  However,
>> all other tools seem to be inoperative.  Zooming changes the range on
>> the scroll bars, but the canvas is not updated.  The cursor is updated
>> according to the tool selection, but no button or key strokes register
>> on the canvas.
>>  
> Hmm, that works for me. I'd need more detailed steps to reproduce to
> test whether it occurs here as well or not.
>
> (Please ensure your check-out is up to date. I've not knowingly fixed
> any bugs which relate to this issue, but it is always useful to know we
> are testing vaguely the same code!)
>
Here's the output of pcb --verbose:

Action: DoWindows(DRC)  //open DRC window - everything still OK in the 
main PCB window.
Action: DRC()  //refresh DRC
ChangeGroupVisibility(Layer=0, On=1, ChangeStackOrder=1)  //double-click 
first DRC error
Action: LayersChanged()
ghid_layer_buttons_update cur_index=0 update_index=0
Action: LayersChanged()
ghid_layer_buttons_update cur_index=0 update_index=0
Action: LayersChanged()
ghid_layer_buttons_update cur_index=0 update_index=0
Action: PointCursor()//extra PointCursor() deleted
Action: PointCursor(True)  //mouse button - no effect
Action: PointCursor()
Action: PointCursor(True)
Action: PointCursor()
Action: Scroll(up)//scroll - no effect on canvas, only on 
scroll bars
Action: PointCursor()
Action: Scroll(up)
Action: PointCursor()
Action: Scroll(up)
Action: PointCursor()
Action: Scroll(down)
Action: Scroll(down)
Action: PointCursor()
Action: Zoom(0.8)   //zoom - no effect on canvas, only on scroll bars

Any further suggestions for debugging this?  It makes DRC completely 
unusable for me - once I see the errors, I can't correct them and have 
to restart PCB.

Thanks,
Ethan



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Re: gEDA-user: PCB: window focus bug in GL branch?

[Ethan Swint]

On 11/10/2009 05:26 PM, Kai-Martin Knaak wrote:
> On Tue, 10 Nov 2009 13:15:38 -0500, Ethan Swint wrote:
>
>
>> I just did a git fetch&  build today from Peter's GL branch - many kudos
>> again! - but I'm getting a few "features" in my zooming activity.  The
>> first is reproducible by
>> 1) open PCB layout
>> 2) Swap application focus
>> 3) Use Alt+TAB to return focus to PCB.
>> 4) Use scroll wheel to zoom
>>  
> Alt+Tab does not focus the mouse here. I have to move the mouse to the
> pcb window to make the mouse wheel zoom in pcb. (My config is: Gnome,
> metacity, mouse_focus=sloppy, pcb from Peters before-pours branch)
>
If I have another window open over PCB - e.g. schematic or text editor - 
typically the first thing I do when I Alt-TAB back to PCB is to zoom in 
to a related part of the board.  When that happens, the cursor doesn't 
move relative to the screen.  That's when the above behavior occurs.

-Ethan


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Re: gEDA-user: PCB+GL benchmark revisited

[Ethan Swint]

On 11/10/2009 12:08 PM, Peter Clifton wrote:
>
> To update without re-fetching the whole thing, this might / might not
> work:
>
> git fetch
> git reset --hard origin/before_pours
>
>
This works fine for me.

-Ethan


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gEDA-user: PCB: window focus bug in GL branch?

[Ethan Swint]

I just did a git fetch & build today from Peter's GL branch - many kudos 
again! - but I'm getting a few "features" in my zooming activity.  The 
first is reproducible by
1) open PCB layout
2) Swap application focus
3) Use Alt+TAB to return focus to PCB.
4) Use scroll wheel to zoom

The menu bars around the drawing area gray out and don't return, 
although you can zoom in and out all day long.  Gone also is the command 
interface or any other action.  I have seen this behavior on the GTK 
interface, as well.

The second bug I'm seeing may be more GL-specific and involves the DRC 
window.  After double-clicking in the DRC window, the cursor is 
transferred to the main PCB window on top of the DRC error.  However, 
all other tools seem to be inoperative.  Zooming changes the range on 
the scroll bars, but the canvas is not updated.  The cursor is updated 
according to the tool selection, but no button or key strokes register 
on the canvas.

Does any one else see this behavior or have a suggestion as to which 
point in the code could be responsible?

Thanks,
Ethan


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Re: gEDA-user: moving treces

[Ethan Swint]

Vincent Onelli wrote:

The task was a time consuming one, the most difficult was moving the trace 
because the trace brakes at every bend.
  
Select a train of traces, then save while they are selected.  Use a text 
editor to increase the line width of the lines containing the "selected" 
attribute.
Is there away to retain connection while moving? 
  

Turn on "Rubber-band" mode under the Settings menu.

Vinny



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<>

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Re: gEDA-user: plated mounting holes

[Ethan Swint]

On 10/23/2009 05:58 AM, gene glick wrote:
> How can I make a mounting hole that does:
> 1. top/bottom side plated round pad, e.g. .250"
> 2. connected from top to bottom with a plated hole
> 3. inner layer clearance is just the normal clearance around the hole,
> say .010"
>
>
Presently, PCB can't do different pads on different layers.  I can think 
of two ways to do this:
1) Make a via with no pad, then make a solid thermal to a polygon which 
approximates a circle on top and both.  Finally, an arc trace can cover 
over the jagged edges.
2) Make an element with two rounded pads, same location, but one with 
the flag "onsolder".  Then put a pin through that has zero (or minimal) pad.

-Ethan
> I tried a large via, but the inner layer clearance is the clearance of
> the surface pad leaving a really big copper-free section on the inner
> layers.
>
> I suppose creating to elements, one for the top-side and another for the
> bottom, connected with a via of the proper hole size would work.  Seems
> there's another way, though?
>
>
> gene
>
>
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Re: gEDA-user: PCB+GL+3D (Z-coord) Eye-candy

[Ethan Swint]

> Just proof of concept stuff...
>
> http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/
>
> There isn't anything clever here.. just the same PCB+GL translucent
> rendering I had before, but with a 3D virtual trackball to rotate the
> viewport.
>
>
Very cool!  How do you set the origin for the viewport?  One thing you 
might want to do is to provide a number box for azimuth, elevation, and 
z-angle, and z-distance (optional, for zoom) from the origin to the 
camera.  That's the easiest way to reset your view when things get 
squirrelly from the oval graphic control or revisit an angle that you 
liked previously.

-Ethan


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Re: gEDA-user: Barred solder mask in PCB

[Ethan Swint]

On 10/13/2009 04:45 PM, John Griessen wrote:
> I see the "wrong angles" change at different zoom levels.
> I compiled the gtk GUI
>
> John
>
>
Yeah - I guess that's the limitation of PCB's resolution (1e-5 inch) 
coming through?


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Re: gEDA-user: Barred solder mask in PCB

[Ethan Swint]

On 10/13/2009 02:34 PM, Ben Jackson wrote:
> On Tue, Oct 13, 2009 at 01:10:40PM -0400, DJ Delorie wrote:
>
>> Another option is to rebuild pcb without Xrender support, and see if
>> it's the rendering that's the problem.  Or export to Postscript.  IIRC
>> the gerbers use the dicer, so if the dicer is bad, the gerbers should
>> be bad also.
>>  
> They do, but they operate on the full board.  The clue about being
> zoomed in suggests that it has to do with first cropping the poly to the
> visible area and then dicing it.  That would also explain why the
> artifacts move around (as the visible objects, many of which seem to
> be placed on an angle, intersect at different offsets).
>
>
The barring also happens at full-view (zoomed out), but Gerbers are just 
fine.  The Gerber soldermask layer is a negative image - maybe that 
makes the difference to the dicer?  I'll work getting a "sample board" 
for public consumption.

Thanks,
Ethan


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Re: gEDA-user: Barred solder mask in PCB

[Ethan Swint]

On 10/13/2009 12:09 PM, Duncan Drennan wrote:
>> Fedora 11; PCB 20081128: On this board, the solder mask displays in bars on
>> my board, which has some components placed at arbitrary angles.
>>  
> What do the gerber outputs look like? Are they also corrupt?
>
>
Gerbers are correct, so whatever code is responsible for the barring 
doesn't appear to be common to screen and gerber outputs.



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Re: gEDA-user: PCB GL status update?

[Ethan Swint]

On 10/02/2009 03:07 PM, Peter Clifton wrote:
> On Fri, 2009-10-02 at 12:36 -0400, Ethan Swint wrote:
>
>> The last update I saw on the list for using GL in PCB was back in
>> February, although the recent screen-shot looks very cool.  Are the
>> build instructions still the same?
>>
>> git clone git://repo.or.cz/geda-pcb/pcjc2.git
>> cd pcjc2
>> git checkout -b before_pours origin/before_pours
>> autogen.sh
>> configure --disable-doc
>> make install
>>  
> "probably"..
>
> I rebased it against PCB git HEAD occasionally, but otherwise there has
> been little progress.
>
> Best wishes,
>
> Peter C.
>
>
>
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>
Hmm... the message just after the one where I pulled those instructions 
lists

./configure --disable-doc --enable-threads=posix --enable-dbus --enable-gl

-Ethan




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gEDA-user: PCB GL status update?

[Ethan Swint]

The last update I saw on the list for using GL in PCB was back in 
February, although the recent screen-shot looks very cool.  Are the 
build instructions still the same?

git clone git://repo.or.cz/geda-pcb/pcjc2.git
cd pcjc2
git checkout -b before_pours origin/before_pours
autogen.sh
configure --disable-doc
make install




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Re: gEDA-user: PANGO FONTS MERGED: Call for testing

[Ethan Swint]

On 08/18/2009 04:18 PM, Peter TB Brett wrote:
>>> I run Fedora 11, and it works for me.  Please provide the output of:
>>>
>>> rpm -q glib2{,-devel}
>>>
>>> Mine is:
>>>
>>> glib2-2.20.4-1.fc11.i586
>>> glib2-devel-2.20.4-1.fc11.i586
>>>
>> # rpm -q glib2{,-devel}
>> glib2-2.20.4-1.fc11.x86_64
>> glib2-2.20.4-1.fc11.i586
>> package glib2-devel is not installed
>>
>> So it is looking for glib2... but it's not finding it.  Is there a way
>> to re-build the installed package index?
>>  
> Your problem is that glib2-devel is not installed.
Ahh.. that got it.  Many thanks.  I have compiled gaf before, I'm not 
sure what happened to the devel package.

-Ethan


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Re: gEDA-user: PANGO FONTS MERGED: Call for testing

[Ethan Swint]

On 08/18/2009 03:53 PM, Peter TB Brett wrote:
> On Tuesday 18 August 2009 20:47:12 Ethan Swint wrote:
>
>> On 08/18/2009 08:22 AM, Peter Brett wrote:
>>  
>>> Duncan Drennan
>>>
>>> writes:
>>>
>>>> On cygwin:
>>>>
>>>> ./configure --prefix=/home//geda
>>>>
>>>> [snip]
>>>> configure: error: GLib 2.12.0 or later is required.
>>>>
>>>> The latest official glib2 release on cygwin is 2.10.3 :(
>>>>  
>>> GLib 2.12 is a dependency of GTK+ 2.10, which we currently require.  I
>>>
>> Also, on an up-to-date Fedora 11 distribution, configure complains about
>> Glib 2.12.0.  The latest glibc in the Fedora repositories is 2.10, but
>> there is a Glib2 v. 2.20 installed on my machine.   How do I determine
>> exactly which package configure is looking for?
>>  
> I run Fedora 11, and it works for me.  Please provide the output of:
>
>rpm -q glib2{,-devel}
>
> Mine is:
>
>glib2-2.20.4-1.fc11.i586
>glib2-devel-2.20.4-1.fc11.i586
>
>
# rpm -q glib2{,-devel}
glib2-2.20.4-1.fc11.x86_64
glib2-2.20.4-1.fc11.i586
package glib2-devel is not installed

So it is looking for glib2... but it's not finding it.  Is there a way 
to re-build the installed package index?

-Ethan


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Re: gEDA-user: PANGO FONTS MERGED: Call for testing

[Ethan Swint]

On 08/18/2009 08:22 AM, Peter Brett wrote:
> Duncan Drennan
> writes:
>
>
>> On cygwin:
>>
>> ./configure --prefix=/home//geda
>>
>> [snip]
>> configure: error: GLib 2.12.0 or later is required.
>>
>> The latest official glib2 release on cygwin is 2.10.3 :(
>>  
> Yes, this problem was also noted by Bert Timmerman.
>
> GLib 2.12 is a dependency of GTK+ 2.10, which we currently require.  I
> have difficulty believing that the Cygwin GTK+ package hasn't been
> updated more recently than May 2006 (actually, that's frankly
> ridiculous).  I recommend that you whinge at the Cygwin package
> maintainers for the GTK+/GLib packages.
>
>
Also, on an up-to-date Fedora 11 distribution, configure complains about 
Glib 2.12.0.  The latest glibc in the Fedora repositories is 2.10, but 
there is a Glib2 v. 2.20 installed on my machine.   How do I determine 
exactly which package configure is looking for?

-Ethan


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Re: gEDA-user: MoveObject()

[Ethan Swint]

Aha... I'll have to do that!

-Ethan

On 07/27/2009 02:43 PM, DJ Delorie wrote:
> As a followup, run "pcb --verbose ..." to see all the actions
> happening.
>
> (before you ask... PointCursor chanes the cursor shape as it passes
> over different things)
>
>
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Re: gEDA-user: MoveObject()

[Ethan Swint]

   On 07/27/2009 02:26 PM, John Griessen wrote:

DJ Delorie wrote:
  

[1]http://geda.seul.org/wiki/geda:pcb_tips#how_do_i_move_objects_by_an_arbitrar
y_distance


One of these days, I'm going to remember that :-P


What would be the relative or absolute reference point MoveObject() uses on a p
rimitive like a line?

John



   Are all actions in PCB mapped to a command-line script?  For those
   actions that do have a command line, it would be nice if the script
   for every mouse-driven action was printed to a dialog box, e.g. the
   log window.  That's how I got a lot more proficient at AutoCAD.  (Not
   that I use it any more, but I did like that interface.)
   -Ethan

References

   1. 
http://geda.seul.org/wiki/geda:pcb_tips#how_do_i_move_objects_by_an_arbitrary_distance


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gEDA-user: annoying PCB hangups

[Ethan Swint]

I've been working with PCB compiled on 26 Feb 2009 in Fedora 11 and have 
encountered one annoying hangup and one crash in the gui fairly 
frequently.  Neither one have been consistent enough for me to nail down 
completely, but I wondered if anyone else has encountered something 
similar to the following events:

The hangup comes when I use Alt-Tab to switch from another window (e.g. 
schematic) to PCB and immediately scroll.  The PCB canvas becomes 
unresponsive, the buttons and menu become grayed out, but the 
application doesn't hammer any system resources (CPU, memory, disk).  
Clicking the "close window" icon has immediate results and I think that 
I have been prompted to save unchanged work.

The crash comes from clicking in the netlist window after changing the 
netlist, e.g. directly editing the .pcb file or importing a netlist.  A 
workaround is to close & reopen the netlist window with every change.  
This can result in the loss of work, although the auto-backup does 
prevent too much from being lost.

Regards,
Ethan


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Re: gEDA-user: comments in gaf source

[Ethan Swint]

> For some time there are Doxygen developer docs based on the git repo for
> pcb to be found here:
>
> http://www.xs4all.nl/~ljh4timm/pcb-doxygenation/dox_pcb/index.html
>
> I'm currently looking into how much disk space my ISP has left me and
> how much disk space it would take for the Doxygen developer docs for
> gaf.
>
Thank you very much!

-Ethan


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Re: gEDA-user: Gschem/Custom Symbol/Path

[Ethan Swint]

On 07/26/2009 08:53 PM, Mike Hansen wrote:
> I just transferred my Linux image to a new box and installed Gschem.
> I have custom symbols for gschem that are in their own directories.
> Now when I load up the schematics I get the dreaded "component not
> found" on the schematic in place of the component diagram for custom
> components.  I know I have to modify one of the rc files(I think) but
> I cannot for the life of my figure out which file it is.  I know the
> directory for the custom symbol has to be defined in one of the rc
> files.
>
> Thanks!
>
Put this in a file called "gafrc" (no extension) in your project 
directory.  Alternatively, put it in your /home/*username*/.gEDA directory:

(component-library "/home/ethan/electronics/symbols")
(component-library "/home/ethan/electronics/footprints/")
(component-library-search "/home/ethan/electronics/footprints")
(source-library ".")

In your /home/username/.pcb directory, edit "preferences" and put your 
footprint library path there.  I have

library-newlib = ~/gaf/footprints

Regards,
Ethan


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