gEDA-user: Shitty chip vendor companies
Larry Doolittle wrote: > I have done that, too, but only rarely. It's a royal PITA. > Do those guys *cough*Marvell*cough* want us to use their parts, > or not? The real problem occurs when a device with the functionality you need is made *only* by the "shithead" companies like Broadcom, Marvell or Mindspeed, and not by any of the more open companies. xDSL transceivers are a prime example, although not the only by any means. Ahh, if only Russia, China, North Korea and Iran were willing to grow some balls, invade USA or more specifically those parts of USA which harbor the HQ of the abovementioned companies, send troops (special forces) to storm their HQ, seize all their "intellectual property" at gunpoint and publish it simultaneously on ftp.gov.ru, ftp.gov.cn, ftp.gov.nk, etc free to the world... If all 4 named countries were to do it simultaneously, acting in unison as a joint force, methinks it would be pretty effective... MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any place that fabs custom project boxes?
On 02/17/2011 08:33 PM, yamazakir2 wrote: > I have never done this before, but I want to fab some customized boxes > for some pcbs I'll be making in the future. I want custom dimensions > and custom cutouts and custom mounting posts for the pcb. I have used the services of Vinatech Engineering Inc. to design and manufacture the custom sheet metal enclosure for my OSDCU board: http://www.vinatechinc.com/ It was expensive, but the result was truly of professional quality, suitable for a shippable commercial product. You can see pictures here: http://ifctfvax.Harhan.ORG/OpenWAN/OSDCU/ The pictures don't show any internal mounting elements, but the drawings they gave me are on the FTP site; you can look at them to judge the complexity. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FUNDING
al davis wrote: > Just because Eudora on Windows can't cope with it? Who said Eudora? Who said Windows? I use neither. I read all my mail raw exactly as it comes across the wire, without using *any* MUA that does any decoding behind my back. I have a little program I wrote myself that decodes base64, but it's a major PITA. Hence if mail arrives in base64 and neither its source nor its subject line give a strong signal that it's important, it usually gets deleted by the firmware in my fingers without ever reaching my eyeballs. Any responses to this message that are encoded in base64 are likely to receive such fate. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FUNDING
al davis wrote: > Base64 is a published standard that should be > universally supported. ... by way of standard open source mailing list managers detecting and automatically rejecting posts encoded in base64. Sorry, couldn't resist. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Functional blocks and PCB format changes
Stephan Boettcher wrote: > We had that: M4 footprints. I never liked those, I could not figure out > how to use them. But I love them! MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: wishful UI
John Doty wrote: > but "pcb" is apparently almost completely = > dependent on gnetlist. No, it isn't. PCB defines its netlist input format; the schematic capture folks like gEDA then adapt to it, in gEDA's case by way of a gnetlist back-end. My OSDCU board through which the characters of this message pass on their way from my keyboard to your screen (well, from my mail server to the list) has been laid out in PCB, yet the netlist has been loaded from uEDA rather than gEDA. -MS, who otherwise generally sides with John Doty in this perennial argument. Ahh, if I only had an aerospace-like budget for my retrocomputing projects... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for a flash IC programming service
Hello fellow free EDA users, I wonder, would there happen to be anyone on this list who has a working flash chip programmer setup and who would be willing to help out a fellow Open Source Hardware maker, for some monetary compensation for your time and effort? I need to have some 29F040 type flash chips programmed, using code images which I post on my public FTP site. (The code to be programmed into the chips is 100% FOSS, the source can be checked out by anyone at any moment from my anonymous CVS repo, and the OSDCU board these chips go into is 100% open source too: the schematic and PCB sources in the ueda and pcb respective formats are posted on the FTP site, as are the Gerber, PostScript, PDF and BOM files generated from them.) I don't have my own device programmer that can be used without Weendoze, I no longer have access to one at my day job, and I have tried to get the same contract manufacturer who has been soldering my boards for me to do the flash chip programming as well, but they don't seem interested enough in my business to bother learning how to use their programmer. (They have tried, but gave up at the first sight of an error message from their software.) So I am looking to hire someone else with a working device programmer setup to program these 29F040s for me. These are 5V 512Kx8 flash chips, PLCC32 packages, very classic. I can ship you the Am29F040 parts I have along with a check for the programming service, or if you have blank parts of your own which you don't mind selling, that would work too. I have two images that need to be programmed (upper and lower halves of a 16-bit data bus), and I would like to program 5 chips with each image, for a total of 10 chips. I would greatly appreciate any offers. I'm located in California and would prefer to work with someone in USA to avoid international logistics. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for my first fab shop.
> Are there any fab shops that would be gentle with a very new, very > inexperienced PCB designer? OH and reasonable for a prototype. Last time > I laid up a board I used a drafting table and mylar. I may need a bit of > handholding as I go along. I had my OSDCU board fabbed at Sierra Circuits (protoexpress.com). It certainly ought to meet the "inexperienced first-timer" requirement, as it was my life's first hardware design, and I am a software/firmware guy who got into designing hardware because I wanted to play with toys that didn't already exist because apparently they are of no use/interest to anyone in the world but me. I really liked Sierra's service and quality. To get an idea of just what I mean by "my life's first HW design", see this page: http://ifctfvax.Harhan.ORG/OpenWAN/OSDCU/ Includes schematics, PCB prints and a high-resolution photo of the finished board. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: more kvetch re: pcb Arcs
Mark Rages wrote: > If I can't get this working in the next few days, I'll probably be > buying a license for Altium and a Windows computer. The thought > depresses me. If you are already prepared to spend $$$ on Altium and Weendoze licenses, why not instead offer that same money to someone who can fix the problem in PCB for you? No, I am *not* the person you would want to hire for this as I know next to nothing about PCB internals, but I'm sure there ought to be plenty of other good candidates on this list. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: DC power feed on xDSL circuits
Hello again, I have figured out the answers to some of my questions regarding DC on xDSL by talking to a support engineer at Midcom, one of the vendors for the custom transformer parts used for xDSL. (Trying to get support from the SDSL transceiver chip vendor would have been hopeless as it's Mindspeed, but I hadn't previously thought of trying the transformer vendor instead.) Here is what I've got: * The most pimped-out design for an ISDN/IDSL/SDSL/SHDSL subscriber terminal (the kind that would be made by someone who likes to cover every possible corner case and has the parts and PCB real estate to spare) uses a fancy DC termination scheme. DC through the line transformer's winding is blocked with a cap, but another device is connected in parallel across the line which provides the fancy DC termination. Lucent's LH1465 ISDN DC termination IC is the example I am familiar with. The DC termination is fancy in that the device presents a high DC resistance until the voltage reaches a certain threshold; then it "switches on" and the DC resistance becomes quite low; it then stays "on" for as long as the current flowing through it remains above another threshold. There is yet another threshold for the maximum allowed current; when that one is reached, the device increases its DC resistance to limit that current. Finally, the presence or absence of DC current is indicated to the ISDN device's microprocessor via an optocoupler. Fancy indeed. The stuff above is what I already knew prior to my original inquiry. * The subject of my inquiry was devices made for SDSL and IDSL (rather than ISDN or SHDSL) which do away with the expensive fanciness described above on the presumption/realisation that it would be a waste of effort and parts because the SDSL/IDSL lines in North America don't have intentional DC on them. In the absence of intentional DC on the line one does away with the LH1465 or equivalent, but there remains the question of what to do with the DC blocking capacitor: leave it in or take it out? The choice made in the design of dominant SDSL CPE devices from Copper Mountain, Netopia and Inefficient Networks has been to leave the cap in, and that is what I have reproduced on my OSDCU. The Midcom support engineer didn't have a clear answer to this question either except to confirm that their HDSL/SDSL transformers have been designed with the provision for DC flowing through them and that they are guaranteed to perform within specs with up to 160 mA flowing through the primary winding. (160 mA is a lot, all the specs I've seen for over-the-line powering of remote terminals and repeaters say the limit is 60 mA.) I have decided to leave the DC blocking cap on the OSDCU board in place in any future revisions because: a) In the CPE application I simply "do like the others" and that's what I'll tell to anyone who asks :-) b) In the CO application with DC power feeding we do need an open rather a short in there as explained below. * Now moving on to the question of interest to me: how would one provide DC power on the line if such a thing was needed. I've asked the Midcom support engineer the same question I had asked on this list: is it better to apply the DC power to the centre split or outside the transformer? The Midcom guy agreed with my reasoning that either way ought to work, and the discussion then turned to the question of why they have designed their transformers to work with up to 160 mA of DC when the requirement could have been avoided if one simply opted to apply the DC feed in parallel with the DC-blocked winding. The Midcom guy explained to me that the core needs to be gapped in order to make the transformer DC-tolerant, but since they also need to gap the core in order to provide the required primary inductance (the SDSL transceiver chip requires the custom transformer to dual-function as a high-pass filter with a precisely specified primary inductance), it appears that making the transformers DC-tolerant didn't cost them much extra. While the only authoritative answer was that Midcom had designed their transformers with the specs that they have (including the 160 mA DC current) because that's what the SDSL chip vendor had asked them to make, by analysing the situation rationally we came to the conclusion that applying the DC source or load to the centre split and letting the feeding current flow through the winding results in a smaller part count. If one were to apply DC in parallel with the DC-blocked winding, the DC power supply would at the minimum need a big inductor at its output in order to provide a high impedance at the data signal frequencies, whereas if one applies DC to the centre split, the transformer itself takes care of that. * The conclusion I have reached for any SDSL designs that we may create in the open source communit
gEDA-user: OT: DC power feed on xDSL circuits
Hello fellow gEDA users, I have a telecom electronics design question - are there any folks here who have done telecom stuff? My question deals with DC power feeding on data-carrying copper loops: ISDN, [S]HDSL, etc. The typical circuit found in equipment interfacing to such lines (either at the CO or at the remote terminal) looks like this (ASCII art): *---3 | 3+ 3 | 3| 3 | 3--+ | 3 || +- To transceiver IC 3 |= (1 uF or so) To copper loop 3 || +- 3 | 3--+ | 3 | 3| *---3 | 3+ I have observed the above circuit in SDSL chip datasheets as well as inside most SDSL gear found on eBay, and I have faithfully reproduced it on my OSDCU board - it works just fine so far. But there are some things I just simply fail to understand about this circuit, and I wonder if anyone here might have some insight. 1. What is the benefit from having the DC blocking capacitor across the centre split in the transformer's primary winding? What harm would there be if someone took that capacitor off the BOM and simply shorted those pins on the transformer to make the primary winding effectively non-split? While SDSL lines in North America are generally unpowered (I've never seen one with DC power on it), when someone does put DC power feed on a line of this kind (like they do with ISDN for example), they generally want the user-attached CPE to conduct some DC current (they call it sealing or wetting current, supposedly it somehow helps with contact corrosion), so my simple peasant mind thinks that a DC short ought to be closer to what they want than a DC open, yet they put that DC blocking cap in there to make the device present itself as an open in terms of DC termination. Why? 2. Suppose that I do want my CO-side terminal unit to provide DC power feed on the line - say, to power a mid-span repeater. Where would I need to connect my DC power source? Would it need to be connected across the centre split of the line transformer's primary winding in parallel with the cap, or would it simply go across the copper pair instead? Some of those SDSL transformers (which are all custom parts) were apparently designed for fairly high DC current, so it seems like connecting the DC power source (or load) across the centre split is the way it's done. But why? Why can't one simply connect the DC power source across the copper pair in parallel with the SDSL box? If power feeding can be achieved by connecting the DC power source across the copper pair outside the main xDSL equipment, it could be a modularity advantage (design the main xDSL box without worrying about power feed and let those users who need it do it externally), whereas otherwise one needs to provide a special tap to allow the user to get to that centre split in the transformer winding. TIA a lot for any insight. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: geda build error on Mac OS
Craig Niederberger wrote: > So if you could get disabling language support in > configuration to work, that would probably help others. I second that request! Whenever I have to build any GNU software that uses those darned configure scripts, I always specify --disable-nls for ideological reasons: NLS/i18n is one of the most evil and heinous things invented in all of computing. English is the international language of Computer Science, and every computer user should be required to think in English only whenever one is operating Computing Machinery of any kind. And I'm saying this as a non-American (from the opposite side of the Berlin wall in fact) whose native language isn't English! And yes, I maintained exactly the same attitude when I lived in my home country: I used to go around saying that my native language and computers should not mix. Of course that goes hand-in-hand with my general attitude that computers should not be for mere mortals in the first place. I so wish that it was illegal for anyone to even *touch* a computer or any device containing a processor of any kind unless that person is capable of booting it up by entering the very first machine instructions from a blinkenlights-and-toggleswitches console... If computers were restricted to the select few, there would be absolutely no problem with requiring their users to learn English as part of learning Computer Science and to think in English when operating those marvelous magical devices that are beyond the reach of mere mortals. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: More strange ideas: Start PCB layout from symbols view
DJ Delorie wrote: > I've been writing in C++ on Unix for, oh, twenty years now. How > ancient is your Unix? Well, different components have different ages (as in time since the last modification), but the system's C compiler (which is the part that matters in this case) is PCC for VAX, principally unchanged since 1979 or so. 30 y instead of 20. :-) MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: More strange ideas: Start PCB layout from symbols view
DJ Delorie wrote: > Try this... it might need additions to support full schematics, and > it's not as pretty as libgeda would produce... No longer of use to me as I've already made the one-way transition to uschem, but perhaps someone else will find it useful... > http://www.gedasymbols.org/user/dj_delorie/tools/sym2eps.cc Hmm, the .sym format is actually one thing that I have kept unchanged from gschem, and my uschem-print utility contains the code to render gschem graphics primitives into PostScript. But it's written in K&R C instead of C-crap-crap so it can run under Ancient UNIX. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: More strange ideas: Start PCB layout from symbols view
John Doty wrote: > But are you talking about genuine, essential capabilities, or just > sugar? An example from the coding world is the ability to single step > through code you're debugging. That's pure sugar: you don't need it, > it is a monumental waste of time, and the coders who are addicted to > it are not productive. Yes, total agreement here! > Yet they swear it's essential... Oh yeah, all the ridicule I get from cow-orkers on sw projects as "the guy who doesn't believe in debuggers". > On the other hand, the ability to come back to a project after a > couple of years, make a small change, and have "make" regenerate all > of the data products: schematics, netlists, documention, software > drivers, etc. is almost priceless. Total agreement again! > Hurray for gEDA! Sorry, but I have to disagree with you here: gschem's assinine requirement of having an X11 display to generate PostScript output from the command line totally kills it. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: "Analog" books
Bill Gatliff wrote: > Quick OT question about the format of this email, which I see used a lot > on this list. Are you using an automated email filter to generate these > references, or do you do it by hand? If the former, what is the name of > the software? There unfortunately exist some netiquette-deficient people who send HTML E-mail and post such to mailing lists. Apparently this list tries to be nice and autoconverts such HTML mail to plain text, probably by running it through good ol' Lynx, and what you are seeing is the output of that conversion. It is also very common for electron and bandwidth wasters to send their messages in the super-bloated MIME multipart/alternative format, which is plain text followed by HTML. This list's MIME filter is misdesigned or misconfigured with regard to handling such messages: the right thing to do would be to simply delete the HTML part with extreme prejudice and pass only plain text through, but for some strange reason this list converts the HTML part to plain text but still leaves it there in the multipart/alternative structure, so you get two plain text copies: one generated by the original sender, the other generated from HTML by the list's MIME filter. I see all these mail abuses while others are blissfully ignorant of them because I refuse to use mail clients that would do things behind my back and instead I read all my E-mail raw, exactly as it travels across the wires. That has some unfortunate side effects: for example, anything that comes through this list from Kai-Martin Knaak and a few other less regular posters usually gets deleted without reading on my end because those messages arrive encoded in base64, i.e., gibberish to a raw mail reader, and it's far too much pain to save them and decode them externally. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to deal with single/dual parts?
Bill Gatliff wrote: > Now I'm beginning to see the problems with slotting and symbols the way > we're doing them now: they unnecessarily tie the concept of a symbol to > the concept of a component, because the pin numbers that we currently > record in our symbols are also the pin numbers that the component maps > to the pins of the component's package. We have munged together the > concepts of symbol and component in our "symbol" files, but can't seem > to admit to that. You have hit the nail right on the head! It was this very issue (the fundamental difference between symbols and components) that played a major factor in my decision to invent a new schematic file format for uschem instead of merely writing a tool that prints gschem format schematics into PostScript without requiring an X11 display or a "modern" system to compile and run gEDA/gaf with all of its dependencies. > That's the breakage, methinks. Yup, the very first thing I have fixed in my fork. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to deal with single/dual parts?
John Doty wrote: > A powerful component of an electronic design *automation* process. > Not the usual fritterware tool that forces you to tell it what to do, > repeatedly, by manual operation. Do graphics with GUI, do flow with > scripts. High productivity rather than cute a marketable. John, why don't you just fork? I've already made my own divergent-and- forever-irreconciliable fork of gaf (uEDA/uschem) due to dissatisfaction with the "fritterware" direction that gEDA/gaf is heading into, so why can't you do the same? This way you and I can have our totally scriptable UNIX-style high-IQ-requiring toolbox while Peter C and crew can have their "fritterware", and everyone will be happy with his choice. That's what I like the most about Free / Open Source Software: the ability to fork! I have forked almost every program I use on a daily basis because what I want is typically the opposite of what the rest of the world wants. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA-dev: Arc intersection connectivity bug
Ineiev wrote: > The sample o.pcb is an extraction of teardropped OSDCU board. What exactly are these teardrops and what is their benefit? Just curious. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA and pcb status and minigration from Eagle
Torsten Wagner wrote: > is uschem public available ? cvs -d :pserver:anon...@ifctfvax.harhan.org:/fs1/IFCTF-cvs co ueda ifctf-part-lib OSDCU will give you uEDA/uschem, my part library for it and a sample project (the only board project done with uEDA so far :-) which dual-serves as documentation. > I would like to test it out as well. Please beware that because I wrote uEDA for my own use[*], it is designed to compile and run on a 30 year old UNIX system. If your OS/compiler is younger than 30 or so, you are likely to have compilation problems as others have already discovered. MS [*] I release absolutely all my creations into public domain as a matter of religious philosophy, but whether or not anyone else likes them, cares about them or finds them useful is often of little concern to me. :-) I'm an isolationist. You've been warned. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA and pcb status and minigration from Eagle
Torsten Wagner wrote: > How mature and stable are the suite yet ? > Can it be really considered for serious work ? I have designed and built an SDSL physical layer interface board using this suite, a board which one of the gEDA developers (Peter C) has remarked upon as being quite complex. That board is an open source hardware project which you can see here: http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/ That board project started with me drawing my initial schematics in gschem, then about halfway through the project I had converted to uschem (my own fork of gschem that has no GUI, command line only to generate PostScript schematics, netlists and BOM information) and finally the layout part was done in PCB by Ineiev who is on this list. I have also heard that many other users of these tools have used them to create serious work that is quite a bit more impressive than mine. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Alternative subparts
k...@aspodata.se (Karl Hammar) wrote: > Is there a way to organize alternative subparts in a project, e.g. > a cpu-card for one user will have one kind a bus-connector and for > another user another bus-connector, but still maintanable as one > project? I don't see a sensible way to do it with GUI tools like gEDA, but with batch mode Makefile-driven tools like uEDA you could set your Makefiles up to pass your source code through a preprocessor like cpp or m4 (allows conditional compilation) before feeding it into uschem-print and uschem-netlist for example. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: My uEDA-designed open source hardware board works!
David SMITH wrote: > However, I think you'd have a problem with non-GUI PCB layout. Whilst > you could automate all of the routing and some of the placement, I'd > really struggle without a GUI for placing the parts where their location > matters (e.g. connectors, front panel stuff, etc.). I suspect that > doing this textually would be a rather tedious and long-winded process. Actually for me it's exactly the other way around: when it comes to putting down those elements whose locations are fixed by external constraints, vi-ing the .pcb file is my preferred method for doing that: I'm really good at doing the centimil math involved in that and this way I have the confidence that the element or the mounting hole (Via object) is exactly where I need it to be. For the OSDCU board this has turned out to be a non-issue because I went with the strategy of making the board first and then building an enclosure for it later once it's 100% working, so I told Ineiev that it was OK to move the "fixed" components around a little if necessary on this first pre-enclosure PCB revision, but previously I had a different plan. My previous plan had been to fit my board into the enclosure from a gutted Inefficient Networks router, and I had measured the old board out with a caliper and entered all fixed locations into OSDCU.pcb with vi. But then I changed my mind because I wanted to use right angle LEDs instead of the upward-shining ones used by FP/EN, and I didn't want the IEC 320 AC mains entry right on my board as I wanted more flexibility (allow OSDCU+router or multi-OSDCU combinations sharing a common enclosure and power supply). So I trimmed my PCB down to a rough size equivalent of the functional section (sans AC mains entry) of FP/EN's PCB, made it simple rectangular, made the dimensions metric (I still consider myself a Soviet citizen and follow Soviet standards) and let Ineiev have a go at it. :-) And now we have a working board, yay! k...@aspodata.se (Karl Hammar) wrote: > The ueda don't compile out of the box here, there are a lot of forward > references to static functions, exit(3) and strlen(3) no declared, and > conflicting declaration of malloc. uEDA is intended to run on 1970s-80s versions of UNIX like I use, but it builds OK on my Linux boxes too if one simply ignores the voluminous gcc warnings. > Attached diff fixes thoose for me. With this diff it would be unusable to me because doesn't exist on UNIX systems like V7 and 4.3BSD. MS P.S. Yes, I'm heavily into retrocomputing. The OSDCU board I've just built is actually a retrocomputing device too, as its primary purpose is to hook SDSL circuits up to 1980s-style routers. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: My uEDA-designed open source hardware board works!
asom...@gmail.com wrote: > "Horror" is the correct description of my first thought. EDA is such > an inherently graphical task, a gui seems natural. For a "professional hardware engineer" type: yes. For someone like me: no. Although I've had an active interest in how electronic circuits and digital hardware in particular work for about as long as I've been programming (both since the age of 7 or so), I've been on the software track mostly and have never done hw work professionally, certainly not hw design. When I had discovered UNIX, I totally fell in love with it and never looked back (to DOS and various GUI shells that ran on top of it), so now I have a UNIX mind. My UNIX mind simply cannot fathom doing *any* kind of intellectual creation work by any way other than writing the source code in vi, writing a Makefile and then iterating vi source and make until the product works the way I want. I don't use IDEs for software development, only vi & make, I don't use word processors like OpenOffice or M$ crap, I write all my TPS reports in vi & troff (non-WYSIWYG text formatter) instead, and now I'm doing the same thing with EDA. But unfortunately "professional hardware engineer" types don't think like this. They aren't programmers, so they haven't been raised in the programming geek culture that generally embraces UNIX and its way of doings things (pipefitting and Makefiles), hence they are blind to its power and instead like those GUIs that we UNIX people abhor. To me Open Source Hardware is an outgrowth of the Free / Open Source Software movement, *not* an outgrowth of the commercial for-profit hardware engineering world where the Weendoze & GUI types dominate, so to me it makes perfect natural sense that OSH development can be done by someone like me who is absolutely not a professional hardware engineer, but a passionate zealot of FOSS and the UNIX Way of Doing Things (tm). But I guess the gEDA community is quite different, and I've noticed that quite a few people here (perhaps even the majority) are *not* doing Open Source Hardware, instead they are using FOSS EDA to create closed proprietary hw designs. Argh! I'll spare my obligatory Marxist-Leninist comment on what I think should be done to such people. > But you apparently > did without, so maybe I can too? Is uEDA public yet? I'd like to > check it out. It has always been public in the sense of being developed in a public CVS repository which anyone can check out at any time (ditto for my board), but the documentation still hasn't been finished - too many other tasks on my plate. The following cvs checkout command: cvs -d :pserver:anon...@ifctfvax.harhan.org:/fs1/IFCTF-cvs co ueda ifctf-part-lib OSDCU will give you the source for uEDA, my part library and the board I've just got working. > If you could write a non-gui PCB layout tool, I'd be > even more impressed. That isn't my department - Ineiev is my PCB layout partner. :-) MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: My uEDA-designed open source hardware board works!
I've already posted this great news on the relevant project mailing list, but I thought I'd post it here too: Almost 5 months ago Peter Clifton wrote here: > Thanks. I had quick a look through, and I must say, the SDSL unit is a > very impressive project - far more complex than I'd imagined. > > Good luck with it, and thanks for the example. Well, I have some news: I have finally got this board physically built (sent gerbers to fab, got PCBs back, populated one of them) and it works! So far I only have the CPU subsystem populated (not the SDSL part yet), but I still find it amazingly cool that I have an MC68302 microprocessor system designed by me, it's running at ~16.67 MHz with no extra wait states, 16-bit SRAM and flash, I've got a working serial console port and I'm talking to it: my own little M68K debug monitor running on my very own hardware design! The following factoids make this success even more amazing: * It's my very first hardware design, and I chose something of this complexity rather than some toy traffic light controller or somesuch. * Being unhappy with the too-much-GUI-for-me EDA programs like gEDA, I wrote my own non-GUI, non-WYSIWYG, totally Makefile-driven EDA system (uEDA) to make this board and others in the future, and this board project is naturally uEDA's first. GUI-indoctrinated "professional hardware engineer" types may scream in horror at the thought of non-GUI, non-WYSIWYG EDA, yet I've designed a board of this complexity with it and it works! * Being a great fan of the UNIX Way of Doing Things (tm), I have used M4 footprints wherever possible in direct contrast to the strong admonitions against their use that are frequently expressed on this mailing list. Having heard comments like "I have had to throw boards out because of those awful M4 footprints", I naturally had some trepidations when I took the PCB and the box with parts to the assembly shop. But the people there didn't complain about any footprint problems, and when I had asked them specifically, the assembler told me they were fine. Oh, and I had completely skipped the common step of printing the board on paper and checking the parts against it, I had simply crossed my fingers and sent the gerbers to the fab. :-) * Aside from some initial confusion resulting from the assembly shop having populated one of the SOICs backwards (I take some blame there too for not having inspected it visually before applying 5V), everything worked exactly right on the first try! I had the code for the microprocessor ready well before the PCBs arrived, so when I had the board assembled, I went straight to the device programmer to burn two 29F040s, popped them into the PLCC sockets, applied power and guess what, instead of magic smoke coming out there is a working interactive monitor prompt on the serial port! A lot of kudos go to Ineiev too as it's his PCB layout - great job! MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: )(
Ineiev wrote: > I wonder if I may ask to keep GL code optional. most my machines have > no GL-enabled hardware; and on the computer that has GL support, it is > so weak that PCB+GL is quite unusable with any non-trivial board --- > much worse than traditional PCB . sorry. I second that! I don't use single-user personal computers, instead I run applications like PCB on a multiuser timesharing host (a machine in a machine room with no humans present nearby) and direct the X11 DISPLAY to a traditional 1980s-style Ethernet-attached X11 terminal, so I want a PCB HID that works in the traditional 1980s X11 way. I would run the original Xaw PCB if I could, but I need to be able to open current .pcb files. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Flexibility and capability
John Doty wrote: > To a lesser extent > that true of pcb, too (as we have heard from an xcircuit user). And a uEDA user too! My first PCB laid out by Ineiev in GNU PCB from my uschem schematics is currently being fabbed. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind and buried vias?
Bill Gatliff wrote: > The latest generation of BGA parts have so many pins on the package, > packed so tightly together, that it isn't possible to get all the > signals out of the chip in two layers and still have the traces large > enough to meet specs. > [...] > I'm told that the OMAP3430's Package-on-Package configuration > requires at least six layers to get all the signals out. Ugh. OK, that explains the need for a lot of layers. But how does the need for blind/buried vias arise? MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind and buried vias?
How about we move this thread back to its original topic of blind and buried vias, not arguments regarding whether or not PCB is part of gEDA. I have some questions out of plain curiosity: completely aside from the question of how they ought to be handled by GNU PCB or any other PCB design tool, I wonder how these blind/buried vias work at a more basic level: 1. How are blind/buried vias made physically? I thought they glued the layers together first, then drilled the holes. 2. How are they represented in the Gerber+drill file set that passes from the PCB design tool to the fab? I'm asking out of plain curiosity - I hope that I never have to make a board with such vias as I've heard that they add a bit of sadomasochistic flavor to board bringup/debug efforts - but then I guess some boards are so cramped for space that you can't avoid them... MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb option --fab-author not working
Ineiev wrote: > But actually it does not claim this is fab author, it intentionally > reports the Unix user who saved the board. if you want to save author > info in the PCB you probably can use attributes. In my code of honor a PCB designer who lays out an Open Source Hardware board deserves to have his/her name on the silk screen, at least on the bottom side if there is no room on the top component side. Once the fame/honor attribution of the OSH project contributor(s) has been secured in this manner, the header comment in the .pcb file becomes less important IMO. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Strange problem with gerber export
Ineiev wrote: > Your locale was Russian. PCB output aperture sizes as 0,025 instead of 0.025. This is a perfect example why I consider the whole concept of locales and i18n to be a diabolical abomination. Whoever invented these evil things should be taken out and shot as an enemy of the People, and in the meantime everyone ought to abstain from using these things as a universal protest. I generally prefer to use non-POSIX UNIX systems such as V7 or 4.3BSD that don't have any i18n/locale abominations in the first place, but when I'm forced to use a POSIX-pandering system such as Linux I always make sure the locale is set to C. I also always configure my timezone to GMT/UTC as a matter of principle, being an internationalist. Programletarians of all countries, unite! MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: More robust support of multi-part symbols.
DJ Delorie wrote: > So, in my dream world, there's exactly one 2-NAND gate symbol, for > example. Mapping that to a specific gate in a specific part, with > pinning, power, manufacturer and vendor information, pricing, and > footprint infomation, is all done by a separate database (in whatever > form). That dream world already exists; it's called uEDA. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Needs create a language (english, spanish...) specific list?
Gabriel Paubert wrote: > I use three languages almost everyday (I'm french, I live in Spain and > I work for an international research institute). However, when I am in = > front of a computer, I think in english. Ditto! English should be the one and only international official language of Computing Machinery! I am vehemently opposed to any form of i18n/NLS, and I always run ./configure scripts for software that has such things with --disable-nls as a matter of principle. And I'm saying this as a non-American and a non-native English speaker myself! I also run all my computer clocks on GMT/UTC because I don't believe in local time. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: RFC: Towards a better symbol/package pin-mapping strategy (was: Re: slotting and power pins)
Bert Timmerman wrote: > got cvs co working > Simply typing make barfs the following: > [snipped] Your OS is too modern. Install something that is at least 25 years obsolete and try again. Seriously though, Ineiev has already told me that ultra-modern versions of gcc refuse to compile uEDA as distributed by me. So you need to apply some local patches of your own to port it to your modern OS. uEDA is developed on/under/for 4.3BSD-Quasijarus, my own version of UNIX that very faithfully maintains the traditions of UNIX Version 7 and Berkeley VAX UNIX. The C compiler maintains strict compatibility with the K&R C standard aka C78. uEDA does however compile OK under Slackware 10.2 and RHEL 4. Lots of warnings, but no fatal errors, so I just ignore them. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: RFC: Towards a better symbol/package pin-mapping strategy (was: Re: slotting and power pins)
Bert Timmerman wrote: > > cvs -d anon...@ifctfvax.harhan.org:/fs1/IFCTF-cvs co ueda > > [...] > > copy-pasting the cvs command to a Bourne shell on my workstation gives > that a password other than is required. Oops, forgot the :pserver: part; try the following: cvs -d :pserver:anon...@ifctfvax.harhan.org:/fs1/IFCTF-cvs co ueda MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: RFC: Towards a better symbol/package pin-mapping strategy (was: Re: slotting and power pins)
Bill Gatliff wrote: > At the risk of going OT, I'll add that as I get better at following the > above strategy--- which is particularly helpful with more complex parts > like microcontrollers--- I get really frustrated at gschem's strong > association between pin numbers on the symbol, and pin numbers on the > footprint. That's just... wrong. It would be nice if there was an > additional "layer of abstraction" somewhere between the symbol and > footprint, such that actual pin assignments weren't made until the > footprint (and slot, if necessary) were specified. Until that point, it > doesn't really matter anyway. That's exactly how I've implemented it in uEDA. > As a "mostly software" guy, I think about schematic capture the way I > think about C code: Ditto! > The solution might be to get rid of physical pin numbers in symbols > entirely, and replace them with "virtual pin numbers" that map to > physical pin numbers in some intermediate processing step. For example, > a 7400 symbol might have pin "numbers" A, B, and Y, and then our DIP16 > footprint would have pin "numbers" A.1, B.1, and Y.1, A.2, B.2, Y.2, > etc. Wow, just like in uEDA, except that you chose '.' as the separator character and I chose ':' in uEDA for that purpose. > A.1 1 > B.1 2 > Y.1 3 > A.2 4 > B.2 5 > Y.2 6 > GND 7 > ... > VCC 14 Even your proposed table format is *exactly* the pinout mapping file format used by uEDA except for the slot separator character. Is someone reimplementing uEDA here? How about the other way around? Anyone feel like porting the gschem GUI to operate on the uschem file format? That's the only remaining piece that's missing from the uEDA solution. cvs -d anon...@ifctfvax.harhan.org:/fs1/IFCTF-cvs co ueda The documentation is still incomplete though. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: protoexpress.com and copper thieving
Darrell Harmon wrote: > I have used the no touch service from http://www.protoexpress.com They are > in Sunnyvale, CA, and do good work. I like their deal, it's the best I have found so far for what I want. The only remaining concern I need to resolve before I settle on them as the recipient of my gerbers is the following: back in early 2007 DJ has posted the following on this list: > protoexpress auto-adds copper thieving, which would mess up my > isolation gaps (I've emailed them asking about it). Is copper thieving the trick whereby the fab adds little isolated copper squares in places where the customer's gerbers call for a complete clearing? Does DJ or anyone else here know if protoexpress still does that on their "no touch" service or not? My PCB has a section where the DSL circuit comes in from the phone company - as that's basically a phone line that can potentially have all kinds of nastiness on it, I prefer to have good isolation - hence copper thieving (if I understand the term correctly) would be undesirable in that area. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Freedog-like groups in Southern California?
Hello gEDA/PCB users, I wonder, is there perchance a local user group in Southern California similar to the Freeedaug on the East Coast? Or if there is no established group, are there any individual gEDA/PCB users in Southern California who might be interested in starting such a group? I would really like to find someone local from whom I could learn how to use PCB for simple tasks. Because of the way my brain is wired, tasks that are inherently graphical by their nature (such as PCB layout) are very unnatural and difficult for me, so I know I will probably never do my own complex PCB layouts of professional quality, instead I'll have to outsource them like I did with the OSDCU (Ineiev did an outstanding job in my opinion!), however, I would like to at least be able to do simple things with PCB. I would like to be able to view existing layouts and examine areas of interest to me, make minor edits and do my own layouts of very simple boards that have maybe 2 or 3 components and fewer than 10 or so traces. My difficulty is that my disability when it comes to graphical tasks makes it harder for me than it would be for an average person, so whereas a "normal" person would have no difficulty learning how to use PCB from the various resources on the web, I think I would need to learn from someone I can interact with in person. Hence I wonder if there is anyone local in Southern California who would be willing to teach me some basic use of the PCB GUI. I do have pcb-20081128 installed and working with the lesstif HID on my Slackware Linux laptop. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-20081128 is broken
I wrote: : But the thing is, when I tried building with the GTK HID (out of : desperation), it behaved exactly the same way! (Worked OK with -x ps, : but trying to bring up the GUI produced an identical-looking crash.) : : I'll see if I still have the binary from that build around somewhere. Scratch that. I've found the binary and running it under gdb reveals that lesstif functions are being called, i.e., it wasn't really rebuilt with the GTK HID. That was when the lesstif build wasn't working and I tried to reconfigure with GTK and remake without cleaning the tree out properly. But now I've got the lesstif HID working and that's the one I want to use, so it's all that matters. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-20081128 is broken
DJ Delorie wrote: > Most people build for GTK. But the thing is, when I tried building with the GTK HID (out of desperation), it behaved exactly the same way! (Worked OK with -x ps, but trying to bring up the GUI produced an identical-looking crash.) I'll see if I still have the binary from that build around somewhere. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-20081128 is broken
DJ Delorie wrote: > It's long since been fixed in cvs/git. > >/* homedir is set by the core */ > + home = homedir; >home_pcbmenu = NULL; With this patch PCB compiles and works - thanks! I still scratch my head at how such a bug could make it into a release - I mean, shouldn't it cause an instant crash on startup on just about any system? But oh well, I now have a working PCB installation that can open OSDCU.pcb in the lesstif GUI, so I'm happy. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb-20081128 is broken
Hello,
I'm having a difficulty getting a recent version of pcb to work on my
system. First a little background: Ineiev has finished the layout of my
OSDCU board (he has done a great job of it too!), but before I run
pcb -x gerber OSDCU.pcb and send the resulting files to the fab, I would
really like to view the layout in the PCB GUI first. So far I've been
checking the progress of the work by running pcb -x ps OSDCU.pcb,
lpr'ing the resulting PostScript and viewing it on paper, but this
method is rather limiting - I would like to examine the routing of
certain traces as they wind their way from layer to layer, and that is
really hard to do on paper - being able to bring up the GUI and
highlight the net(s) of interest to me would be much preferable.
The problem is that the only version of PCB that I have working with the
GUI is 20060822, and it's too old to open Ineiev's work: his OSDCU.pcb
has this line in it:
FileVersion[20070407]
So I went out to look for a newer version of pcb. Going to
pcb.gpleda.org and selecting "Downloads" in the sidebar on the left
takes me to the download page on Sourceforge, and the only thing that's
listed there is the 20081128 release/snapshot. Judging from the header
comments that's what Ineiev has used to, so it seemed like the right
version. I have downloaded it, untarred it, configured it for the
lesstif HID and run make - compiled fine. However, attempting to run
the resulting binary in the GUI mode results in a SIGSEGV crash.
(Running it with -x ps works fine though.)
I have finally found the time to investigate the crash with gdb, and
what I have found is really bizarre. The crash occurs in this code in
hid/lesstif/menu.c, and my simple peasant mind can't comprehend how
could this code possibly ever work on anyone's system:
Widget
lesstif_menu (Widget parent, char *name, Arg * margs, int mn)
{
Widget mb = XmCreateMenuBar (parent, name, margs, mn);
char *filename;
Resource *r = 0, *bir;
char *home_pcbmenu, *home;
int screen;
Resource *mr;
display = XtDisplay (mb);
screen = DefaultScreen (display);
cmap = DefaultColormap (display, screen);
/* homedir is set by the core */
home_pcbmenu = NULL;
if (home == NULL)
{
Message ("Warning: could not determine home directory (from HOME)\n");
}
else
{
home_pcbmenu = Concat (home, PCB_DIR_SEPARATOR_S, ".pcb",
PCB_DIR_SEPARATOR_S, "pcb-menu.res", NULL);
}
[rest of function snipped as it never gets that far]
Here we have an automatic variable declared inside the function
(char *home), it is never initialized, then it is compared with NULL,
and if not NULL, it is passed as the first pointer argument to Concat().
But it's an automatic variable that is never initialized! Its value
will be random garbage on the stack, and that garbage (which happens to
be nonzero, 0x1e0 specifically on my Slackware Linux system) is passed
to Concat() as a pointer argument. Concat() then passes this argument
on to strlen(), where the SIGSEGV occurs.
This has me really baffled. I'm not trying to compile modern pcb on a
VAX or anything like that, I'm building it on a vanilla Slackware 10.2
system, i.e., reasonably modern Linux, but in any case the code is so
fundamentally broken that I can't understand how could it have possibly
ever worked on anyone's system. How did this code get released, and how
are Ineiev and others seemingly able to run and use it?
And the biggest question of all, what can be done about it?
MS
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Re: gEDA-user: Looking for PCB fab recommendations
Peter TB Brett wrote: > > * SnPb finish - this one is an absolute requirement for ideological / > > philosophical reasons, RoHS crap is *not* acceptable. > > In the nicest possible way, WTF? RoHS is an evil abomination that is reprehensible to the core of my being. The whole underlying philosophy behind RoHS is that "bad" elements should be eliminated from electronic products because those products will ultimately be thrown out and put into landfill. I am fundamentally at odds with that ideology because I don't believe that any computing, communication or other electronics should *ever* be thrown out. The idea of buying a new computer every few years and tossing the old one out is fundamentally reprehensible to me. Computing machinery should be passed through generations from father to son to grandson. I am using 1970s technology to compose this E-mail and I plan on continuing to use it well past 2038. The lead-free crap suffers from the severe problem of tin whiskers. The f***heads behind it don't care because they expect their crap to be thrown into trash long before tin whiskers grow, but it is a real problem for anyone who wants his electronic creations to outlast his own lifetime. I want my SDSL gadget to be usable to my great-great-great- great-grandchildren, so they can still connect their networks at 384 kbps even when everyone else around them has gone to exabits per second. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for PCB fab recommendations
Ineiev wrote: > BTW why unplated holes may be preferable for this case? Sentimental reasons: I want my SDSL gadget to be just as "professional" as all those "mainstream" existing SDSL CPE products that fill eBay. I have *never* seen a "real" commercial product PCB on which the holes accommodating the plastic mounting tabs of non-Ethernet RJ connectors were plated. The SDSL gear is no exception: every single piece of SDSL CPE I've ever taken apart has had a plastic RJ connector for the DSL port (either 6-pin or 8-pin, but never the shielded type used for Ethernet), and the holes where the plastic mounting tabs go are unplated. Hence I want the same on my board. Right now I'm leaning toward pcbfabexpress.com as my fab choice. I'll call them tomorrow to ask if they can do SnPb finish (late night here right now). They charge $50 extra for unplated drill and I'm OK with that. (That's for the whole order, not per board.) MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Looking for PCB fab recommendations
Hello gEDA/PCB users, Ineiev is almost done with the layout of my SDSL board, and I am now looking for a place to fab it. I am posting here in the hope that some kind soul can suggest a PCB fab shop that would be a good fit for what I want to build. Here are my board features: * Simple rectangular PCB shape, 130x165 mm (about 33 sq in) * 4 layers (I was originally planning on 6, but Ineiev got it laid out in 4 layers without having to increase the size!) * Soldermask on both sides (color doesn't matter) * Silk screen on both sides (color doesn't matter) * SnPb finish - this one is an absolute requirement for ideological / philosophical reasons, RoHS crap is *not* acceptable. * Both plated and unplated drill. Some parts have plastic mounting elements and I want unplated holes for those. * 8 mil rules should be good enough (Ineiev can correct me if I'm wrong on this one). Other considerations: * Quantity: 1 to 5 boards depending on the pricing * I would prefer a shop somewhere in USA for the ease of shipping, payment, communication, avoidance of customs etc. * I'm hoping for a price range somewhere around $500-700. Would anyone here happen to know of a PCB fab shop that can do what I want? TIA, MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Can we fix the HTML stripping on this list?
Dave McGuire wrote: > I vote for automatic and immediate unsubscription of people who > post messages in HTML. I second that! MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: "Inherited" attributes view in gschem
Peter Clifton wrote:
> What does the pinout file look like?
#pin name pin number
A:1 1
B:1 2
Y:1 3
A:2 4
B:2 5
Y:2 6
GND 7
Y:3 8
A:3 9
B:3 10
Y:4 11
A:4 12
B:4 13
Vcc 14
> > PinToNet GND GND;
> > SymOnPin GND "gnd-1";
>
> What do last two lines above two lines do?
PinToNet connects the pin named GND to the net named GND, SymOnPin
illustrates that connection graphically. uschem-netlist cares only
about the former, uschem-print cares only about the latter. If only one
is present or if the two conflict, uschem-check will flag a DRC error if
run with the symbol files present.
The above is a good illustration of uEDA's principle of orthogonality:
the component information, the netlist (electrical interconnect)
information and the graphical information are kept orthogonal in the
schematic source code language. One rule is that graphical symbols
(*.sym files) are merely a decoration and must not be needed for netlist
generation - thus uschem-netlist does not read them or look for them at
all; *.usch, MCL and pinout files must be sufficient for generating the
netlist for the circuit being described.
The symbol used with the SymOnPin decoration must have exactly one pin
and may not be rotated. The SymOnPin trick is the only way in uschem to
have two abutting pins, i.e., two pins whose active ends are at exactly
the same (x,y) coordinates, otherwise that is not allowed.
Even though I have invented my own language for schematic sheets (*.usch),
the symbol (*.sym) format is basically borrowed from gschem with a few
tweaks. Many gschem symbols may be used totally unchanged with uschem,
but some uschem symbols in the IFCTF part library use new uschem features.
Here is my 7400-1.sym:
L 300 200 300 800 3 0 0 0 -1 -1
L 300 800 700 800 3 0 0 0 -1 -1
L 300 200 700 200 3 0 0 0 -1 -1
A 700 500 300 270 180 3 0 0 0 -1 -1
V 1050 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1100 500 1300 500 1 0 1
{
T 1100 550 5 8 1 1 0 0 1
pinnumber=%d
T 950 500 9 8 0 1 0 6 1
pinname=Y
}
P 300 300 0 300 1 0 1
{
T 200 350 5 8 1 1 0 6 1
pinnumber=%d
T 350 300 9 8 0 1 0 0 1
pinname=B
}
P 300 700 0 700 1 0 1
{
T 200 750 5 8 1 1 0 6 1
pinnumber=%d
T 350 700 9 8 0 1 0 0 1
pinname=A
}
Here is my gnd-1.sym:
P 100 100 100 300 1 0 1
{
attr forcenet=GND
}
L 0 100 200 100 3 0 0 0 -1 -1
L 55 50 145 50 3 0 0 0 -1 -1
L 80 10 120 10 3 0 0 0 -1 -1
gschem's net= attribute (which I consider to be a horrendous kludge) can
never work in uschem because the *.sym files are excluded from the
netlist generation process by design. All net connections must be
declared in the *.usch files using the Net object, the GraphNet object
or the PinToNet decoration. If you want to make a net connection which
is not represented graphically (I'm not passing judgment on the wisdom
of doing so as uEDA follows the traditional UNIX philosophy of providing
mechanism, not policy), you can use the non-graphical Net object (legal
even in an otherwise graphical schematic sheet) or a PinToNet decoration
with no corresponding SymOnPin - if the pin in question isn't shown on
the symbol, that won't even be a DRC error.
The forcenet= attribute used in the decorative symbols such as gnd-1.sym
is only for DRC (uschem-check) and for the future graphical schematic
editor.
You can get a much better idea of how it all works by checking uEDA, my
part library and a sample board project out of my CVS:
cvs -d :pserver:anon...@ifctfvax.harhan.org:/fs1/IFCTF-cvs co ueda
ifctf-part-lib OSDCU
MS
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Re: gEDA-user: "Inherited" attributes view in gschem
Peter Clifton wrote:
> Could you send an example as to the syntax used please?
In the MCL:
part 74LS00:
device=74LS00
footprint=SO14
description=Standard logic IC, SOIC package
manufacturer=Generic
npins=14
pinout=7400.pinout
U4:
# M68K bus read and write strobes
part=74LS00
In a schematic sheet:
Component U4pwr graph "74xx-pwr" 21900 1700 {
DisplayAttr refdes 22800 2700 10 0 6;
DisplayAttr device 22050 2000 10 90 0;
PinToNet GND GND;
SymOnPin GND "gnd-1";
};
Component U4urds graph "7400-1" 14300 4200 {
(slot="1")
DisplayAttr device 14600 4200 8 0 0;
DisplayAttr refdes 14600 5100 10 0 0;
};
Component U4uwrs graph "7400-1" 14300 3000 {
(slot="2")
DisplayAttr device 14600 3000 8 0 0;
DisplayAttr refdes 14600 3900 10 0 0;
};
Component U4lrds graph "7400-1" 14300 1500 {
(slot="3")
DisplayAttr device 14600 1500 8 0 0;
DisplayAttr refdes 14600 2400 10 0 0;
};
Component U4lwrs graph "7400-1" 14300 300 {
(slot="4")
DisplayAttr device 14600 300 8 0 0;
DisplayAttr refdes 14600 1200 10 0 0;
};
> Is it compatible with (or an extension of) the gEDA file format?
No, as you can see from the above it's a totally different file format
I've had to invent. It's parsed like C in that there is no syntactic
difference between spaces and newlines.
I've made the decision to invent my own file format for uschem instead
of trying to kludge my way around the gschem format, and now I'm paying
for it by not having any graphical editor for my schematics, just batch
tools for making PostScript and netlist output.
I think the only way to make uEDA a complete usable system would be for
me to hire someone to take the gschem code and make a version that
operates on the uschem file format (I strongly doubt being able to do
that myself as I'm so not a GUI person), but I probably won't have the
money to do that for a long time...
I have graphical schematics for the OSDCU in the uschem format because
they were originally drawn in gschem and converted to uschem (it's a
semi-automated process with a lot of manual assistance) later when I had
lost the one machine I had with a usable gschem setup, and I can eeck by
with vi followed by uschem-print|lpr for the current "finishing touches"
editing phase, but I don't know what I'm going to do for the next project.
MS
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Re: gEDA-user: "Inherited" attributes view in gschem
Peter Clifton wrote: > Given a blank canvas, my personal preference would be that as an > internal representation, attributes are simply name=value pairs without > any coordinates or other graphical representation. > > The text you see on the schematic would be an entity without its own > text, but instead reference the logical attribute. This is exactly what I have implemented in uEDA/uschem. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Breadboard drawings with pcb?
Ineiev wrote: > Hmm, I wonder if your lpr outputs onto reusable media. No, it does not. I kill trees. I know, I am a bad boy. Setting up a system for viewing PostScript on an X11 display that's usable from my 4.3BSD-Quasijarus VAXen is on my *very* long list of things I'd like to get done some day if I have the time. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Breadboard drawings with pcb?
John Doty wrote: > You can print using the print.scm from a text terminal or script as > long as there's an X server for gschem to flash the page on. A minor > annoyance, I think. That "minor annoyance" was enough for me to write uschem (from scratch) to replace gschem. uschem currently has no GUI at all, in fact there is no program named "uschem" like gschem, there is only uschem-print which generates PostScript and uschem-netlist which generates a netlist, both traditional UNIX-style non-interactive programs intended to run from a Makefile. uschem itself is actually a language I have invented for schematics, not a program. What's currently missing is uschem-edit, a graphical editor for files in the uschem language. Right now I just do vi OSDCU_??.usch, then check with uschem-print | lpr, which I admit is rather poor when I need to edit the graphical aspect of my schematics. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Breadboard drawings with pcb?
Chris Smith wrote: > I keep seeing references to uEDA and uschem, but I can't find any > mention of it on the gEDA page or with Google. What is it? Where is it?= The following cvs checkout command: cvs -d :pserver:anon...@ifctfvax.harhan.org:/fs1/IFCTF-cvs co ueda ifctf-part-lib OSDCU will give you uEDA, my part library for it and a sample project done with it. The documentation under ueda/doc is still in the process of being written. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Breadboard drawings with pcb?
Ineiev wrote: > BTW I couldn't achieve > this with gschem --- it doesn't work from text terminal for me. That is exactly why the circuit which you'll be laying out has been done in uschem instead of gschem! MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
Gabriel Paubert wrote: > Sorry, I did not express myself well, I meant the TI part (SN75LBC784), > that one does not appear in stock in any of my providers. I have it in my design for the sentimental value - I just like EIA-423 - and I have 25 of those parts in my little grabby hands, enough for my own play. If that ISP follows through on wanting 100 of my units (or if someone else expresses a similar interest), *and* if we can somehow solve the RS8973 situation, then I'll revise my design and respin the PCB for whatever is available in the requested quantity. But I don't want to think about that at the present time. Right now I just want to get the damn thing finally built after all these years, just for my own personal sanity, just to prove to myself that I can design and build a piece of hardware of that level of complexity - even if it's only a one-off piece that can never be made in volume. I've been working on this project since 2006, and there were several times over the last 2.5 y when I was just about ready to put the finishing touches on it and send it off to layout, but every time I had a context switch. If I have a context switch, the project goes into the background and won't resurface for another few months at least. Then the cycle repeats. With Ineiev getting ready to do the layout for a price I can easily afford on my hobby budget, I want to actually make it happen this time. At this point I want as little change to my design as possible. Basically I want to change my currently existing design only if it is rather certain that the circuit won't work if I give it to Ineiev with my current netlist as it stands. If the circuit has a high chance of working as it currently stands with the current netlist and the parts I physically have on hand, I want to lay it out and build it as it stands. (I'm going to have a couple of local friends who are real HW engineers review my schematics for the cost of me taking them out to lunch to help me answer that go/no-go question.) If I start making bigger changes to my design, I'll have another context switch to other pressing life needs and the gadget won't get built for at least another year... MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
Gabriel Paubert wrote: > Indeed, while some distributors apparently still have a non-negligible > stock of Conexant's RS8973 (www.americaii.com claims 1943), Thanks for the pointer, I'll check it out! > the transceiver is obsolete. Yes, Mindspeed doesn't want to make, sell or support it any more because they have M289xx as the "new replacement". Care to know why they obsoleted RS8973 in favor of M289xx? RS8973 was open source-friendly, whereas M289xx is completely closed. See this page for the full gory details: http://ifctfvax.Harhan.ORG/OpenSDSL/chips/mindspeed.html MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
John Griessen wrote: > but then, the international reach of the internet along with closed borders > and regulated trade may put me out, way out :-) You mean Ineiev's offer being 15-40 times cheaper than what you and everyone else has offered? Yeah, that pretty much guarantees that I'll go with him. :-) Yes, I know the saying that you get what you pay for. But this is a *hobby* project on which I don't expect to make any money ever. I have mentioned the possibility of one ISP wanting me to make 100 of those units, but after I had made that post I have rechecked the availability of all the parts on my BOM and confirmed what I had feared: the RS8973 SDSL transceiver chip, the one that the whole design revolves around, is no longer available by any means other than buying other old SDSL routers on eBay and desoldering that chip. I have 10 such sacrificial routers in my stash which have been acquired for that specific purpose. There is one other chip in my design which I would like to keep in there for sentimental reasons (TI SN75LBC784 EIA-423 transceiver), and it has also apparently become unobtainium. I have 25 of those on hand. Ineiev's price is something I can actually pay out of my own personal hobby budget and it won't bother me that I'll be spending the money on the design of a board of which I'll never be able to make more than 10 or so due to part unavailability. But in order to pay the kind of layout labor prices everyone else is asking (which I have to admit are very reasonable), my project would need to get some outside sponsorship. Under different circumstances this might not have been a problem, but who in the world would sponsor the NRE for a project that can't be built in any volume beyond a few units due to part unavailability? > I was wondering if this fit with anything I am doing? > Michael, does this SDSL link have any better > deterministic time you can phase lock to? I need to understand the question a little better. I can give you my phone # off-list. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
Joerg wrote: > It sure does sound reasonable. Probably what my layouter would have > quoted me also (and no, he won't be an option here because he doesn't > use gEDA). Well, I don't use gEDA either, I use uEDA for the schematic/BOM phase of the design, but that doesn't really matter, I just export PostScript/PDF schematics, a netlist and various BOM formats. Your layouter *would* actually be an option for me, but only if he charges significantly less than what others on this list have already offered, which I indeed find rather unlikely. If two layout contractors charge approximately the same rate, but one uses PCB and the other uses something proprietary, I would choose the one who uses PCB because: * Making uEDA export the netlist in other formats would be extra work for me; * I already have all the footprints for my board in the PCB format, but if the layout contractor uses something else, he would have to redraw those footprints and charge me for that extra time; * Having the layout done in PCB would make it easier for me to "own" the final product. (I'm not talking about the legal ownership crap which is implied if I hire someone to do a layout for me, I'm talking about being able to do whatever I like with it afterward in the technical sense.) MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
Kai-Martin Knaak wrote: > That is, you already did the initial gsch2pcb run? I did the uEDA equivalent thereof. I use uEDA rather than gEDA, but the output PCB elements and PCB netlist format are exactly the same. All nets are meaningfully named. > My rule of thumb for an economical size, that is still no pain to layout > is twice the combined area of all components. Would having 2 extra layers make it less pain to fit into a smaller size or not? Here is my issue, and it's a sentimental one: my SDSL modem design is the functional equivalent of a CSU/DSU (sync serial on the other end, no Ethernet), whereas all competing SDSL CPE devices are full routers. One particular SDSL CPE router that has caused me an untold amount of grief in the past was the (in)Efficient Networks 5851, and my project's goal has basically been to replace that abomination. The PCB inside EN 5851 has 6 layers (I can tell by the layer stackup markings on the side), and its functional section is approximately 130x165 mm. I have previously thought about fitting my OSDCU board into that form factor and putting it into the enclosure from a gutted EN, but I have subsequently rejected that plan for a number of reasons. I now want to make it a simple rectangular PCB, but I'm keeping the 130x165 mm dimensions. (EN's design probably wasn't metric and their PCB was an odd non-rectangular shape anyway, but I'm approximating and I like metrics.) I suppose I could make the PCB bigger than 130x165 mm if that makes the layout labor cost much cheaper, but then we'll have a device with CSU/DSU functionality that is physically larger than a competing device which is a full router, and that somehow feels "wrong" psychologically. > > Again because the project is non-commercial, mass production is not a > > consideration. > > Maybe small series :-) There is one ISP I am currently in negotiations with, they say they have some existing customers with an SDSL-to-V.35 arrangement, but those customers are served from some very very old DSLAMs. The ISP says they would like to migrate those customers to a newer DSLAM platform (still old, but not as old as the other one), but apparently their existing SDSL-to-V.35 CPE won't work with the other DSLAM. I am trying to convince the ISP to fund the NRE cost of my OSDCU (basically the cost of the layout labor I'm soliciting right now) so they can use it as their new SDSL-to-V.35 CPE solution that works with all DSLAM flavors. The ISP's response so far is that *if* they are interested (it's still an if), they will want "maybe 100 units". Well, 100 units is not a low quantity in my book - but again the whole deal is still hypothetical. I still consider my project to be non-commercial though because I want to build it regardless of whether or not that 100 unit ISP deal comes through, just because *I* want to have the toy for my own use on my own SDSL line. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
Kai-Martin Knaak wrote: > A bill of material (BOM) woud help to estimate the necessary effort. The > BOM should include the package of the parts, especially of the connectors > and special ICs. http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/OSDCU-AA.bom http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/shortbom.txt > So it can be seen whether or not all footprints are > available in the existing pcb libs. I have already drawn all the necessary footprints in the PCB format. I have provide them either in the form of a file-per-element tarball (each file inside named after the refdes) or in the form of a .pcb file like you would get from an initial gsch2pcb run. > Maximum PCB size matters. An otherwise unspectacular layout task can get > really nasty if the maximum allowed size is below a certain threshold. > Again, a BOM would help to estimate. Because it's a totally non-commercial hobby project, terms like "maximum allowed" are not applicable. The size I have specified (130x165 mm) is only a suggestion - I had come up with it by measuring the size of an existing DSL modem board whose circuit complexity appears similar to mine. But again, it's only a suggestion - if a different (larger) PCB size would result in a significantly lower layout labor bill, go for it! > If cost is a factor, why not aim for four layers but slightly larger size? The only cost that is a factor is the layout labor cost, and I thought that having more layers makes the layour labor easier. The cost of physically making the PCB is not a factor - I have checked pcbexpress.com and their price for a 6-layer board of the size I have in mind is perfectly affordable, which is all that matters. Again because the project is non-commercial, mass production is not a consideration. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
> Why not use RoHS chips? You can use those with leaded solder, as long > as they're not BGA or CSP. Yeah, that's what I do when SnPb components aren't available, but if they are available, I use them as a matter of principle. My understanding is that if one uses RoHS parts, then tin whiskers can still grow even if one uses good SnPb solder. I am bothered by tin whiskers because I believe that computing machinery should outlast the average human lifespan and should be passed from father to son to grandson. The word "obsolete" is banned from my vocabulary. That's actually the root of my beef with RoHS: lead in electronic devices can't cause any harm to the environment if those devices will never, ever, ever be thrown out, so the whole RoHS concept is fundamentally based on the premise that electronic devices will be tossed at most a few years after they are made because they'll be "obsolete". That ideology is anathema to the core of my being, I still use 1970s computing technology and plan on continuing to use it well past year 2038, meaning that some time soon I'll have to change time_t from a signed to an unsigned long. (Extending it to 64 bits would break too many things I'm afraid.) > Double-check the SRAM timing; 70ns seems too slow for a 25 MHz cpu. Well, the M68K bus protocol gives the target device two clock periods (80 ns at 25 MHz) to respond with the data when set to 0 wait states, but then of course there are setup and hold times, propagation delays, transmission line effects and other "real hardware" stuff that makes my software&logic-minded head hurt... I actually plan on populating a 16 MHz MC68302 part on the first board because that's what I already have on hand and because it'll be plenty fast for Flavor B operation, and even if I were to run it at 25 MHz and the SRAM is too slow, I could program it for 1 extra wait state, but you are right, eventually I will want to run it at 25 MHz with 0 wait states to get the full performance for the on-the-fly protocol converter mode of operation, and at that point 70 ns *might* turn out to be just a tad too slow when all the annoying "real HW" factors are figured in. I already have 70 ns SRAM parts on hand, but I should check to see if I can get faster ones in the same footprint. 5V SRAM parts are a problem unfortunately... > Put two 0603's between circuit and chassis ground. For my furnace > controller, I populated these with a 10M resistor and a 0.1uF > capacitor. Thanks for the advice. So this arrangement is better than having the two grounds connected with a 0 ohm resistor or disconnected altogether? What's the underlying rationale? And I'm still looking for someone to do the layout for a price I can afford... (So far I have no clue as to what price range to expect, not even an order-of-magnitude estimate.) MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Outsourcing PCB layout
Hello fellow gEDA/PCB users, I hope this post is not too off-topic/inappropriate for this list. I have an open source hardware design (an SDSL hacking board) that's getting close to entering the layout phase, and I will soon need to hire someone to do the PCB layout. (I have to outsource it because it's a task well outside my skills range.) Right now I'm just looking for a very rough guess order-of-magnitude estimate of how much this is going to cost me, so that I can tell whether I can foot that bill on my own or if I'll need to procure some sponsorship before this project can proceed. It's a totally non- commercial open source hardware design, I share the design freely with the world and I'll do the same with the PCB and Gerber files which I'll be paying someone to create, and if I do make and sell any physical hardware units, I'll sell them for the cost of production without any profit margin. If anyone here does PCB layouts for hire, I would appreciate it if you could take a quick look at my summary below and give me a rough approximate estimate of how much you would charge to do this layout. I would prefer for it to be done in PCB so that the resulting product will be in an open source format, but nonetheless my main overriding concern is cost, so in the admittedly unlikely case that person A offers to do it in PCB, person B offers to do it in some proprietary format and person B charges significantly less than person A, I'll have to go with person B - but again I think that scenario is very unlikely because I would imagine that those into proprietary tools are likely to be more commercially-minded, be less friendly to non-profit hobbyist open source projects and charge more. Summary of the board design that needs to be laid out: * Schematics: 10 B-size sheets; the circuit complexity should be roughly equal to that of an average DSL "modem" of the older generation that hasn't been shrunk down to one chip. * Estimated board size: I would like to fit it into a 130x165 mm 6 layer PCB if possible (again matching the average DSL "modem"). * No BGAs, 3 QFPs, the rest is mostly SOICs, TSOPs and SMT discretes, very few TH parts. * MC68302 microprocessor (QFP) with 20 address lines and 16 data lines wired, non-multiplexed; these buses need to go to two 8 bit wide SRAM chips, two 8 bit wide flash chips (covering the 16 bit wide data bus), the SDSL transceiver chip (only 8 address lines and 8 data lines) and an FPGA (13 address lines, all 16 data lines). * A lot of synchronous serial data and clock signals for the SDSL data path, including 4 muxes. * Mostly digital, but there is a small analog section between the SDSL transceiver chip and the jack. * No RF, the fastest signals would be the M68K bus which I may want to run at up to 25 MHz. Additional documentation: Project home page: http://ifctfvax.Harhan.ORG/OpenSDSL/ Schematics as they stand currently: http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/OSDCU_schem.pdf http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/OSDCU_schem.ps The design is done in uEDA, my own offshoot of gEDA which I'm in the process of polishing up for release. I don't expect the person hired to do the PCB layout to mess with uEDA, but I can export the netlist in the PCB format as well as a bundle of PCB elements for all components. Design spec (very detailed): http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/hwdesign.txt That's all I have for now. I hope someone is willing to do the PCB layout for a price I can afford. :-) MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Teaching credentials (was geda cygwin package)
Joerg wrote: > But then lots of road blocks are thrown > in front of them. Like having to first get teaching credentials and so > on. Costs time you may not have, and money. I really don't understand > why someone who explains electronic design to students and has decades > of hands-on experience needs a "credential". Well, it can be seen both ways. I have learned the hard way that knowing the subject matter well yourself and teaching it to someone else are two very different things. For example, after having maintained my own version of UNIX for 10 y, using this UNIX system for all daily work all this time, administering the system and making plenty of code changes both in the kernel and in various userland components without any outside help (my system is totally divergent from the direction in which the rest of the world has gone), I think I can say that I know UNIX pretty well. However, my attempts to teach UNIX to my significant other and her son have not been very successful. Even though they have already been required to give up Weendoze as a condition of receiving financial and emotional support from me, so if they want to use any computing technology at all, it has to be UNIX or Linux, but that still doesn't give them the motivation to get up from the bed/couch and learn UNIX. Very frustrating. And it isn't just UNIX either: when I tried to teach my S.O.'s son a little bit of high school physics, that didn't go too well either. I guess it depends a lot on the student's motivation. If the student is highly motivated and has a burning desire to learn, that makes the teacher's job so much easier. About 5 y ago a young hacker has contacted me over the 'net (he sought me out, not the other way around) wanting to learn more about 4.3BSD-Quasijarus (my divergent version of Ancient UNIX). He was and still is rather "green" in many ways, but he had and still has a burning desire to learn, and teaching him various technical things ranging from Ancient UNIX to hardware engineering has been a quite pleasant experience, totally different from that trying to teach UNIX to my S.O. and her son. I guess what I'm trying to say is that it's a push vs. pull issue: if someone is actively pulling you for information, it's quite easy to give it to them, but it's much much harder to feed the information in a "push" manner to someone who is passive at best or resistant at worst. It would be absolutely wonderful if every student was internally-motivated and was actively pulling his/her teachers for information, but unfortunately I don't think that's the reality in any school system, even in the best ones like the old Soviet I grew up in. Even if you don't have students who are outright lazy or stupid or categorically disinterested in learning, I don't think it is realistic for a teacher to expect every student to have a burning desire to learn his/her subject. At best you can expect a moderate general interest in learning, but you still have to have the skill and talent of presenting the material in a way that keeps the students interested and motivated. A special talent which I sadly lack. So in summary my view is that you don't need special teaching qualifications to teach the subject of your expertise to the exceptional super-motivated student who is actively pulling you for information, but you do need one to teach the average. > My second chemistry teacher > did not have any teaching credential, had a hard to understand Czech > accent, and was one of the best teachers I ever had in my life. He was a > lead engineer at a chemical plant that makes laundry detergents, on > "emergency loan" to our school. Well, since he was in a lead role at his main job, it is quite likely that his job involved mentoring others, perhaps ones with only moderate motivation, so that's how he had perfected his teaching skills. To me it doesn't matter whethor or not you have a teaching credential as in a piece of paper, but it does matter whether or not you have the ability to teach, which I maintain is separate from knowing the subject matter itself. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: chipscope vs. rerouting signals to test pads/pins
Eric Brombaugh wrote: > There's one little bit of advice you might be able to help with - I'm > running ISE 10.1.03 on a Fedora 9 system and several of the GUI apps are > impossible to run because they're linked against libXm.so.3 which isn't > in any of the standard Fedora repositories. I thought one of those GUI apps was the Webpack installer, and they've made it impossible to bypass it by putting all the bits in encrypted (!) ZIPs. At least this was the case the last time I looked at it in late 2005, and this problem (the inability to bypass the installer) was what made me choose Altera over Xilinx. How did you get around the installer block? MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FWD: Applying for GSoC2009
sha liu wrote: > Test are mostly run on our self-designed low-volume FPGA, but also on other > popular commercial products. Are you saying that you (your university group I guess) have fabbed your own FPGA silicon? Is it open source? Is it comparable in capabilities to the major commercial FPGAs like Brand A or Brand X? As you may know the biggest bone in the throat of Open Source Hardware is the secret nature of the configuration bitstream format for Brand A and Brand X FPGAs. Right now the only way to put your logic design into a programmable logic device that's more capable than a 22V10 is to use closed source software from A or X. One can use open source tools like Icarus Verilog to compile your RTL source into an EDIF netlist, but one still has to then use the FPGA vendor's proprietary closed source software for place&route and the actual bit file generation. We can't make an FOSS replacement for those proprietary tools because the configuration bit format and even more fundamentally the precise internal structure of the FPGA's logic and routing resources are secret. Is ANYONE out there working on making a new FPGA that would be at least somewhat comparable to A & X in capabilities, but have a fully publicly documented internal structure and configuration bit format? MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Building the PCB+GL branch [WAS: Re: Open GL survey (for PCB)]
DJ Delorie wrote: > Actually, four wires all the way out the driveway. I know it's not > the two-wire variety because the last time they had to fix it, they > commented on the fact that I hadn't been "upgraded" to the two-wire > one. I have two lightning protectors in the demarc box, not one. And > yes, it usually throws off the repair guys. Hmm. The fact that you have a "smartjack" demark at all (do you?) suggests to me that it's still an HDSL terminal, albeit the older 4-wire HDSL1 variety. It's still 4 wires like a Classic T1, but instead of each pair carrying 1.544 Mbps in one direction only, each pair carries 1/2 of the T1 in both directions. The smartjack unit has two RS8973 or Bt8970 chips in it, each driving one HDSL pair, an 8953 chip combining them together into the full T1 frame, and whatever other chip is the PHY for the T1 interface presented to the user. On-topic bit for this list: I have gschem symbols for RS8973 -- that's the chip that was taken out of the HDSL system described above and used by itself to make what's called SDSL. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Building the PCB+GL branch [WAS: Re: Open GL survey (for PCB)]
Dave McGuire wrote: > My last two DSL circuits had no voice capability. Ahh, the difference between ADSL and SDSL. One of my pet peeves is people saying "DSL" to mean ADSL... Time to plug my Open SDSL Connectivity Project: http://ifctfvax.Harhan.ORG/OpenSDSL/ Hey, I drew it in gschem originally, so it's on-topic... MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Keyboard shorcuts [WAS: Re: GTK RANT]
Peter Clifton wrote: > Right, next hardware project for DJ then... design a build-it-yourself > kit to build USB HCI HID device with a row of buttons for driving PCB ;) Isn't it easier and cheaper to just buy a Sun keyboard with those L-keys on eBay? I'm using one to type this email. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slotting
DJ Delorie wrote: > The idea I had a while back was to use symbolic pin names in the > symbols, and map symbolic pin names to physical pin numbers as part of > the "heavyification" of the symbol. The physical pin numbers are > added to the symbol at that point. That's exactly how my uEDA handles it. > The syntax for slots would be > expanded, to allow for multiple levels of grouping (like, all nand > gates, then all inputs for each nand gate) - slots vs pin groups, for > example. uEDA's handling of slots is a somewhat more primitive version of what you describe, but it's tied in with the pin name -> pin number mechanism, i.e., there is a mapping from pinname:slot to pinnumber. Not the gEDA way; uEDA has no concept of pinseq. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Wish list, sort of
Mike Crowe wrote: > In my (weak) world view of electrical schematics there exist three types > of data > netlist data - provides component to component connectivity) > graphical data - infomation related to rendering a graphical schematic > component data - additional infomation about the component, not strictly > needed for the schematic (footprint, vendor info, price availability) Ditto, this is also how I view the EDA flow and viewing these three as mostly orthogonal is indeed the philosophy that I have implemented in uEDA/uschem, quite in contrast with gEDA/gaf's approach. But I don't use any databases in uEDA though, the "source code" for a design is all text files to be entered in vi, i.e., the EDA flow is vi and make (and cvs). The component data are entered in the MCL (Master Component List) whereas the netlist and graphical data are captured in the schematic source (.usch) files. The latter have a language designed to keep the different classes of data (netlist, graphical, links to MCL for components) as orthogonal as possible. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: one fix for building under Solaris
der Mouse wrote: > If you mean just the shell written by S. R. Bourne, then > yes, it's not a Bourne shell script, but that's pretty much irrelevant, > because I doubt there's anyone still using the real Bourne code. I do! I am not aware of any user-visible differences in /bin/sh between V7 and 4.3BSD, nor have I changed anything between 4.3BSD and 4.3BSD-Quasijarus. > (Well, anyone who cares about gEDA; I do very much care about free & open source EDA, but gEDA's heavy slant toward too-modern-for-me computing environments has prompted me to write uEDA as a replacement. (As 'g' in gEDA stands for GNU, the 'u' in uEDA stands for UNIX!) > there are probably a few people > running V9 on real PDP-11s and the like.) So in your mind V9 on a real PDP-11 "counts" but 4.3BSD-Quasijarus on a real VAX doesn't? Why? MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: a pcb level panelizer tool
Ales Hvezda <[EMAIL PROTECTED]> wrote: > PS. I've tolerated it until now (threshold reached), but please stop > posting HTML to this list. Please post plain text only messages to the > geda-* mailing list. Yes, this policy is described here for all the > geda-* lists: > [...] > * Do NOT send messages to any gEDA list in HTML. Plain text only please! Why is this policy not enforced with demime on the list stripping/blocking all HTML, base64, attachments and other garbage? MS, who believes that sending HTML E-mail is the most heinous offense one can commit, far more serious than murder. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: the peril of ascii file formats
John Griessen <[EMAIL PROTECTED]> wrote: > How are your non-X11 schematic methods coming Michael? cvs -d :pserver:[EMAIL PROTECTED]:/fs1/IFCTF-cvs co ueda It's coming along. The project has been on hold for a while as I've been dealing with other life priorities, but I'll be able to resume it soon now that my data centre move is complete. > Do you have a > way to tie in your preferred ascii-art schematics with netlist creation? Oh yes, it's tied in with netlist creation very well, although my schematics aren't ASCII art, they are non-WYSIWYG PostScript. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: the peril of ascii file formats
DJ Delorie <[EMAIL PROTECTED]> wrote: > Today I sat down to work on my latest project. Next step, rearrange > some of the signal wires. I type "vi mcu.sch"... er, no, > backspace... "gschem mcu.sch", yeah, that's right. What's wrong with "vi mcu.sch"? I personally find that a heck of a lot easier than fiddling around to start an X11 display... MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: uEDA .. was .. Re: Heavy Symbols and such
al davis <[EMAIL PROTECTED]> wrote: > Why invent a new language? Either Verilog-AMS or VHDL-AMS, the = > structural subset, has everything you need. I needed something I could implement by myself without any help from the outside world and without any dependencies. It also needs to run under UNIX Version 7 and cannot depend on anything other than a K&R C compiler plus standard UNIX stuff that came with V7 (such as M4 that everyone hates so much but which I absolutely adore). The uEDA distribution tarball (source + documentation) weighs 35032 bytes. Small is beautiful. The Original UNIX way. Quoting from uEDA documentation: First a disclaimer is in order. Different people write Free Software based on different motivations. Like most Free Software written by Michael Sokolov, uEDA is based on the "scratching a personal itch" development model. In other words, I have written the software to satisfy my own internal need, and I don't really care if you like it or not. Please keep this observation in mind as you discover that it lacks some feature you need or want, or that its flow is not to your liking. I have written it to satisfy *my* needs. I could have written it for myself and never released it, but I believe in sharing and letting others have what I have (though whether they like it or not is not my concern). So there you have it. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Bob Paddock <[EMAIL PROTECTED]> wrote: > The BOM should be the master document that populates everything. > > [...] > > Obviously people on this list are dealing with schematics and PCBs, > so we tend to think of the schematic as the "master", > but in the contracting environment the BOM is what rules everything. Yes, you've hit the nail right on the head! That's exactly how I do it in uEDA, gEDA's evil twin. In uEDA the master source code for a board is an ASCII text file named MCL, which stands for Master Component List. It is not a generated file and it isn't edited by any GUI, instead you create and edit it in vi and source-control it with SCCS/RCS/CVS/pick-your-favourite. The MCL is where you enter footprints, cap & resistor values, orderable part numbers, etc. uEDA has no GUI though, *all* design entry is done in vi. When the uEDA suite is complete, you'll be able to enter your design in vi, then run 'make' and get: * A bundle of M4-generated PCB footprints to hand over to your PCB layout contractor; * Various BOM forms (the MCL is a BOM in itself, but there are other BOM forms too that can be generated from it); * Printable schematics in PostScript; * Netlist file to be loaded into PCB (by you or your layout contractor). The first 2 bullet points are there already, the last 2 aren't there yet. I plan to implement the latter by designing a gschem-like ASCII-based "schematic source code" format, but with one critical difference from the gschem one: instead of attributes in the schematic source file itself, all that information will be taken from the MCL. The complete source code for a board will thus consist of the MCL, the *.usch schematic source files (one per page just like gschem's *.sch) and the Makefile. The MCL and the Makefile form the top-level notion of "project" which some people complain the gEDA suite lacks. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: M68K bus and transmission line ringing
Mark Cianfaglione <[EMAIL PROTECTED]> wrote: > It's reasonably loaded. Too low a load was bad as the drivers of the > processor were hefty so the overshoot and undershoot were nasty unless you > dampened them with series resistors. Ah, good to know. > On heavily loaded systems (like yours) it's not really a huge issue > although we would as a precaution put them in on the address and control > lines anyway on certain designs. OK. > (I design telecom equipment so it had to run for 20 years as designed.) My hat off! The gadget I'm building is for telecom too, although of the hobbyist variety. I'm a hobby telecom nut. > You would probably see ringing on the other chips if there is any. One > saving grace in your situation is your bus speed. I currently have 16.67 MHz processor parts on hand, so that's the speed I'm going to run at initially. MC68302 at 16.67 MHz *might* be fast enough to serve a 2.3 Mbps line (theoretical maximum data rate for SDSL) in which case I would be all set, but I would also like the have the option of populating a 25 MHz processor part and running it at 25 MHz. Are you saying that 25 MHz is slow enough that the ringing will die out before the receiver latches the data? Or should I not count on that? > In reality the control > signals have to be beautiful. Yeah, that's what I was thinking too. Now consider this: as you may remember, M68K puts out UDS, LDS and R/W signals and external combinational logic is needed to turn them into OE and WE that normal chips can use. This aspect is unchanged in MC68302. (I'm not using the LC302 version as I use all 3 SCCs.) What if I place my combinational read/write strobe decoder right next to the 302, have the UDS, LDS and R/W traces run only between the 302 and this decoder (plus the required pull-ups), and have only the decoded signals disperse to the rest of the board. Where should I put the series resistors: on the 302 native control signals or on the decoded ones? Am I correct in thinking that the series resistors should go on the decoded signals? Those have the benefit of being strictly unidirectional w/o pull-ups. With the decoder the control outputs from the 302 will not be heavily loaded at all. However, they won't run very far either. Will they be OK w/o resistors? My read/write strobe decoder consists of an LS00 and an LS04; I've been told that the lower impedance of TTL inputs helps dampen the ringing; is that true? There are two other control signals I'm worried about: AS (address strobe) and DTACK. AS should not be needed on a non-multiplexed bus, but the SDSL chip wants it nonetheless, so I'll be pulling the net into the SDSL part of the board. On my current schematic the M68K_AS net interconnects the MC68302, the SDSL chip and a pull-up resistor. As I've already explained, the SDSL chip has rather inflexible placement and will probably be a bit away from the 68302 subsystem. I should therefore put a series resistor on this net, right? Am I correct in thinking that after the 302 I should have the pull-up first, then the series resistor, than the long-ish trace to the SDSL chip? See further below about DTACK. > The address can be loud as long as it > settles before the minumum setup time but as it's a single source (unless > you are doing DMA) I'm not doing any external DMA; all my M68K bus cycles will be initiated by the MC68000 core or the internal DMA engines in the MC68302. But consider this: MC68302 has a bunch of on-chip peripherals (both masters and slaves) connected to the M68K bus internally besides the MC68000 core, and it has a single continuous M68K bus both on- and off- chip. From the transmission line perspective do I need to take into account that the chip acts as both a driver and a receiver on each net for every transaction (via different internal functional units), or does the chip have buffers at the pads which hide all that internal mess? Does anyone know the answer to the last question specifically for MC68302? In other words, can I still treat the address bus as single-source even though there are two different units inside the chip which can drive it? And do I need to worry about other internal units listening and decoding as the MC68000 core drives? > it can be controlled by series terminations at the > processor. OK, I think I can do this. > The data is a little harder to control as it's a multi source > bus. Essentially the strongest signal on the bus will be the worst quality > to the other devices. I'm wondering if I can get by without resistors on the data bus and live with the ringing if I ensure that the control signals are pretty. If the ringing takes too long to die out, I suppose I can run with nonzero wait states -- I wouldn't want that in the finished product, but it's still better than throwing the first batch of boards out completely. > I hope I've added to your body of knowledge...;-) Certainly! I very much appreciate it! Bob Paddock <[EM
gEDA-user: M68K bus and transmission line ringing
Hello fellow gEDA/pcb users, I know there are a few old-timers on this list (by that I mean hardware engineers of old school), and my question is directed to those. Would anyone here happen to experience designing a system with the good old Motorola MC68302? (It's an old-school telecom processor, if I'm not mistaken it's an early 1990s chip, but it most perfectly fits the late 1980s computing and communications environment, the era of MicroVAXen. Has the most classic original 68000 core inside.) I'm using MC68302 on my SDSL board, and I'm now in the process of putting the finishing touches on this design before sending it off to a layout contractor. Here is my area of concern: my current schematics (see http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/) have the M68K bus interconnecting the MC68302, RAM, flash, the SDSL transceiver's microprocessor control port and the FPGA. I have pull-up resistors on the bidirectional control signals (AS, UDS, LDS, DTACK). But I don't have any series resistors yet, and I wonder if I should add some, and if so, where? I've been told that when a sufficiently fast-switching signal is driven onto a sufficiently long net, one has to worry about this signal ringing due to transmission line effects. That of course raises the question of just how fast it needs to be and just how long do the traces have to be for the issue to become a concern. I've been told that my MC68302 running at 16 to 25 MHz is fast enough, and that traces running half-way across my 130x165 mm board would be long enough that I do need to worry about this stuff. I've been told that the solution is to insert series resistors of ~30 Ohm into the nets close to the source. Here are my questions which I hope might be answered by someone who has some experience with MC68302 or any M68K-based design: * Does the MC68302 in fact produce slew rates fast enough on the M68K bus signals it drives (address bus, data bus on writes, control signals) for the designer to be worried about transmission lines ringing? * As I've mentioned before, my design will be laid out on a 130x165 mm PCB. I can probably get the core microprocessor subsystem (MC68302, RAM and flash) fairly close together in one corner, but I also need the bus to go to the SDSL transceiver chip. The latter is a mixed signal IC and its physical placement is rather inflexible as it's a critical component standing on the boundary between the digital and analog sections of the board. The latter requirement would probably mean that my M68K bus traces *will* run half-way across my PCB. Is running half-way across a 130x165 mm PCB long enough for me to be worried? * If the answers to the previous two questions are affirmative (i.e., that I do have a transmission line ringing issue which needs to be addressed), what's the proper way to address it? Would series resistors take care of it? If so, exactly where should I put them? On the address bus? On the data bus? On the control signals? * I've been told that the series resistors I'm talking about go right after the source. But where is the source on a bidirectional multipoint net? Take the data bus for example: it's bidirectional and goes to multiple peripherals. Series resistors between the MC68302 and the main bus nets would take care of writes, but what about reads? I hope someone can give me some insight, preferably backed by some actual experience with M68K designs. TIA a lot, MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB mounting holes for metric screws
Hello fellow gEDA/pcb users, I've got a PCB mechanical design question. I have given up on the idea of copying the form factor of EN routers (basically I don't really like that form factor) and I'm going for a form factor of my own. However, being a proud citizen of the Union of Soviet Socialist Republics, I want to make my form factor all metric -- the Soviet national standards body required that for all new designs and my own sense of taste does the same. :-) I've speced my board dimensions in metric (130x165 mm) and I'll have mounting holes for metric screws, some M3 and some M4. My question is about the latter: I've been told that the drill diameter should be 3.1 mm for an M3-accommodating PCB hole and 4.2 mm for an M4-accommodating one; is this correct? But what about the copper annulus? What would be a good copper annulus for those screw-accommodating holes? Assume the "typical" kind of screw used to secure PCBs to enclosures. TIA, MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Surface mount LEDs
Hello gEDA/PCB users, I'm looking for some surface mount LEDs, specifically a 1206-sized (or thereabouts) green LED and a 1210-sized (or thereabouts) bicolor red/green LED, both shining upward from the PCB (i.e., not right angle). Would prefer for the two to be somewhat matched, i.e., from the same family. I wonder, would anyone here have a part they can recommend? I.e., one for which there is: a) a good PCB footprint; b) a part number orderable from somewhere; c) an indication of which side is the anode and which is the cathode; d) for the bicolor LED, knowledge of which one is red and which one is green. I want to connect the green one to the DSR modem control signal and the red one to an error signal on my SDSL board, so I'd like to know which is which by some way other than connecting it randomly on the PCB, firing it up and observing the color. TIA, MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: interesting links
Ales Hvezda <[EMAIL PROTECTED]> wrote: > However, if you are going to write an free software EDA tool in > any language (of your choice), then by all means, discuss here to your > heart's content Really? Does this mean that discussion of uEDA and uschem would be on-topic here? At least the uEDA flow shares *some* parts in common with gEDA... MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: First release of uEDA
I have just made the first very very alpha release of uEDA. uEDA is envisioned to do for the 4-capital-UNIX culture what gEDA has done for the GNU/Linux culture, but right now it does just two things: * Provide an alternative to gsch2pcb for getting footprints into PCB; * Provide a nice (IMO) set of BOM management tools. uEDA fully embraces the UNIX philosophy that revolves around vi and make for scripted, iterative, non-WYSIWYG flow, and it also embraces M4, just to piss off those who hate it so much. :) I have ported PCB's M4 footprint library from GNU M4 to the original UNIX M4 as part of this project. uEDA does not currently replace gschem or PCB but works with them, which is why I feel that it's OK for me to post it on this mailing list. In the future however I plan to replace gschem with uschem, a non-WYSIWYG schematic capture system in which schematic entry would be done in vi and graphical schematics would be generated in PostScript by a batch program similar to the non-WYSIWYG text formatters like troff or TeX. I do plan to stick with PCB though, except perhaps for making a port of it to Ancient UNIX with X11R4 and Motif instead of Lesstif. uEDA release 0.1 can be downloaded via anonymous FTP: ifctfvax.Harhan.ORG:/pub/hweng/ueda-0.1.tar.Z (That is not a URL, it's a file location spec from the golden pre-WWW days.) An example project that uses gschem, PCB and uEDA for footprint generation and for the BOM is my SDSL board, work in progress which can be checked out with: $ cvs -d :pserver:[EMAIL PROTECTED]:/fs1/IFCTF-cvs co OSDCU Enjoy or be horrified as you like! MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: simulation advice
[EMAIL PROTECTED] wrote: > It recently took me five minutes to sweet-talk openoffice into > letting me type "MHz" correctly. Yet another reason to use vi and troff instead of OO. > Good thing for me I rarely use word processors of any kind. > I'm a TeXhead from way back. So why were you using OO rather than TeX then? MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Lab Equipment
> Does he still use ABEL? > The last edition I saw did, but also had some VHDL. Dunno, I only have the 2nd edition (1994 or so IIRC). MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Lab Equipment
_Digital Design: Principles and Practices_ by John Wakerly is my favourite. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Flame about XML (was: Some footprints I tried to create)
Dave McGuire <[EMAIL PROTECTED]> wrote: > I remember "back in the good old days" when it was considered a > good thing to be self-sufficient. ;) I believe in that too and I do strive to be self-sufficient whenever I reasonably can. If I didn't strive to be self-sufficient, I wouldn't be maintaining my own operating system and underlying HW platform, and most pertintent of all to the present discussion, if I didn't strive to be self-sufficient to some serious extremes, I most certainly wouldn't be building my own SDSL CPE, I would just use the ISP-provided router, so there would be no PCB for me to lay out in the first place. But unfortunately I can only take it so far. I have a very busy life with gazillion things competing for my time and attention, and learning the art of PCB layout, as interesting as it would be I'm sure, is unfortunately more than I can take upon myself at the present time. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Flame about XML (was: Some footprints I tried to create)
Stephen Williams <[EMAIL PROTECTED]> wrote: > So I am noticing that your refusing to use modern tools just > because they are modern has rendered you unable to do your tasks > yourself. > > That's fine, of course, because that other person [...] > gets your money. OK, so if you ever develop, say, a tumor that needs to be surgically removed, you are going to cut it out yourself rather than pay a surgeon to do it, right? MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Flame about XML (was: Some footprints I tried to create)
Dan McMahill <[EMAIL PROTECTED]> wrote: > vi layout.pcb > pcb -x gerber layout.pcb Thank you, Dan, for expressing it so succinctly! This is exactly how I use PCB at the present moment. Of course it would be just a tad too difficult to do the whole layout this way, but that's exactly why I plan on hiring someone else to do the layout for me while insisting that it be done in GNU PCB rather than some proprietary package: while the layout itself is a job too visual for my ASCII brain and it's just simply a job that I feel someone else would do gazillion times better than me, having it in the text-based PCB format would allow me to do any necessary minor tweaks afterward by the very method that Dan has just demonstrated. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Flame about XML (was: Some footprints I tried to create)
Steve Meier <[EMAIL PROTECTED]> wrote: > Does this include only 1979 and earlier components? No, just the philosophy, paradigm, world view and way of thinking, not necessarily the components. What matters is not the date code stamped on the chips or the release date of a piece of software or whatever, but the underlying philosophy and scale of moral values. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Flame about XML (was: Some footprints I tried to create)
Peter Baxendale <[EMAIL PROTECTED]> wrote: > What a wimp. What's wrong with ed? Nothing wrong. I do use ed too sometimes, as well as ex. Vi is just a mode in ex, and I use ex a lot, in both command and vi modes. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Flame about XML (was: Some footprints I tried to create)
Dave McGuire <[EMAIL PROTECTED]> wrote: > Sure, you can always fork. But as DJ pointed out...how, exactly, > are you running PCB on an ASCII terminal? I don't. I plan on hiring someone else to do the layout when I get to that stage. But I want to do all preceding steps first using my scripted text-based Ancient UNIX environment. And just for completeness, I do have access to an X11 graphical display for when I really need one. I just don't *like* using it. When a tool requires the use of a GUI for a task that *could* be done in a scripted text-based environment, it hampers my productivity. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Flame about XML (was: Some footprints I tried to create)
Steve Meier <[EMAIL PROTECTED]> wrote: > My overall impression of > this is that I propably won't be influenced by your oppinions. I don't care. As I've said, I can always fork. I'm already used to maintaining my own versions of virtually everything I use, starting with the OS and the underlying hardware platform. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some footprints I tried to create
Steve Meier <[EMAIL PROTECTED]> wrote: > The only tool ever needed is a > > 2LBs Claw I disagree: there is one more tool needed. What tool can one possibly need besides a hammer? Can anyone guess? A sickle of course! That's a no-brainer. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Flame about XML (was: Some footprints I tried to create)
Steve Meier <[EMAIL PROTECTED]> wrote: > I really am interested in why or why not going with XML? How would I use XML with punched cards or paper tape? > So a few more details would be nice. OK, here are a few more details about me for you to mull over. I have been called things like "Neo-Amish" or "Techno-Luddite". I am fundamentally and totally against all forms of modern technology. I do not have a personal computer and never will, for as one of my heroes Ken Olsen has said, "There will never be a need for any individual to have a computer in their home." My computer is a mainframe housed in an underground bunker which I access remotely from ASCII terminals around the world. ASCII text terminals in 80 columns of course. Well, OK, it is not truly a mainframe in the IPM EBCDIC sense, it's a UNIX system, but I call it a mainframe because I use it in the centralised computing access-through-terminals paradigm. It runs my own version of UNIX (4.3BSD-Quasijarus) which is very very close in both spirit and code to the original PDP-11 UNIX Version 7. (The hardware platform is based on a VAX CPU, but it has been put together specifically to run 4.3BSD-Quasijarus. It has never run VMS or any other OS.) I fully and totally embrace the computing philosophy and world view of the 1970s that has produced my OS of choice. I worship ed, sed, awk and m4. No Perl, no Python, no XML, none of those latter-day abominations. It is all a conscientious choice. I can't stress this point enough. I was wetting diapers and sucking my mom's breasts when UNIX Version 7 was current, so it is not like that was my first computing platform and I then never evolved. I have used DOS and Windows 3.1 in the past (so long ago though that it's basically a past life), and even that abomination called Micro$oft Word (for DOS), all before I had discovered UNIX. Now regarding my choice of UNIX. My first encounter with UNIX was in 1995 upon coming to USA with my parents (at age 15.5). My decision to forego "modern" UNIX and opt for the V7-like 4.3BSD didn't come until around 1998. Obviously a very deliberate and conscientious choice; in 1998 there was plenty to choose from: Linux, modern *BSD, you name it. But I have chosen the 1970s technology, philosophy and paradigm. *HAVE CHOSEN* are the operative words. > Also, which office suite do you use? Pen and paper usually, sometimes a manual typewriter. Seriously though, I have absolutely no need for an office suite. Writing papers: 99% of the time I write them in plain text files in vi. On those special occasions that call for fancy formatting with non- teletype fonts etc. I use troff, a non-WYSIWYG text formatter that takes source code in a text formatting programming language on stdin and emits PostScript on stdout. (I only use PostScript printers of course, and only the large "workhorse" type like HP LaserJet 4Si or 5Si, Digital PrintServer series, etc.) Spreadsheets: no need for them. I do math the way every Soviet kid has been taught in elementary school: columnar addition, subtraction and multiplication, long division. Works equally well on a piece of paper, on the brown chalkboard, or in an ASCII text file in vi. There is also dc(1), with or without the bc(1) front end, and the good old TI-85 calculator for problems complex enough to where messing with the calculator is easier than doing the math in my head or a scrap piece of paper. If I ever have a need to get really fancy and need functionality like formulas in spreadsheets where one can change inputs and everything recalculates automatically, I'll just whip up an awk or m4 script for the problem at hand. Need to have the output professionally presented along with text etc? No problem, just whip up another script or Makefile that takes the math data, combines it with other stuff (cat(1) or include directives should do the job) and feeds it into troff. Think outside the box. You don't need an office suite just because you think you need one. People in 1970s did just fine without office suites, and so do I. Same for XML. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some footprints I tried to create
Steve Meier <[EMAIL PROTECTED]> wrote: > Why? Because given a *choice* between an XML-based tool/format and a non-XML- based one, I'll choose the latter. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some footprints I tried to create
Steve Meier <[EMAIL PROTECTED]> wrote: > And while I am at it. I would like to see all of the geda and pcb text > files get converted to xml. I would have to fork if this were ever done. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: freedog pictures
Stuart Brorson <[EMAIL PROTECTED]> wrote: > Actually, I've often thought that we should advertise gEDA to the big > chip guys as a method to distribute reference designs -- schematics, > layouts, and Gerbers. Yeah, right... When you find a chip vendor like that, please let me know. Anyone care to guess what kind of "reference design" I have received from the vendor for the chip in my design (RS8973 HDSL/SDSL transceiver)? They gave me an encrypted ZIP and refused to tell me the password, requiring me to expend 5 months of CPU time to crack it by brute force (trying all 95 printable ASCII chars including space, turned out to be 7 chars long). You can read the full gory details here: http://ifctfvax.Harhan.ORG/OpenSDSL/mindspeed.html MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint for an SMT chip resistor array
John Luciani <[EMAIL PROTECTED]> wrote: > I would go for the concave terminations. The concave may be easier to > hand solder > on small pads. Thanks John, I'll put the EXBV8V with concave pads in there, using the M4 pcblib footprint. (Of course this is all very preliminary -- written with forks on water as we say in Russia -- until the layout is actually done.) MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint for an SMT chip resistor array
Dan McMahill <[EMAIL PROTECTED]> wrote: > take a look in the ~panasonic library for footprints like > PANASONIC_EXB14V. Those are the panasonix EXB series of SMT resistor > arrays. Thank you Dan, that's exactly what I was looking for! And they are M4 footprints, yay! I love M4! I adore M4! (Right now I'm in the process of reworking pcblib to work with The Real Thing, Dennis Ritchie's original M4 from UNIX Version 7, instead of GNU M4. I can't stand cheap copycats.) A question though. Looking at this family of footprints and the corresponding pages of the Digi-Key catalog, I see that I have a number of choices. EXB18V, EXB28V, EXB38V, EXBN8V and EXBV8V will all do the job. EXB18V is a bit too small for me, so I'll exclude it from my consideration, and I have yet to decide whether I want the smaller 28V/N8V or the larger 38V/V8V. But the really tough one to decide for me is whether to go with the 28V/38V style or the N8V/V8V style. Would anyone happen to have a suggestion as to which is generally better / easier to work with etc? Thanks, MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: cut and paste between designs in PCB, gschem
John Griessen <[EMAIL PROTECTED]> wrote: > Is there a way to get something like that in PCB now? I can't see one. > The way I would like to have is to open two windows of PCB, each with a > different netlist loaded or none, and be able to copy to a buffer, and paste > in the other window. I second the feature request. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Footprint for an SMT chip resistor array
Hello fellow gEDA/PCB users, I wonder, does anyone have a footprint for an SMT chip resistor array with 4 isolated resistors? I don't know how those footprints are called (which is why I'm unsure what to look for), but such resistor arrays can be found on many many digital boards. I don't have a specific part picked out and I can use just about any part in the Digi-Key catalog with any reasonable footprint, so I'd like to reverse the problem of making the footprint for a part and look for an existing PCB footprint that I like and then pick a Digi-Key part that'll fit it. So, does anyone have a footprint for ANY SMT chip resistor array of the kind that I've described (8 pins, 4 resistors)? (Yes, I know that drawing footprints is not as scary as it seems, but again I'm completely flexible in my choice of parts and don't have any other basis for choosing my footprint, so why not make existing PCB footprints my choice criterion.) TIA, MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
