Re: gEDA-user: Icarus verilog Synthesis
Hi, Does any one know about any book that describes how to convert a behavioral code into unoptimized gate level netlist. I know that after an unoptimized gate level netlist is got logic synthesis is applied to get an optimized netlist. I have a book called Algorithms for VLSI Design Automation. It has a chapeter on high level synthesis. But it doesnt explain my above question. I am looking for a book that for example describes how a for/while/repeat/forever and other verilog behavioral constructs are converted to multiplexors/and gates etc. Regards, Ronald On 9/5/10, Ronald Mathias <[1]ronnie.math...@gmail.com> wrote: Hi, Thanks a lot. Regards Ronald Mathias On 9/4/10, Philipp Klaus Krause <[2]...@spth.de> wrote: Am 04.09.2010 06:19, schrieb Ronald Mathias: > > >I transform the Verilog code containing behavioral statements into >verilog code that contains only gate level instantiations. This is >passed as input to ABC Logic synthesis tool. Finally the >output generated by ABC is passed to Versatile Place and Route(VPR) >program which generates the bitstream. You don't have to go down to gate level: Simple verilog, (e.g. still allowed to use '+', '-', but not '*', etc) can be read by vl2mv, you can the use vis to flatten the resulting blif-mv into blif, which can be read by abc. This is the way I currently do synthesis (for a simulated asic, directly writing the simple verilog vl2mv understands; the resulting gate level verilog is then simulated in Icarus to get timing). Philipp ___ geda-user mailing list [3]geda-u...@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:ronnie.math...@gmail.com 2. mailto:p...@spth.de 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus verilog Synthesis
Hi, Thanks a lot. Regards Ronald Mathias On 9/4/10, Philipp Klaus Krause <[1]...@spth.de> wrote: Am 04.09.2010 06:19, schrieb Ronald Mathias: > > >I transform the Verilog code containing behavioral statements into >verilog code that contains only gate level instantiations. This is >passed as input to ABC Logic synthesis tool. Finally the >output generated by ABC is passed to Versatile Place and Route(VPR) >program which generates the bitstream. You don't have to go down to gate level: Simple verilog, (e.g. still allowed to use '+', '-', but not '*', etc) can be read by vl2mv, you can the use vis to flatten the resulting blif-mv into blif, which can be read by abc. This is the way I currently do synthesis (for a simulated asic, directly writing the simple verilog vl2mv understands; the resulting gate level verilog is then simulated in Icarus to get timing). Philipp ___ geda-user mailing list [2]geda-u...@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:p...@spth.de 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus verilog Synthesis
Hi,
Thanks for the response. I was under the impression that Icarus was
moving towards synthesis capability.
I have the 0.8.1 Icraus version with me. I have made the source code
compilable in Visual Studio 2005 though its not fully complete.
May I know the reason as to why synthesis capability is being dropped ?
I am really interested in making Icarus synthesizable.
Here is my idea:
I transform the Verilog code containing behavioral statements into
verilog code that contains only gate level instantiations. This is
passed as input to ABC Logic synthesis tool. Finally the
output generated by ABC is passed to Versatile Place and Route(VPR)
program which generates the bitstream.
Regards,
Ronald
On 9/4/10, Stephen Williams <[1]st...@icarus.com> wrote:
What are you trying to do? Are you really trying to "synthesize"
your
Verilog design, meaning you are trying to generate a bit stream to
load into your FPGA? Or are you trying to compile and simulate your
Verilog?
Icarus Verilog is mostly a *simulator*, not a synthesizer. There
were
some synthesis capabilities back in the 0.8 release, but that
support
has been largely dropped in the 0.9 releases or current devel
branch.
Verilog code generator? OK, this suggests that you really are trying
to *synthesize* (and not simulate) and no, not even the 0.8 release
supported synthesis of user defined tasks.
Ronald Mathias wrote:
>Hi,
>
>
>
>I have written a verilog code that makes use of a user defined
task to
>do some computation. The task takes two parameters as input and
one
>parameter as output.
>
>
>
>When I try to synthesize it, I get the following error:
>
>
>
>internal error: NetProc::nex_output not implemented on object
>type NetUTask
>
>internal error: NetProc::nex_output not implemented on object
>type NetUTask
>
>Does this mean that icarus verilog has not yet support for
synthesis of
>user defined tasks?
>
>When I try to send the elaborated netlist to the verilog code
generator
>back end, the task definition is missing from the output.
>
>Is this a bug or the verilog code generator backend is still
not
>completely implemented ?
>
>Regards,
>
>Ronald
--
Steve Williams"The woods are lovely, dark and deep.
steve at [2]icarus.com But I have promises to keep,
[3]http://www.icarus.com and lines to code before I sleep,
[4]http://www.picturel.com And lines to code before I sleep."
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References
1. mailto:st...@icarus.com
2. http://icarus.com/
3. http://www.icarus.com/
4. http://www.picturel.com/
5. mailto:geda-user@moria.seul.org
6. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
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gEDA-user: Icarus verilog Synthesis
Hi, I have written a verilog code that makes use of a user defined task to do some computation. The task takes two parameters as input and one parameter as output. When I try to synthesize it, I get the following error: internal error: NetProc::nex_output not implemented on object type NetUTask internal error: NetProc::nex_output not implemented on object type NetUTask Does this mean that icarus verilog has not yet support for synthesis of user defined tasks? When I try to send the elaborated netlist to the verilog code generator back end, the task definition is missing from the output. Is this a bug or the verilog code generator backend is still not completely implemented ? Regards, Ronald ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Chortle: A Technology Mapping Program for LookupTable-Based Field Programmable Gate Arrays
Hi, Thanks a lot. This is actually what I was looking for. Regards, Ronald On 7/13/10, Andy Fierman <[1]andyfier...@signality.co.uk> wrote: I reached much the same place ... Is this it? "Chortle-Technology Mapping for Lookup Tables (ZIP File)" on this page: [2]http://www.eecg.toronto.edu/~jayar/software/software.html Otherwise try contacting Jonathan Rose directly. Andy [3]signality.co.uk On 13 July 2010 15:27, John McCaskill <[4]jhmccask...@fastertechnology.com> wrote: > Here is a web page for one of the papers authors: > > [5]http://www.eecg.toronto.edu/~jayar/Welcome.html > > I saw Chortle mention on his pages, but not the source code for it. He > did have source code for other projects he is working on, so maybe he > can get you a copy. > > > Regards, > > John McCaskill > Faster Technology LLC > Xilinx Authorized Training Provider and Alliance partner > 1812 Avenue D, Suite 202, Katy, TX 77493 USA > Tel: (281) 391-5482, Fax: (281) 391-9384 > Email: [6]jhmccask...@fastertechnology.com > Web: [7]http://www.fastertechnology.com > > >> -Original Message- >> From: [8]geda-user-boun...@moria.seul.org [mailto:[9]geda-user- >> [10]boun...@moria.seul.org] On Behalf Of Ronald Mathias >> Sent: Monday, July 12, 2010 11:15 PM >> To: [11]geda-u...@moria.seul.org >> Subject: gEDA-user: Chortle: A Technology Mapping Program for > LookupTable- >> Based Field Programmable Gate Arrays >> >> Hi, >> >> Could any one tell me from where I can download the source code for >> Chortle: >> A Technology Mapping Program for Lookup Table-Based Field Programmable >> Gate >> Arrays program. >> >> I have tried searching for it on google. I only get the pdf file that >> describes the program but I am unable to find its source cde. >> >> Regards, >> Ronald > > > > ___ > geda-user mailing list > [12]geda-u...@moria.seul.org > [13]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list [14]geda-u...@moria.seul.org [15]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:andyfier...@signality.co.uk 2. http://www.eecg.toronto.edu/~jayar/software/software.html 3. http://signality.co.uk/ 4. mailto:jhmccask...@fastertechnology.com 5. http://www.eecg.toronto.edu/~jayar/Welcome.html 6. mailto:jhmccask...@fastertechnology.com 7. http://www.fastertechnology.com/ 8. mailto:geda-user-boun...@moria.seul.org 9. mailto:geda-user- 10. mailto:boun...@moria.seul.org 11. mailto:geda-user@moria.seul.org 12. mailto:geda-user@moria.seul.org 13. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 14. mailto:geda-user@moria.seul.org 15. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays
Hi, Could any one tell me from where I can download the source code for Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays program. I have tried searching for it on google. I only get the pdf file that describes the program but I am unable to find its source cde. Regards, Ronald ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Books on RTL synthesis algorithms
Hi, I just wanted to know if anyone knows any good books that describe RTL synthesis algorithms. I know about books on Logic synthesis. Logic synthesis books only describe about optimizing gate level descriptions. I am not interested in them. I am particularly interested in what algorithms are used to convert a RTL level description into gate level description. Any pointers in this directions. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Structure of Iverilog Windows Version
Hi, I have downloaded the windows version of icarus verilog version 0.8.1.7 from [1]http://bleyer.org/icarus/. When I install the executable, I get the executable vlpp.exe ivl.exe. in the lib\ivl directory. I know that vlpp.exe is the preprocessor. But I do not know what is ivl.exe used for. When I run ivl.exe separately, using the -h option the output is similar to vlpp.exe. What is ivl.exe and what is it used for? Is it like a backend for iverilog.exe? Regards, Ronnie References 1. http://bleyer.org/icarus/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
